WO2007110959A1 - Process for producing semiconductor device - Google Patents

Abstract

The occurrence of a failure during plug formation is inhibited. A structure comprising alumina films and an interlayer dielectric sandwiched therebetween is formed (steps S3 to S5). Then, contact holes passing through these layers are formed (step S7). Thereafter, annealing is conducted in an inert-gas atmosphere or a vacuum for a given time at a given temperature (step S8), and the contact holes are sufficiently degassed. Thus, degassing of the contact holes during tungsten plug formation is inhibited and the contact holes can be inhibited from coming to have a part not filled with a tungsten plug. Therefore, a semiconductor device can be realized which has an interlayer contact structure having low resistance.

Description

 Manufacturing method of semiconductor device

 Technical field

 TECHNICAL FIELD [0001] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a strong dielectric capacitor having an interlayer outer structure. Background art

 In recent years, attention has been focused on using a ferroelectric film such as lead zirconate titanate (PbZr Ti 2 O 3, ΡΖΤ) as a dielectric film of a capacitor. Ferroelectric memory (Ferro-electric Random Access Memory, FeRAM) using such a ferroelectric capacitor is capable of high-speed operation, low power consumption, excellent write Z read durability, etc. In the future, further development is expected.

 [0003] By the way, the ferroelectric film has the property of being easily deteriorated by moisture and hydrogen entering from the outside, or moisture and hydrogen generated in the formation process of the interlayer film and FeRAM. . For this reason, in normal FeRAM, the wiring layer of the ferroelectric capacitor is covered with an aluminum oxide (alumina, Al 2 O 3) film to block moisture and hydrogen from reaching the ferroelectric capacitor.

 twenty three

 (For example, see Patent Document 1).

[0004] Furthermore, in addition to the surface of a ferroelectric capacitor, a structure in which a flat alumina film is formed as a moisture or hydrogen block film between different wiring layers has recently been used.

 Patent Document 1: Japanese Patent Laid-Open No. 2005-268617

 Disclosure of the invention

 Problems to be solved by the invention

However, when an alumina film as a moisture or hydrogen block film is used between different wiring layers, there are the following problems.

 FIG. 29 is a schematic cross-sectional view of an essential part of an example of an interlayer contact structure, and FIG.

[0006] The lower wiring 200 and the upper wiring 201 are connected by a tungsten (W) plug 202. Yes. For example, the lower wiring 200 has a laminated structure of an aluminum (A1) film 200a, a titanium (Ti) film 200b, and a titanium nitride (TiN) film 200c, and an aluminum film 203 is formed on the surface of the lower wiring 200. Has been. An interlayer insulating film 204 is formed on the alumina film 203, and further an interlayer insulating film 206 is formed via the alumina film 205. Then, a W plug 202 is formed through the two layers of interlayer insulating films 204 and 206 and the two layers of alumina films 203 and 205, and an upper layer wiring 201 is formed thereon.

In the case of forming such an interlayer contact structure, first, as shown in FIG. 30, after forming the lower layer wiring 200 and the alumina film 203, the interlayer insulating film 204, the alumina film 205, and the interlayer insulating film 206 are formed. The contact holes are formed in order, and through them, the contact hole reaching the lower layer wiring 200 is formed. Then, as shown in FIG. 29, the contact hole is filled with W using a CVD (Chemical Vapor Deposition) method to form a W plug 202, and an upper wiring 201 is formed thereon.

 However, after the contact hole is formed and before the W plug 202 is formed, the interlayer insulating films 204 and 206 may absorb moisture depending on the processing environment between them, especially when cleaning is performed after the contact hole is formed. Such moisture absorption is likely to occur (in the figure, arrows in the directions of the interlayer insulating films 204 and 206). In addition, silane gas and TEOS (Tetra Ethoxy Silane) and other moisture generated during the growth of the interlayer dielectric film are taken into the film.

 [0009] Therefore, there is a conventional structure without an alumina film! In the case of a structure without an alumina film between wiring layers, a nitrogen (N) gas atmosphere is formed after the contact hole is formed and before the plug is formed.

 2

 Annealing was performed to degas the interlayer insulating film, and then contact holes were filled.

On the other hand, in the case of the structure as described above in which two alumina films 203 and 205 are provided with an interlayer insulating film 204 interposed therebetween, the same annealing treatment as before is performed after the contact hole is formed and before the W plug is formed. Even so, since the degassing from the interlayer film is performed through the contact hole, the interlayer insulating film 204 sandwiched between the alumina films 203 and 205 cannot be sufficiently degassed. As a result, the remaining moisture etc. comes to be degassed by the inner wall force of the contact hole by heating when the W plug 202 is subsequently formed using the CVD method or the like (in the figure, an arrow in the direction of the contact hole). o For this reason, poor filling of the W in the contact hole occurs and the contour Problems such as an increase in resistance will occur.

 The present invention has been made in view of these points, and an object of the present invention is to provide a method of manufacturing a highly moisture-resistant semiconductor device having a good interlayer contact structure.

 Means for solving the problem

 In the present invention, in order to solve the above-described problem, in a method of manufacturing a semiconductor device having an interlayer contact structure, a stacked structure in which an interlayer film is formed between first and second films having moisture resistance is provided. A step of forming, a step of forming a contact hole penetrating the formed first and second films and the interlayer film, and an annealing treatment after the formation of the contact hole to perform the first and second steps There is provided a method for manufacturing a semiconductor device, comprising: a step of degassing the interlayer film sandwiched between films; and a step of forming a plug in the contact hole after the annealing process.

 [0013] According to such a method of manufacturing a semiconductor device, after a contact hole is formed in a laminated structure in which an interlayer film is sandwiched between first and second films having moisture resistance, the interlayer film is removed. Annealing for gas is performed. By performing this annealing process under predetermined conditions, degassing from the contact hole is suppressed during subsequent plug formation.

 [0014] According to the present invention, in the method of manufacturing a semiconductor device having an outer structure with an interlayer contour, a step of forming a laminated structure in which an interlayer film is formed between the first and second films having moisture resistance; Forming a contour outer hole penetrating the formed first and second films and the interlayer film, performing a surface treatment on the inner wall surface of the contact hole after the formation of the contact hole, and the surface treatment And a step of forming a plug in the contact hole later. A method for manufacturing a semiconductor device is provided.

 [0015] According to such a method of manufacturing a semiconductor device, after forming a contact hole in a laminated structure in which an interlayer film is sandwiched between first and second films having moisture resistance, the inner wall surface of the contact hole is formed. Surface treatment is performed on the surface. By this surface treatment, for example, the moisture resistance of the inner wall surface of the contact hole is improved. As a result, degassing from the contact hole is suppressed during subsequent plug formation.

The invention's effect In the present invention, after a contact hole is formed in a laminated structure in which an interlayer film is sandwiched between first and second films having moisture resistance, annealing treatment for degassing the interlayer film is performed. I did it. As a result, when a plug is formed after the contact hole is formed, degassing from the contact hole can be suppressed to prevent the occurrence of a defective plug formation, and a semiconductor device having a low-resistance interlayer contour structure can be realized. Become.

Further, in the present invention, after forming a contact hole in a laminated structure in which an interlayer film is sandwiched between first and second films having moisture resistance, surface treatment is performed on the inner wall surface of the contact hole. To do. As a result, it is possible to suppress the outgassing due to the contact hole force when the plug is formed after the contact hole is formed, thereby suppressing the occurrence of a plug formation failure, and a semiconductor device having a low resistance interlayer outer structure can be realized.

[0018] The above and other objects, features and advantages of the present invention are preferred as examples of the present invention, and will become apparent from the following description in conjunction with the accompanying drawings showing embodiments.

 Brief Description of Drawings

FIG. 1 is a diagram showing an example of a semiconductor device formation flow.

 FIG. 2 is a diagram illustrating a configuration example of a semiconductor device.

 FIG. 3 is a diagram showing the configuration of a sample.

 FIG. 4 is a cross-sectional schematic diagram for major components showing a first step of a first application example.

 FIG. 5 is a schematic cross-sectional view of an essential part of a second step in the first application example.

 FIG. 6 is a schematic cross-sectional view of an essential part of a third step in the first application example.

 FIG. 7 is a schematic cross-sectional view of an essential part of a fourth step in the first application example.

 FIG. 8 is a schematic cross-sectional view of the relevant part showing a fifth step of the first application example.

 FIG. 9 is a schematic cross-sectional view of the relevant part showing a sixth step of the first application example.

 FIG. 10 is a cross-sectional schematic diagram for major components showing a seventh step in the first application example.

 FIG. 11 is a schematic cross-sectional view of an essential part of an eighth step in the first application example.

 FIG. 12 is a schematic cross-sectional view of an essential part of the ninth step in the first application example.

 FIG. 13 is a cross-sectional schematic diagram for major components showing a tenth step of the first application example.

 FIG. 14 is a schematic cross-sectional view of an essential part of an eleventh step in the first application example.

FIG. 15 is a cross-sectional schematic diagram for major components showing a twelfth step of the first application example. FIG. 16 is a cross-sectional schematic diagram for major components showing a thirteenth step of the first application example.

 FIG. 17 is a cross-sectional schematic diagram for major components showing a fourteenth step of the first application example.

 FIG. 18 is a cross-sectional schematic diagram for major components showing a fifteenth process of the first application example.

 FIG. 19 is a cross-sectional schematic diagram for major components showing a sixteenth step of the first application example.

 FIG. 20 is a cross-sectional schematic diagram for major components showing a seventeenth step of the first application example.

 FIG. 21 is a cross-sectional schematic diagram for major components showing an eighteenth step of the first application example.

 FIG. 22 is a cross-sectional schematic diagram for major components showing a nineteenth step of the first application example.

 FIG. 23 is a cross-sectional schematic diagram for major components showing a twentieth process of a first application example.

 FIG. 24 is a schematic cross-sectional view (No. 1) of relevant parts showing a modification of the first application example.

 FIG. 25 is a schematic cross-sectional view of the relevant part showing a modification of the first application example (No. 2).

 FIG. 26 is a schematic cross-sectional view (No. 3) of relevant parts showing a modification of the first application example.

 FIG. 27 is a schematic cross-sectional view of the relevant part showing a modification of the first application example (No. 4).

 FIG. 28 is a schematic cross-sectional view of an essential part of FeRAM in a second application example.

 FIG. 29 is a schematic cross-sectional view of an essential part of an example of an interlayer contact structure.

 FIG. 30 is a schematic cross-sectional view of an essential part in the process of forming an interlayer contact structure.

 BEST MODE FOR CARRYING OUT THE INVENTION

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings, taking a semiconductor device provided with a ferroelectric capacitor as an example.

 FIG. 2 is a diagram illustrating a configuration example of a semiconductor device.

A semiconductor device 1 shown in FIG. 2 includes a ferroelectric capacitor 2 having a configuration in which a ferroelectric film 2c is sandwiched between a lower electrode 2a and an upper electrode 2b. The ferroelectric capacitor 2 is covered with a first interlayer insulating film 3, and W plugs 4a, 4b, 4c are formed through the first interlayer insulating film 3. The W plug 4 a is formed so as to be connected to the upper electrode 2 b of the ferroelectric capacitor 2, and the W plug 4 b is formed so as to be connected to the lower electrode 2 a of the ferroelectric capacitor 2. The W plug 4c is connected to, for example, a transistor portion (not shown) formed in the lower layer of the ferroelectric capacitor 2. On these W plugs 4a, 4b, and 4c, first wiring layers 5a, 5b, and 5c are formed, respectively, and the surface of the first wiring layers 5a, 5b, and 5c is exposed and the first interlayer insulation is exposed. On the surface of film 3, moisture and water to the ferroelectric capacitor 2 A first alumina film 6 that suppresses the entry of element is formed.

 [0022] A second interlayer insulating film 7, a second alumina film 8, and a third interlayer insulating film 9 are formed on this structure, and pass through them to connect to the first wiring layer 5c. W plug 10 is formed, and second wiring layers 1 la and 1 lb are formed on the W plug 10 and the third interlayer insulating film 9. Similarly, on this upper layer, the fourth interlayer insulating film 12, the third alumina film 13 and the fifth interlayer insulating film 14, and W connected to the second wiring layers 11a and ib through these layers. Plugs 15a and 15b are formed, and third wiring layers 16a and 16b are formed so as to be connected to the W plugs 15a and 15b. On the upper layer, a sixth interlayer insulating film 17 and a protective film 18 are formed with the third wiring layer 16b partially exposed for pads.

 Thus, in the semiconductor device 1, the flat second alumina film 8 is formed between the first wiring layers 5a, 5b, 5c and the second wiring layers 11a, l ib, It has a so-called double flat alumina structure in which a flat third alumina film 13 is also formed between the wiring layers 11a, ib and the third wiring layers 16a, 16b. In the semiconductor device 1, the second and third alumina films 8, 13 are formed together with the first wiring layers 5a, 5b, 5c and the first alumina film 6 formed on the surface of the first interlayer insulating film 3. As a result, the intrusion of moisture and hydrogen into the ferroelectric capacitor 2 is effectively suppressed.

 Next, an outline of a method for forming the semiconductor device 1 having the above configuration will be described.

 FIG. 1 is a diagram showing an example of a semiconductor device formation flow. However, here, the description will focus on the flow up to the formation of the second wiring layers 11a, ib of the semiconductor device 1.

In forming the semiconductor device 1, first, the transistor portion and the ferroelectric capacitor 2 as an upper layer are formed (step S 1). Next, a first interlayer insulating film 3 and a contact hole penetrating the first interlayer insulating film 3 are formed to form W plugs 4a, 4b, 4c, and further to the first wiring layers 5a, 5b, 5c (step) S2).

[0026] After the formation of the first wiring layers 5a, 5b, 5c, the first alumina film 6 is formed on the entire surface (step S3). A second interlayer insulating film 7 is formed thereon (step S4), a second alumina film 8 is formed (step S5), and a third interlayer insulating film 9 is formed (step S6).

[0027] Then, a contact hole that penetrates through the third interlayer insulating film 9, the second alumina film 8, the second interlayer insulating film 7, and the first alumina film 6 and reaches the first wiring layer 5c is formed. After Step S7), annealing is performed (step S8). This annealing process is, for example, Nyaa

 2 Perform in an inert gas atmosphere such as Lugon (Ar) or in a vacuum at a specified temperature for a specified time. The conditions of the annealing process and the effect will be described later.

 [0028] After the annealing process, after forming the glue layer (step S9), the contact hole is filled with W, and the W is etched back to form the W plug 10 (step S10). A wiring layer 1 la, 1 lb is formed (step S 11).

 [0029] After the formation of the second wiring layers 11a and ib, the fourth inter-layer insulating film 12, the third alumina film 13, the fifth inter-layer insulating film 14 and the following steps S4 to S11 W plugs 15a and 15b are formed to form third wiring layers 16a and 16b. Finally, a sixth interlayer insulating film 17 and a protective film 18 are formed, and a part of them is removed to partially expose the third wiring layer 16b, thereby forming a pad portion.

 Here, the annealing process in step S8 will be described in more detail.

 After forming the contact hole that penetrates through the third interlayer insulating film 9, the second alumina film 8, the second interlayer insulating film 7, and the first alumina film 6 to reach the first wiring layer 5c, the glue layer The annealing process performed before the formation is performed in an inert gas atmosphere such as N or Ar as described above.

 2

 In the air, for a predetermined time, at a predetermined temperature. The results of studying annealing conditions are described below.

FIG. 3 is a diagram showing a configuration of the sample. However, in FIG. 3, the same elements as those shown in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

In examining the annealing conditions, a sample having the structure shown in FIG. 3 was used here. In the sample 20 shown in FIG. 3, the first wiring layers 5a, 5b, and 5c are formed in the above step S2 in a structure in which the Al film 21, the Ti film 22, and the TiN film 23 are stacked (the first wiring layer 5c As shown in steps S3 to S6 above, a first alumina film 6, a second interlayer insulating film 7, a second alumina film 8, and a third interlayer insulating film 9 are formed thereon. As described in step S7, the contact hole 10a reaching the first wiring layer 5c is formed. However, in this sample 20, as shown in FIG. 3, the contact hole 10a formed in step S7 is intentionally displaced with respect to the first wiring layer 5c, and the subsequent steps S9 to S are performed. More unformed parts occur in the W plug 10 formed by 11 It has a thin structure. Note that a 6-inch wafer was used for sample 20, and the average amount of displacement of the contact hole 1 Oa was about 130 nm.

[0032] Using such a sampnore 20, the annealing process time and temperature after the formation of the contact hole 10a were examined. The results are shown in Tables 1 and 2.

[0033] [Table 1]

 [0034] [Table 2]

[0035] Table 1 shows that annealing temperature is 350 ° C in N atmosphere and annealing time is 60 minutes.

 2

 , 120 minutes, 180 minutes, and 240 minutes, the number of occurrence of unformed parts of the W plug 10 under each condition is shown. Table 2 also shows that annealing time is 120 in N atmosphere.

 2

Minutes, annealing at 350 ° C, 375 ° C, 400 ° C

RU

[0036] From Table 1, the annealing time is 60 minutes, 120 minutes, 180 minutes, and 240 minutes, and the number of unformed portions of W plug 10 is 92, 49, 1, and 13 respectively. Met. Sun Despite the fact that pull 20 has a structure in which unformed parts are likely to occur in W plug 10, the number of occurrences is 49, 1, and 13 at 120 minutes, 180 minutes, and 240 minutes, respectively. You can see that the number is small. As described above, when the annealing temperature is 350 ° C., the generation of the unformed portion of the W plug 10 can be suppressed by setting the annealing time to a range of 120 minutes to 240 minutes. In particular, when the annealing time is in the range of 180 minutes to 240 minutes, when the annealing time is 180 minutes when the number of unformed portions of the W plug 10 is very small despite the above structure, the W The number of unformed parts of plug 10 is minimized.

[0037] From Table 2, the annealing temperature was 350 ° C, 375 ° C, 400 ° C, and the number of unformed portions of W plug 10 was 26, 0, and 0, respectively. there were. Although Sample 20 has a structure in which unformed parts are likely to occur in W plug 10, the number of unformed parts in W plug 10 should be small in the annealing temperature range of 350 ° C to 400 ° C. I understand. As described above, when the annealing treatment time is 120 minutes, if the annealing treatment temperature is set in the range of 350 ° C. to 400 ° C., the generation of the unformed portion of the W plug 10 can be suppressed. . In particular, when the annealing temperature is in the range of 375 ° C. to 400 ° C., the W plug 10 is not formed in spite of the above structure, which is very effective.

 [0038] The effects as shown in Table 2 were similarly confirmed even when the annealing temperature ranged from 400 ° C to 500 ° C. It is possible to suppress the occurrence of the unformed portion of the W plug 10 even at a temperature higher than that. When the A1 film 21 is used for the first wiring layer 5c below the contact hole 10a as described above, Since the melting point of A1 is about 660 ° C, it is necessary to set the annealing temperature below that.

 [0039] The effects as shown in Tables 1 and 2 were also observed in an Ar atmosphere or vacuum.

If annealing is performed under the conditions based on the above knowledge, and then the W plug 10 is formed, the contact hole before the W plug 10 is not misaligned. However, it can be said that a good W plug 10 can be formed with no or very few unformed portions in the W plug 10. [0040] The annealing process performed after the contact hole 10a is formed is preferably performed in an inert gas atmosphere or in a vacuum as described above. When forming the semiconductor device 1 having the ferroelectric capacitor 2, an oxidizing gas such as oxygen (O 2) is used to recover the deterioration of the ferroelectric capacitor 2 at an appropriate stage as necessary. Healing recovery with atmosphere

 2

 Processing may be performed. However, if the annealing process is performed in an atmosphere containing an oxidizing gas after the contact hole 10a is formed in this way, the TiN film 23, etc. of the first wiring layer 5c exposed to the bottom of the contact hole 10a is oxidized. This may increase the wiring resistance. Therefore, as described above, the annealing treatment here is preferably performed in an inert gas atmosphere or in a vacuum.

[0041] Here, the annealing process similar to the force described with reference to the annealing process performed before the formation of the W plug 10 connected to the first wiring layer 5c is applied to the second wiring layers 11a and ib. It can be performed before the W plugs 15a and 15b to be connected are formed, and in this case, the same effect as described above can be obtained.

 Here, annealing processing under a predetermined condition is performed before the formation of the W plug 10 connected to the first wiring layer 5c and before the formation of the W plugs 15a and 15b connected to the second wiring layers 11a and ib. We described the case where In order to suppress the formation failure of the W plugs 10, 15a, 15b, for example, before the formation of the W plugs 10, 15a, 15b, for example, plasma nitriding treatment is performed on the inner wall surfaces of the contact holes forming them. You may make it perform. When such a plasma nitriding process is performed, the inner wall surface of the contact hole is nitrided and its moisture resistance is improved. As a result, when the W plugs 10, 15a, 15b are formed, outgassing from the second, third, and fourth interlayer insulating films 7, 9, 12 into the contact holes can be suppressed. The defective formation of 15a and 15b is effectively suppressed.

 [0043] It should be noted that such a surface treatment for the inner wall surface of the contact hole is not limited to the plasma nitriding treatment, and other surface treatment methods can be used as long as they improve the moisture resistance of the inner wall surface of the contact hole. It doesn't matter.

 [0044] It is also possible to perform a surface treatment such as plasma nitriding after the annealing as described above.

The following is an example in which the annealing process is applied to the formation of various types of semiconductor devices. This will be described in detail.

 First, a first application example will be described. This section describes an example of the formation flow and configuration of FeRAM with a planar capacitor structure.

 FIG. 4 is a schematic cross-sectional view of the relevant part in the first step of the first application example.

 For example, a silicon (Si) substrate 30 is used as a semiconductor substrate, and first, an element isolation region 31 for defining an element region by a LOCOS (LOCal Oxidation of Silicon) method is formed on the surface layer. After a well 32 having a predetermined conductivity type is formed in the element region, a gate electrode 34 having a gate length of about 360 nm is formed through a gate insulating film 33.

 [0047] The gate insulating film 33 is formed of, for example, an oxide silicon (SiO 2) film having a thickness of about 6 nm to 7 nm.

 2

 The gate electrode 34 can be formed by forming a tungsten silicide (WSi) layer having a thickness of about 150 nm on an amorphous silicon layer having a thickness of about 50 nm.

[0048] Then, the side wall of the gate electrode 34 is made of a silicon film made of, for example, a SiO film with a film thickness of about 45 nm.

 2

 A Dow insulating film 35 is formed, and a source diffusion layer 36 and a drain diffusion layer 37 are formed in the Si substrate 30 on both sides of the gate electrode 34. In this way, four transistor portions 38 are formed using the Si substrate 30.

 FIG. 5 is a schematic cross-sectional view of the relevant part in the second step of the first application example.

 A silicon oxynitride (SiON) film 39 having a film thickness of about 200 nm is formed as an interlayer insulating film on the surface after the transistor section 38 is formed by using the CVD method. Further, an NSG (Non Silicate Glass) film having a thickness of about 600 nm is formed on the SiON film 39 by a CVD method using TEOS, which is polished by about 200 nm by a CMP (Chemical Mechanical Polishing) process. A TEOS-NSG film 40 having a thickness of about 400 nm is formed by flattening the film.

 FIG. 6 is a schematic cross-sectional view of the relevant part in the third step of the first application example.

 After the formation of the TEOS-NSG film 40, a TEOS-NSG film 41 having a thickness of about lOOnm is further formed thereon. Then, for the degassing of the TEOS-NSG films 40 and 41, for example, annealing is performed in an N atmosphere at about 650 ° C. for about 30 minutes.

 2

[0051] After this annealing, an alumina film 42 having a film thickness of about 20 nm is formed on the TEOS-NSG film 41 by using a PVD (Physical Vapor Deposition) method. After that, using an RTA (Rapid Therma 1 Anneal) apparatus, annealing is performed at about 650 ° C for about 60 seconds in an O atmosphere. FIG. 7 is a schematic cross-sectional view of the relevant part in the fourth step of the first application example.

 A platinum (Pt) film 43 having a film thickness of about 155 nm is formed on the alumina film 42 after the annealing using the PVD method. Further, a film thickness of about 150 nm to about 200 η is formed on the Pt film 43 using the PVD method. m capsule 44 is formed. After forming the PZT film 44, for example, using an RTA apparatus,

 2 In the atmosphere (O flow rate 0.025LZmin), perform annealing for about 90 seconds at about 585 ° C.

 2

 [0053] Next, iridium oxide (IrO) with a film thickness of about 50 nm is formed on the PZT film 44 using the PVD method.

 ) Form a film and use the RTA device again in the O atmosphere (O flow rate 0.025LZmin),

2 2 2

 Annealing is performed at about 725 ° C for about 20 seconds. Then, PVD method is applied again on the IrO film.

 2

 By using this to form an IrO film, an IrO film 45 having a total film thickness of about 250 nm is formed.

 twenty two

 FIG. 8 is a schematic cross-sectional view of the relevant part in the fifth step of the first application example.

 After the formation of the IrO film 45, a photoresist is formed and the IrO film 45 is etched. to this

twenty two

 Thus, the upper electrode 45a made of IrO is formed.

 2

 [0055] Thereafter, in order to recover the PZT film 44, a vertical furnace was used, and the atmosphere was O atmosphere (O flow rate 20LZ

 twenty two

 min), annealing at about 650 ° C for about 60 minutes. After forming the photoresist and etching the PZT film 44, the vertical furnace is used again in the O atmosphere (O flow rate 20LZmin

 twenty two

 ), Annealing at about 350 ° C for about 60 minutes. Thereby, a ferroelectric film 44a made of PZT is formed.

 [0056] Thereafter, in order to protect the ferroelectric film 44a, an alumina film having a film thickness of about 50 nm is formed on the entire surface using the PVD method (not shown), and further, using a vertical furnace, O

 2 In atmosphere (O

 2 Flow rate 2

OL / min), annealing at about 550 ° C for about 60 minutes.

FIG. 9 is a schematic cross-sectional view of the relevant part in the sixth step of the first application example.

 Next, a photoresist is formed, and the Pt film 43 is etched to form a lower electrode 43a made of Pt. Thus, a ferroelectric capacitor in which the ferroelectric film 44a is sandwiched between the upper electrode 45a and the lower electrode 43a is configured.

[0058] After that, in order to recover the ferroelectric film 44a, a vertical furnace was used in an O atmosphere (O flow

2 2 volume 20LZmin), annealing at about 650 ° C for about 60 minutes. Then, in order to protect the ferroelectric capacitor, an alumina film with a film thickness of about 20 nm is formed on the entire surface by PVD method (not shown), and further in an O atmosphere (O (Flow rate 20LZmin), approx. 550 ° C Annealing is performed for about 60 minutes.

[0059] After that, the CVD method is used to completely cover the ferroelectric capacitor so as to have a film thickness of about 150

An Onm TEOS-NSG film 46 is formed, and the surface is flattened by CMP. FIG. 10 is a schematic cross-sectional view of the relevant part in the seventh step of the first application example.

[0060] After the formation of the TEOS-NSG film 46, the surface thereof is nitrided (the nitride film is not shown.) ₀ Nitriding is performed by, for example, using a CVD apparatus to generate nitrogen monoxide (NO) plasma for about 350 times. About 2 minutes at ° C

 2

 This can be done by plasma annealing. Thereafter, a photoresist 47 is formed on the nitrided surface and etching is performed to form a contact hole 48 that reaches a predetermined region of the transistor portion 38.

FIG. 11 is a schematic cross-sectional view of the relevant part in the eighth step of the first application example.

 After the contact hole 48 is formed, after removing the photoresist 47, a PVD method is used to sequentially form a Ti film with a thickness of about 20 nm and a TiN film with a thickness of about 50 nm on the entire surface to form a barrier metal film. (Not shown).

[0062] After the formation of the rare metal film, a W film having a film thickness of about 500 nm is formed on the entire surface by CVD, and the W film formed other than the contact hole 48 is polished by CMP. This

Then, W is buried in the contact hole 48, and a W plug 49 is formed.

[0063] After polishing, the TEOS-NSG film 46 surface was again irradiated with N 2 O plasma at about 350 ° C for about 2 minutes.

 2

 Nitridation is performed by plasma plasma annealing (nitride film is not shown), and a SiON film 50 having a thickness of about lOO nm is formed thereon by CVD.

FIG. 12 is a schematic cross-sectional view of the relevant part showing the ninth step of the first application example.

 A resist pattern is formed on the SiON film 50 (not shown), and a contact hole 51 communicating with the upper electrode 45a and the lower electrode 43a is formed by etching using the resist pattern as a mask. After that, the recovery annealing treatment of the ferroelectric film 44a is performed in an O atmosphere using a vertical furnace (O

 2 2 Flow rate 20LZmin), about 500 ° C for about 60 minutes.

[0065] After the contact hole 51 is formed, the entire surface of the SiON film 50 is etched by an etching process.

 FIG. 13 is a schematic cross-sectional view of an essential part of the tenth process of the first application example.

[0066] After the etching process of the SiON film 50, the contact hole 51, the W plug 49 and the TEO On the S-NSG film 46, a laminated film 52 in which an aluminum copper (Al-Cu) film with a film thickness of about 550 nm, a Ti film with a film thickness of about 5 nm, and a TiN film with a film thickness of about 150 nm are formed in order using the PVD method. Form

FIG. 14 is a schematic cross-sectional view of the relevant part in the eleventh step of the first application example.

 After forming the laminated film 52, a predetermined resist pattern is formed, and etching is performed using the resist pattern as a mask to form the first wiring layer 52a. At the same time, a moisture-proof ring 52b outside the pad and a moisture-proof ring 52c inside the pad are formed outside and inside the region where the pad portion is finally connected, respectively. After that, using a vertical furnace, in N atmosphere (N flow rate 20LZmin)

 twenty two

 Perform annealing for about 30 minutes at about 350 ° C.

[0068] After annealing, the PVD method was used on the first wiring layer 52a and TEOS— NSG film 46.

As a result, an alumina film 53 having a thickness of about 20 nm is formed.

 FIG. 15 is a schematic cross-sectional view of the relevant part showing a twelfth step of the first application example.

[0069] A TEOS-NSG film 54 having a film thickness of about 2600 nm is formed on the alumina film 53 by using the CVD method, and flattened by CMP processing. After that, the TEOS-NSG film 54 surface

Nitrid by plasma annealing that irradiates O plasma at about 350 ° C for about 4 minutes (nitride film

2

 Is not shown. Then, a TEOS-NSG film 55 having a film thickness of about lOOnm is formed by CVD. Then, an alumina film 56 having a thickness of about 50 nm is formed on the TEOS-NSG film 55 by using the PVD method.

[0070] On this alumina film 56, a TEOS-NSG film 57 having a film thickness of about lOOnm is formed by CVD, and then the surface is irradiated with NO plasma at about 350 ° C for about 2 minutes.

 2

 Nitrid by Manner (nitride film not shown).

FIG. 16 is a schematic cross-sectional view of the relevant part showing a thirteenth step of the first application example.

 TEOS— NSG film 57 After nitriding the surface, first wiring layer 52a and pad outside moisture-resistant ring

A contact hole 58 leading to 52b is formed. When forming the contact hole 58, first, a predetermined resist pattern is formed, and the resist pattern is used as a mask to form the TEOS-NSG film 54, 5

5 and 57 and the alumina films 53 and 56 are etched.

[0072] Next, after the contact hole 58 is formed in this way, annealing treatment under a predetermined condition is performed. This annealing process is based on the findings in Tables 1 and 2 above. Set. That is, the TEOS-NSG film 54, 55 sandwiched between the two alumina films 53, 56 is also effectively degassed, and when the contact hole 58 is filled with W later, the W in the contact hole 58 is reduced. The conditions are such that many unformed parts do not occur in the plug.

FIG. 17 is a schematic cross-sectional view of the relevant part showing a fourteenth step of the first application example.

 After the contact hole 58 is formed and a predetermined annealing process is performed, first, a TiN film having a thickness of about 50 nm is formed as a barrier metal film on the entire surface by using the PVD method (not shown). Next, a W film with a film thickness of about 650 nm is formed using the CVD method. Then, the W plug 59 is formed by etching back the entire surface of the W film or planarizing it by CMP.

 FIG. 18 is a schematic cross-sectional view of the relevant part showing a fifteenth step of the first application example.

 After the formation of the W plug 59, a second wiring layer is formed in the same manner as the first wiring layer 52a. First, using the PVD method, a laminated film 60 is formed in which an Al—Cu film with a thickness of about 550 nm, a Ti film with a thickness of about 5 nm, and a TiN film with a thickness of about 150 nm are formed in this order.

 FIG. 19 is a schematic cross-sectional view of the relevant part showing a sixteenth step of the first application example.

 After the formation of the laminated film 60, a predetermined resist pattern is formed and etched to form the second wiring layer 60a. At the same time, the pad outside moisture-resistant ring 60b and the pad inside moisture-resistant ring 60c are respectively formed on the outside and inside of the region where the pad portion is finally connected. After that, a TEOS-NSG film 61 having a film thickness of about 2200 nm is formed on the entire surface by using the CVD method, and flattened by CMP processing. After nitriding the surface of TEOS-NSG film 61 with plasma annealing that irradiates N 2 O plasma at about 350 ° C for about 4 minutes (

2

 The nitride film is not shown. ), A TEOS-NSG film 62 having a film thickness of about lOOnm is formed by CVD, and the surface is irradiated with N 2 O plasma at about 350 ° C for about 2 minutes.

 2

 (Nitride film not shown.) O

 FIG. 20 is a schematic cross-sectional view of the relevant part showing a seventeenth step of the first application example.

After nitriding the surface of TEOS-NSG film 62, contact holes that lead to second wiring layer 60a, pad external moisture-resistant ring 60b, and pad internal moisture-resistant ring 60c are formed, and PVD is used to form a film with a thickness of approximately 50 nm. A TiN film is formed as a barrier metal film (not shown). ₀ Then, a W film with a film thickness of about 650 nm is formed on it using a CVD method, and it is etched back on the entire surface. W plug 63 is formed by flattening by CMP processing.

FIG. 21 is a schematic cross-sectional view of the relevant part showing an eighteenth step of the first application example.

 After the W plug 63 is formed, a third wiring layer is formed in the same manner. First, using the PVD method, a laminated film 64 is formed in which an Al—Cu film with a thickness of about 500 nm and a TiN film with a thickness of about 150 nm are formed in this order.

 FIG. 22 is a cross-sectional schematic diagram for major components showing a nineteenth step of the first application example.

 After forming the laminated film 64, a predetermined resist pattern is formed and etched to form the third wiring layer 64a. At the same time, an external pad moisture-resistant ring 64b and an internal pad moisture-resistant ring 64c are formed on the outer side and the inner side of the region where the pad part is finally connected, respectively. After that, a TEOS-NSG film 65 having a film thickness of about lOOnm is formed on the entire surface by CVD and flattened by CMP. TEOS—NSG film 65

 2

After nitriding with a plasma anneal that irradiates O plasma at about 350 ° C for about 2 minutes (nitride film not shown), a SiN film 66 having a film thickness of about 350 nm is formed by CVD.

 FIG. 23 is a schematic cross-sectional view of an essential part of the twentieth process of the first application example.

 First, a resist pattern is formed on the SiN film 66 (not shown), and the SiN film 66 in the pad formation region, the TEOS-NSG film 65, and the TiN film on the third wiring layer 64a are etched. , Forming an opening.

 Thereafter, photosensitive polyimide having a film thickness of about 3 μm is applied to the region excluding the opening and patterned. In this case, if non-photosensitive polyimide is used instead of photosensitive polyimide, after applying non-photosensitive polyimide, a resist pattern is formed on it and the non-photosensitive polyimide is dissolved using a dedicated developer. . After polyimide patterning, annealing is performed for about 40 minutes at about 310 ° C in N atmosphere (N flow lOOLZmin) using a horizontal furnace.

twenty two

 Then, the polyimide is cured to form a protective film 67.

As a result, the FeRAM 80 including the pad portion 68, the FeRAM cell portion 69, the logic circuit portion 70, and the other peripheral circuit portion 71 is formed.

This FeRAM 80 has a structure in which an alumina film 53 is formed on the surface of the first wiring layer 52a, and another alumina film 56 is formed thereon via TEOS-NSG films 54 and 55. Yes. For such a structure, a contact hole 58 leading to the first wiring layer 52a is formed, Thereafter, annealing is performed under predetermined conditions based on the findings in Tables 1 and 2 above. As a result, the FeRAM 80 in which the formation failure of the W plug 59 is effectively suppressed can be formed.

 [0082] In order to suppress the formation failure of the W plug 59, as described above, instead of the annealing process under such a predetermined condition, the inner wall surface of the contact hole 58 before the W plug 59 is formed, A surface treatment for improving the moisture resistance, for example, a plasma nitriding treatment may be performed.

 In addition, the formation position (formation layer) of the alumina film functioning as a moisture or hydrogen block film is not limited to the above example. In addition, depending on the formation position, the timing for performing annealing treatment for degassing the interlayer insulating film sandwiched between them, or the timing for performing surface treatment for improving the moisture resistance of the inner wall surface of the contact hole, has also changed. come. An alumina film for blocking moisture and hydrogen can be formed at the positions shown in FIGS. 24 to 27, for example.

 FIGS. 24 to 27 are schematic cross-sectional views of the relevant part showing modifications of the first application example.

 In FIGS. 24 to 27, the same elements as those shown in FIGS. 4 to 23 are denoted by the same reference numerals, and detailed description thereof is omitted.

 In FIG. 24, instead of the alumina film 53 shown in FIG. 23, an alumina film 53a is formed between the TEOS-NSG films 54, 55, and another alumina film is formed on the TEOS-NSG film 55. The case where the film 56 is formed is shown.

 When forming the structure as shown in FIG. 24, after the formation of the first wiring layer 52a, the TEOS—NSG film 54 is formed, the alumina film 53a is formed, and the TEOS—NSG film 55 is formed. Then, an alumina film 56 and a TEOS—NSG film 57 are formed. Then, after the formation of the contact hole 58 for forming the W plug 59, annealing treatment under a predetermined condition is performed. As a result, the degassing from the TEOS-NSG film 55 to the contact hole 58 is sufficiently performed, and the formation failure of the W plug 59 is effectively suppressed.

Alternatively, a predetermined surface treatment is performed after the formation of the contact hole 58 for forming the W plug 59. As a result, the moisture resistance of the inner wall surface of the contact hole 58 is improved and the TEOS—NSG film 55 force is prevented from degassing to the contact hole 58, and the W plug 59 is not formed properly. It will be effectively suppressed.

 In FIG. 25, instead of the alumina films 53 and 56 shown in FIG. 23, the surface of the second wiring layer 60a and the TEOS-NSG film 57 and the TEOS-NSG film 62 are In this example, alumina films 53b and 56b are formed.

 When forming the structure as shown in FIG. 25, after forming the second wiring layer 60a, the alumina film 53b is formed, the TEOS-NSG films 61 and 62 are formed, and the alumina film is further formed. 56b is formed. Then, after the formation of the contact hole for forming the W plug 63 leading to the second wiring layer 60a, annealing treatment under a predetermined condition is performed. As a result, the TEOS-NSG films 61 and 62 are sufficiently degassed into the contact holes, and the formation failure of the W plug 63 is effectively suppressed.

Alternatively, a predetermined surface treatment is performed after the formation of the contact hole for forming the W plug 63. As a result, the moisture resistance of the inner wall surface of the contact hole is improved and the TEOS— NSG film 61

, 62 is prevented from degassing to the contact hole, and the formation failure of the W plug 63 is effectively suppressed.

FIG. 26 shows a ferroelectric capacitor in addition to the alumina film 53c (not shown in FIG. 23) of the ferroelectric capacitor layer in place of the alumina films 53 and 56 shown in FIG. In this example, an alumina film 56c is formed in the TEOS-NSG film 46 between the first wiring layer 52a and the first wiring layer 52a.

 In the case of forming the structure as shown in FIG. 26, after the formation of the lower electrode 43a, the ferroelectric film 44a and the upper electrode 45a, an alumina film 53c is formed, and an alumina film 56c is sandwiched therebetween. In this way, a TEOS-NSG film 46 is formed. After that, after the formation of the contact hole 48 for forming the W plug 49 and the subsequent formation of the contact hole 51 leading to the upper electrode 45a and the lower electrode 43a, annealing treatment under predetermined conditions is performed. As a result, the degassing from the TEOS-NSG film 46 to the contact holes 48 and 51 is sufficiently performed, and the formation failure of the W plug 49 and the laminated film 52 (first wiring layer 52a) of FIG. 13 is effectively performed. It will be suppressed.

[0093] Alternatively, after the formation of the contact hole 48 for forming the W plug 49 and the formation of the contact hole 51 leading to the upper electrode 45a and the lower electrode 43a, a predetermined surface treatment is performed. Yeah. As a result, the moisture content of the inner wall surfaces of the contact holes 48, 51 is improved, and degassing from the TEOS-NS G film 46 to the contact holes 48, 51 is suppressed, and the W plug 49 and the laminated film 52 (FIG. 13) The formation failure of the first wiring layer 52a) is effectively suppressed.

 In FIG. 27, the alumina film 42 shown in FIG. 23 is replaced with another insulating film 42a such as a SiON film or a SiN film, and the alumina film 53 shown in FIG. , 56 shows the case where the anolemina films 53d and 56d are formed.

 When forming the structure shown in FIG. 27, after forming the alumina film 53d on the TEOS-NSG film 41, the insulating film 42a is formed, and the alumina film 56d is formed thereon. . Then, a ferroelectric capacitor and a TEOS-NSG film 46 are formed, and after the contact hole 48 reaching the transistor portion 38 is formed, annealing treatment under a predetermined condition is performed. Since two layers of alumina films 53d and 56d are formed between the transistor layer and the ferroelectric capacitor layer, the insulating film 42a is sufficiently degassed to the contact hole 48, and the defective formation of the W plug 49 is effective. Will be suppressed.

 Alternatively, a predetermined surface treatment is performed after forming the contact hole 48 reaching the transistor portion 38. As a result, outgassing from the insulating film 42a to the contact hole 48 is suppressed, and the formation failure of the W plug 49 is effectively suppressed.

 Next, a second application example will be described. Here, FeRAM with a stacked capacitor structure is described as an example.

 FIG. 28 is a schematic cross-sectional view of the relevant part of the FeRAM of the second application example.

 In the FeRAM 90 shown in FIG. 28, a well 93 is formed in the element region defined by the element isolation region 92 of the Si substrate 91, and a gate insulating film 94, a gate electrode 95, and a sidewall insulating film 96 are formed in accordance with a conventional method. A source diffusion layer 97 and a drain diffusion layer 98 are formed to constitute a transistor portion 99.

 The transistor unit 99 is covered with a SiON film 100 formed using the CVD method, and an SiO film 101 similarly formed using the CVD method is deposited thereon. SiON

 2

 The film 100 has a function as a stopper film in contact hole etching and a function of improving moisture resistance.

[0100] Then, the source diffusion of the transistor part 99 passes through the SiO film 101 and the SiON film 100. A W plug 102 is formed in a contact hole reaching the layer 97 and the drain diffusion layer 98 via a barrier metal film (not shown). The noria metal film is formed by laminating a Ti film and a TiN film by sputtering after forming the contact holes. The W plug 102 is formed by depositing a barrier metal film on the entire surface, depositing W using the CVD method or the like, and polishing them to the surface of the SiO film 101 using the CMP method.

 2

 [0101] Immediately above the W plug 102 connected to the source diffusion layer 97 of the transistor part 99 is a lower electrode 103 having a thickness of about 200 nm, a ferroelectric film 104 having a thickness of about 120 nm, and an upper electrode having a thickness of about 200 nm. A ferroelectric capacitor having a laminate strength of 105 is formed. For example, the lower electrode 103 is an Ir film, the ferroelectric film 104 is a PZT film, and the upper electrode 105 is an IrO film.

 2

 Composed. In that case, the Ir film and IrO film can be formed by sputtering.

 2

 The The PZT film is formed by using MOCVD (Metal Organic Chemical Vapor Deposition) method. Incidentally, after the formation of the upper electrode 105, a recovery annealing of the PZT film is usually performed.

 [0102] On the surface of the ferroelectric capacitor and the SiO film 101, in order to protect the ferroelectric capacitor,

 2

 An alumina film 106 is formed. A SiO film 107 is formed on the alumina film 106,

 2

 An alumina film 108 is further formed thereon. A protective film 109 is formed thereon, and the W plug 110 is connected via a barrier metal film (not shown) so as to be connected to the W plug 102 connected to the drain diffusion layer 98 of the transistor section 99. Is formed. Electrodes 11 la, 111b, and 111c are formed on the W plug 110 and contact holes that lead to the upper electrode 105 of the ferroelectric capacitor, respectively. In the case of a multilayer structure, a wiring layer may be formed instead of these electrodes 11la, 111b, 111c.

[0103] In the FeRAM90 having such a configuration, after the formation of the contact hole for forming the W plug 110 or after the formation of the contact hole leading to the upper electrode 105, the predetermined conditions based on the knowledge in Table 1 and Table 2 above are satisfied. Annealing is performed. Alternatively, a predetermined surface treatment is performed to improve the moisture resistance of the inner wall surface of the contact hole. From this point, the SiO film 107 sandwiched between the two alumina films 106 and 108 is sufficiently degassed, and the W plug 110 and electrode 11 lb

 2

, 11 lc formation defects are effectively suppressed. Note that even in the case of a stacked capacitor structure such as this FeRAM90, depending on the structure, an alumina film may be formed in the same manner as illustrated in FIGS. 24, 25, and 27 for the planar capacitor structure. The formation position (formation layer) can be changed. Even in such a case, an annealing process for degassing, or a surface treatment for improving the moisture resistance should be performed under predetermined conditions according to the formation position!

[0105] As described above, here, when a contact hole is formed in a structure in which an interlayer insulating film is sandwiched between alumina films and a plug or the like is formed therein, the plug or the like is formed after the contact hole is formed. Annealing treatment under a predetermined condition or a predetermined surface treatment for the inner wall surface of the contact hole was performed before the formation of.

 [0106] When the annealing treatment is performed, the conditions are as follows: in an inert gas atmosphere or in vacuum, at a temperature of 350 ° C for 120 minutes to 240 minutes, preferably in an inert gas atmosphere or in vacuum Time at 350 ° C. for 180 minutes to 240 minutes, more preferably in an inert gas atmosphere or in a vacuum at a temperature of 350 ° C. for 180 minutes. Alternatively, in an inert gas atmosphere or in vacuum, at a temperature in the range of 350 ° C to 500 ° C for 120 minutes, preferably in an inert gas atmosphere or in vacuum at a temperature of 375 ° C to 400 ° C. The range is 120 minutes. By performing such a pole treatment, degassing from the interlayer insulating film sandwiched between the alumina films to the contact hole can be sufficiently performed, and plugs and the like caused by heating when forming the plugs and the like can be performed. Generation | occurrence | production of formation defect can be suppressed effectively.

 [0107] Further, when performing the surface treatment, for example, a plasma nitriding treatment is used. By performing such surface treatment, the moisture resistance of the inner wall surface of the contact hole is improved, and degassing from the interlayer insulating film sandwiched between the alumina films to the contact hole is suppressed during heating when forming a plug or the like. Therefore, it is possible to effectively suppress the occurrence of formation defects such as plugs.

 In the above description, the case where an alumina film is used as the moisture / hydrogen blocking film has been described as an example. In addition to the alumina film, an oxide film such as a titanium oxide (TiO 2) film, SiON Membrane, Si

 2

N films, nitride films such as boron nitride (BN) films, silicon carbide (SiC) films, carbide films such as carbon (C) films, and polyimide resin films can be used. The same effects as described above can be obtained by predetermined annealing or surface treatment. Ma Even in the case where the interlayer insulating film is sandwiched by using different films among these, the same effects as described above can be obtained by the predetermined annealing treatment or surface treatment.

 [0109] In the above description, the case where a PZT film is used as a ferroelectric film has been described as an example. However, the power of the PZT film, lanthanum-doped lead zirconate titanate (Pb La Zr TiO),- O

 1-χ l -y y 3 Strontium bismuth tantalate tantalate (SrBi (Ta Nb) O)), bismuth titanate (

 2 1 2 9

 BiTi 2 O 3) or the like can also be used.

 4 2 12

 [0110] In the above description, the force described using FeRAM as an example. The predetermined annealing treatment or surface treatment is performed by using a water-hydrogen blocking film such as an alumina film or another interlayer such as an etching stubber film. The present invention can be widely applied to the formation of various semiconductor devices having the same interlayer outer structure using a film.

 [0111] The above merely illustrates the principle of the present invention. In addition, many variations and modifications are possible to those skilled in the art, and the invention is not limited to the precise configuration and application shown and described above, but all corresponding variations and equivalents are It is regarded as the scope of the present invention by the claims and their equivalents.

 Explanation of symbols

[0112] 1 Semiconductor device

 2 Ferroelectric capacitor

 2a, 43a, 103 Bottom electrode

 2b, 45a, 105 Upper electrode

 2c, 44a, 104 Ferroelectric film

 3 First interlayer insulating film

 4a, 4b, 4c, 10, 15a, 15b, 49, 59, 63, 102, 110 W plug

 5a, 5b, 5c, 52a First wiring layer

 6 First alumina film

 7 Second interlayer insulating film

 8 Second alumina membrane

 9 Third interlayer insulating film

10a, 48, 51, 58 Contact hole a, l ib, 60a Second wiring layer

 Fourth interlayer insulating film

 Third alumina membrane

 Fifth interlayer insulating film

a, 16b, 64a 3rd wiring layer

 6th interlayer insulating film

, 67, 109 Protective film

 Samnore

 A1 membrane

 TiH

 TiN film

, 91 Si substrate

, 92 Device isolation region

, 93 uel

, 94 Gate insulation film

, 95 Gate electrode

, 96 Side wall insulation film

, 97 Source diffusion layer

, 98 Drain diffusion layer

, 99 Transistor part

, 50, 100 SiON film

, 41, 46, 54, 55, 57, 61, 62, 65 TEOS— NSG film

, 53, 53a, 53b, 53c, 53d, 56, 56b, 56c, 56d, 106, 108 Alumina film a Insulating film

 Pt film

 PZT film

 IrO film

 2

Photoresist , 60, 64 laminated film

b, 60b, 64b Node external moisture ring c, 60c, 64c Node internal moisture ring SiN film

 Pad part

 FeRAM Senor Department

 Logic circuit part

 Peripheral circuit

, 90 FeRAM

1, 107 SiO film

 2

1a, 111b, 111c electrodes

Claims

The scope of the claims

 [1] In a method of manufacturing a semiconductor device having an outer structure of an interlayer contour,

 Forming a laminated structure in which an interlayer film is formed between the first and second films having moisture resistance;

 Forming a contact hole penetrating the formed first and second films and the interlayer film;

 Performing an annealing process after forming the contact holes to degas the interlayer film sandwiched between the first and second films;

 And a step of forming a plug in the contact hole after the annealing process.

[2] In the step of degassing the interlayer film sandwiched between the first and second films by performing the annealing process after the formation of the contact hole,

 2. The semiconductor according to claim 1, wherein the annealing treatment is performed in an inert gas atmosphere or in a vacuum to degas the interlayer film sandwiched between the first and second films. Device manufacturing method.

 [3] In the step of degassing the interlayer film sandwiched between the first and second films by performing the annealing process after forming the contact hole,

 The annealing treatment is performed at a temperature of 350 ° C. for a time of 120 minutes to 240 minutes, and the first treatment is performed.

The method of manufacturing a semiconductor device according to claim 1, wherein the interlayer film sandwiched between the second films is degassed.

[4] In the step of degassing the interlayer film sandwiched between the first and second films by performing the annealing process after forming the contact hole,

 The annealing treatment is performed at a temperature of 350 ° C. to 500 ° C. for a time of 120 minutes.

The method of manufacturing a semiconductor device according to claim 1, wherein the interlayer film sandwiched between the second films is degassed.

[5] The semiconductor device according to claim 1, wherein the first and second films are formed using an oxide film, a nitride film, a carbide film, or a resin film. Method.

[6] The laminated structure in which the interlayer film is formed between the first and second films having moisture resistance Before the process of forming

 A step of forming a lower layer wiring;

 In the step of forming the laminated structure in which the interlayer film is formed between the first and second films having moisture resistance,

 Forming the laminated structure on the upper layer of the formed lower layer wiring;

 In the step of forming the contact hole penetrating the first and second films and the interlayer film,

 Forming the contact hole so as to penetrate the first and second films and the interlayer film to reach the lower layer wiring;

 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming an upper layer wiring on the formed plug after the step of forming a plug in the contact hole after the annealing treatment.

[7] Before the step of forming the laminated structure in which the interlayer film is formed between the first and second films having moisture resistance,

 Forming a ferroelectric capacitor;

 In the step of forming the laminated structure in which the interlayer film is formed between the first and second films having moisture resistance,

 In the step of forming the stacked structure in the upper layer of the formed ferroelectric capacitor, and forming the contact hole penetrating the first and second films and the interlayer film,

 Forming the contact hole so as to penetrate the first and second films and the interlayer film to reach the ferroelectric capacitor;

 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a wiring on the formed plug after the step of forming a plug in the contact hole after the annealing process.

[8] Before the step of forming the laminated structure in which the interlayer film is formed between the first and second films having moisture resistance,

Forming a transistor, In the step of forming the laminated structure in which the interlayer film is formed between the first and second films having moisture resistance,

 Forming the stacked structure on an upper layer of the formed transistor;

 In the step of forming the contact hole penetrating the first and second films and the interlayer film,

 The contact hole is formed so as to penetrate the first and second films and the interlayer film to reach the transistor;

 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a wiring on the formed plug after the step of forming a plug in the contact hole after the annealing process.

[9] Before the step of forming the laminated structure in which the interlayer film is formed between the first and second films having moisture resistance,

 Forming a transistor,

 In the step of forming the laminated structure in which the interlayer film is formed between the first and second films having moisture resistance,

 Forming the stacked structure on an upper layer of the formed transistor;

 After the step of forming the laminated structure,

 Forming a ferroelectric capacitor on the multilayer structure;

 Forming an interlayer insulating film on the ferroelectric capacitor;

 Have

 In the step of forming the contact hole penetrating the first and second films and the interlayer film,

 The contact hole is formed so as to penetrate the interlayer insulating film, the first and second films, and the interlayer film to reach the transistor;

 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a wiring on the formed plug after the step of forming a plug in the contact hole after the annealing process.

[10] In a method of manufacturing a semiconductor device having an outer structure between interlayer contours, Forming a laminated structure in which an interlayer film is formed between the first and second films having moisture resistance;

 Forming a contact hole penetrating the formed first and second films and the interlayer film;

 Performing a surface treatment on the inner wall surface of the contact hole after forming the contact hole;

 Forming a plug in the contact hole after the surface treatment;

 A method for manufacturing a semiconductor device, comprising:

11. The method for manufacturing a semiconductor device according to claim 10, wherein the surface treatment is a treatment for improving moisture resistance of the inner wall surface of the contact hole.

12. The method of manufacturing a semiconductor device according to claim 10, wherein the surface treatment is a plasma nitridation treatment in which the inner wall surface of the contact hole is irradiated with nitrogen-containing plasma for nitriding.

 13. The method for manufacturing a semiconductor device according to claim 10, wherein the first and second films are formed using an oxide film, a nitride film, a carbide film, or a resin film. Method.

 [14] Before the step of forming the laminated structure in which the interlayer film is formed between the first and second films having moisture resistance,

 A step of forming a lower layer wiring;

 In the step of forming the laminated structure in which the interlayer film is formed between the first and second films having moisture resistance,

 Forming the laminated structure on the upper layer of the formed lower layer wiring;

 In the step of forming the contact hole penetrating the first and second films and the interlayer film,

 Forming the contact hole so as to penetrate the first and second films and the interlayer film to reach the lower layer wiring;

11. The method of manufacturing a semiconductor device according to claim 10, further comprising a step of forming an upper layer wiring on the formed plug after the step of forming a plug in the contact hole after the surface treatment.

[15] Before the step of forming the laminated structure in which the interlayer film is formed between the first and second films having moisture resistance,

 Forming a ferroelectric capacitor;

 In the step of forming the laminated structure in which the interlayer film is formed between the first and second films having moisture resistance,

 In the step of forming the stacked structure in the upper layer of the formed ferroelectric capacitor, and forming the contact hole penetrating the first and second films and the interlayer film,

 Forming the contact hole so as to penetrate the first and second films and the interlayer film to reach the ferroelectric capacitor;

 11. The method of manufacturing a semiconductor device according to claim 10, further comprising a step of forming a wiring on the formed plug after the step of forming a plug in the contact hole after the surface treatment.

[16] Before the step of forming the laminated structure in which the interlayer film is formed between the first and second films having moisture resistance,

 Forming a transistor,

 In the step of forming the laminated structure in which the interlayer film is formed between the first and second films having moisture resistance,

 Forming the stacked structure on an upper layer of the formed transistor;

 In the step of forming the contact hole penetrating the first and second films and the interlayer film,

 The contact hole is formed so as to penetrate the first and second films and the interlayer film to reach the transistor;

 11. The method of manufacturing a semiconductor device according to claim 10, further comprising a step of forming a wiring on the formed plug after the step of forming a plug in the contact hole after the surface treatment.

[17] Before the step of forming the laminated structure in which the interlayer film is formed between the first and second films having moisture resistance, Forming a transistor,

 In the step of forming the laminated structure in which the interlayer film is formed between the first and second films having moisture resistance,

 Forming the stacked structure on an upper layer of the formed transistor;

 After the step of forming the laminated structure,

 Forming a ferroelectric capacitor on the multilayer structure;

 Forming an interlayer insulating film on the ferroelectric capacitor;

 Have

 In the step of forming the contact hole penetrating the first and second films and the interlayer film,

 The contact hole is formed so as to penetrate the interlayer insulating film, the first and second films, and the interlayer film to reach the transistor;

 11. The method of manufacturing a semiconductor device according to claim 10, further comprising a step of forming a wiring on the formed plug after the step of forming a plug in the contact hole after the surface treatment.