WO2007110906A1 - データ処理装置 - Google Patents
データ処理装置 Download PDFInfo
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- WO2007110906A1 WO2007110906A1 PCT/JP2006/306089 JP2006306089W WO2007110906A1 WO 2007110906 A1 WO2007110906 A1 WO 2007110906A1 JP 2006306089 W JP2006306089 W JP 2006306089W WO 2007110906 A1 WO2007110906 A1 WO 2007110906A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
Definitions
- the present invention relates to a data processing device, and more particularly to a task state management method and a task fast search circuit capable of starting execution in a multitask data processing device capable of simultaneously executing a plurality of tasks.
- Multitask control in such a device is generally realized by executing predetermined software on a data processing apparatus represented by an embedded processor that controls the device.
- this software hereinafter referred to as task management program
- this software has a scheduling policy that has been defined in advance in response to a predetermined switching factor such as an interrupt indicating the switching timing of the execution task. It has a function to select the task to be executed next.
- multitask control which is processing overhead, has real-time characteristics, in particular like an embedded processor, that is, the response time until the start of task execution for an event input that causes a specific task to start. Guarantee is required. For this reason, there is a need for a new multi-task control implementation method that efficiently executes a task management program in addition to simply improving the performance of a data processing device.
- Patent Documents 1 and 2 are examples of documents described in connection with processing of a task management program for realizing multitask control.
- Patent Document 1 describes a reservation station (instruction buffer) of a multi-thread processor that supports out-of-order execution. Describes a technology that enables overtaking of instruction execution using the thread number and priority assigned to each instruction.
- Patent Document 2 describes that a processor that processes multi-streams controls access to computing resources according to the priority of each stream, and the priority is dynamically set by off-chip input, software, or hardware. The technology that can be changed is described.
- Patent Document 1 Japanese Patent Application Laid-Open No. 2004-295195
- Patent Document 2 Japanese Translation of Special Publication 2002-532801
- the inventor of the present application has examined the processing contents of a task management program that realizes multitask control, and has also found the following problems to be solved from the viewpoint of improving execution efficiency.
- the core of the functions of the task management program is a process of selecting one task from a task group in a state where the next task to be executed can be started.
- This selection process is a search operation including a series of condition comparison and determination processes for all tasks based on the scheduling policy, and can be executed in parallel.
- the search operation needs to be executed sequentially for the task group, so not only the processing speed decreases due to the increase in the number of tasks, but also It becomes difficult to guarantee real-time performance based on the worst value of the processing time of the task management program.
- the present inventor guarantees the time sequence of task generation when considering the real-time property for tasks for which execution conditions are in place in priority control when executing generated and pooled tasks. Found the importance of.
- An object of the present invention is to provide a data processing apparatus capable of guaranteeing a high-speed condition comparison determination process for selecting data and a time order of the selected data.
- Another object of the present invention is to provide a data processing apparatus capable of realizing multi-task control with high efficiency and high real-time property.
- a data processing device (100) uses a multi-bit storage element (800-0 to 800-m) having a data shift function and a data comparison function as one entry,
- a storage element array (330) having a plurality of entries (333-0 to 333-255) is provided to enable data shift between corresponding bit positions.
- a priority determination for identifying one entry among the plurality of entries with a predetermined priority based on a comparison result between the data inputted in common to the plurality of entries and the contents held in the storage elements constituting the entries. It has a circuit (340).
- each entry has a data shift function and a data comparison function in units of storage elements, so that parallel comparison is possible by an associative memory function as a CAM (Content Addressable Memory).
- an associative memory function as a CAM (Content Addressable Memory).
- the invalid data entry can be prevented by the data shift between the entries, and the valid data can be packed and sequentially held in the entry. Become. Therefore, by holding newly added data in the last empty entry in the shift direction, it is possible to easily guarantee the time order in which the stored data is added according to the entry sequence. Since it is easy to guarantee the time order of entries uniquely, it is possible to identify the required data in consideration of the priority according to the time order for the search result by the CAM.
- the predetermined priority is a rank relating to early and late of the order in which data is held in an entry holding significant data. This makes it easy to implement priority control that considers the time sequence for identifying entries.
- the data processing device (100) has a multi-bit storage element (800-0 to 800-m) having a data shift function and a data comparison function as one entry,
- a storage element array (300) having a plurality of entries (333-0 to 333-255) is provided so that data can be shifted in one direction between corresponding bit positions.
- the entry has a new When responding to an operation command that holds new data, the time order of new data holding for the entry is controlled in the direction opposite to the arrangement in the data shift direction of the entry, and the holding data of the entry is invalidated.
- a control circuit (310, 320, 350) that shifts the data of the upstream entry in the temporal order downstream from the invalidated entry by the number of invalidated entries when responding to the operation command to be invalidated. Further, based on a comparison result between search data that is commonly input to the plurality of entries and search target data held in a storage element that constitutes the entry, one entry of the plurality of entries with a predetermined priority. Is provided with a priority determination circuit (340). At this time, the predetermined priority is set to a predetermined rank in the temporal order.
- each entry has a data shift function and a data comparison function in units of storage elements, so that parallel comparison is possible by the associative memory function. Then, when the data held in the middle entry becomes invalid, the data shift between the entries prevents the invalid data entry from existing in the middle, and the valid data is packed and sequentially held in the entry. Therefore, by holding newly added data in the empty entry at the end of the shift direction, it is possible to uniquely guarantee the time order in which the retained data is added according to the entry sequence. Since it is easy to guarantee the time order of entries uniquely, it is possible to identify the required data in consideration of the priority according to the time order for the search results by CAM. As a result, priority control in consideration of the time order for identifying entries can be performed quickly and easily.
- the present invention has an empty entry position pointer (318-8) indicating the position of an entry that can hold new data.
- an empty entry position pointer (318-8) indicating the position of an entry that can hold new data.
- a multi-bit storage element having a data shift function is used as one table entry, and data can be shifted in one direction between corresponding bit positions of adjacent table entries.
- a plurality of table entries are provided, and the table entries correspond to the entries of the storage element array on a one-to-one basis, and have a data table (360).
- the data table entry corresponds to an entry in the storage element array
- the data shift operation is synchronized with the data shift operation.
- the data table outputs data held by a table entry corresponding to one entry identified by the priority determination circuit.
- the output data is the result obtained by associative search.
- an extended output interface (380) capable of outputting a comparison result with data to be searched in the storage element array, and a logical product of the comparison result in the storage element array
- an extended input interface (370) that can input a higher-order comparison result. It is possible to expand the size of associative memory by parallelizing memory element arrays.
- a data processing device (100) includes a processor unit (200) capable of executing a multitask control program and a plurality of arithmetic units to which tasks to be executed by the multitask control program are assigned. (400-l to 400-n) and a task management unit (300) that performs a process of selecting a task to be executed by the arithmetic unit.
- the task management unit includes a storage element array (330), a control circuit (310, 320, 350), and a priority determination circuit (340).
- the storage element array has a multi-bit storage element having a data shift function and a data comparison function as one entry, and has a plurality of entries so that data can be shifted in one direction between corresponding bit positions of adjacent entries.
- the control circuit responds to an operation instruction from the processor unit that holds new task management information in the entry, the control circuit sets the time sequence of holding the new task management information for the entry in the data shift direction of the entry. Controls in the opposite direction to the array and invalidates the data of the upstream entry in the temporal order from the invalidated entry when responding to the operation command from the processor unit that invalidates the retained data of the entry. Data is shifted downstream by the number of entries.
- the priority determination circuit has a predetermined priority based on a comparison result between search data input in common to the plurality of entries and search target data held in a storage element constituting the entry. Identify one entry.
- the predetermined priority is set to a predetermined rank in the temporal order.
- the data processing apparatus is formed on one semiconductor substrate.
- each entry has a data shift function and a data comparison function in units of storage elements. Noh.
- the task management information of the entry in the middle becomes invalid (when the corresponding task is completed), there can be no invalid task management information entry in the middle due to data shift between entries. Therefore, it is possible to pack valid task management information in order and keep it in entries sequentially. Therefore, by keeping newly added task management information in the last free entry in the shift direction, task management information according to the order of entries. It is possible to guarantee a unique order of the time that is added. Since it is easy to guarantee the time order of entries uniquely, it is possible to identify the required data by adding the priority according to the time order to the search results by CAM. As a result, priority control for task selection in consideration of the time order can be performed quickly and easily.
- the task management unit outputs a task ID included in the task management information held by the entry identified by the priority determination circuit to the processor unit.
- the processor unit causes a free arithmetic unit to process the task specified by the task ID.
- the task management unit uses a plurality of bits of storage elements having a data shift function as one table entry, and shifts data in one direction between corresponding bit positions of adjacent table entries.
- a plurality of table entries so that the table entries correspond to the entries of the storage element array in a one-to-one correspondence.
- the data table entry is subjected to a data shift operation in synchronization with the data shift operation for the storage element array entry.
- the data table also outputs the task ID for the table entry corresponding to one entry identified by the priority determination circuit.
- FIG. 1 is a block diagram generally showing an example of a data processing device according to the present invention.
- FIG. 2 is a format diagram showing an example of a task pool for multitask control.
- FIG. 3 is a block diagram illustrating an example of a task management processor.
- FIG. 4 is a block diagram showing an example of a main processor interface.
- FIG. 5 is a block diagram showing an example of a task state management array.
- FIG. 6 is a block diagram showing an example of a task state management entry.
- FIG. 7 is a block diagram showing a first example of a task state management cell.
- FIG. 8 is a block diagram showing a second example of a task state management cell.
- FIG. 9 is a waveform diagram of terminals () SE1 and () SE2 in FIG.
- FIG. 10 is a flowchart showing the first half of a task control flow in the main processor.
- FIG. 11 is a flowchart showing the second half of the task control flow in the main processor.
- FIG. 12 is a flowchart showing a specific example of array alignment processing by inter-entry shift shown in FIG.
- FIG. 13 is a flowchart showing a specific example of the next task search process shown in FIG. 11.
- FIG. 14 is a flowchart showing an array alignment control flow in the task management processor.
- FIG. 15 is a flowchart showing a specific example of array update processing shown in FIG.
- Task management processor (task management unit)
- TID 0 to TID—k Task ID ST—0 to ST—k Task state
- circuit elements constituting the data processing apparatus described below are formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit technology such as a CMOS transistor or a bipolar transistor. Be done
- FIG. 1 shows an example of a data processing apparatus according to the present invention.
- the data processor 100 includes a main processor (processor unit) 200, a task management processor (task management unit) 300, n arithmetic units 400—1 to 400—n, n local memories 410—1 to 410—n, It consists of n local memory buses 420-l to 420-n, an internal bus 500, an arithmetic unit control bus 510, a peripheral module 600, a main memory interface 700, a main memory 710, and a main memory bus 720.
- the main processor 200 has a unique instruction set similar to that of a general microprocessor, and operates the data processor according to various control programs (not shown) including a multitask control program stored in the main memory 710. To control.
- the task management processor 300 cooperates with the multitask control program running on the main processor 200 to maintain the state of each task, and at the same time, selects a task to be executed next at task switching at a high speed and constant. Multitask control is made more efficient by executing in time.
- the arithmetic units 400-l to 400-n indicate that the multitask control program operating on the main processor 200 has assigned an execution task to the arithmetic unit via the arithmetic unit control bus 510.
- a predetermined task execution start request signal is received, the operation data stored in the local memory 410-1 to 410-n is read via the local memory bus 420-1 to 420-n and a predetermined process is executed.
- the assigned task is executed by a series of operations for storing the operation result in the local memories 410-1 to 410-n again.
- a predetermined task execution completion notification is transmitted to the main processor 200 via the arithmetic unit control bus 510.
- the internal bus 500 includes a main processor 200, a task management processor 300, and an arithmetic unit 400.
- the peripheral module 600 has a DMA transfer function for transferring data between the main memory 710 and the local memory 410-l to 410-n, a timer function as a reference time for task switching, and not shown. Various functions such as output device control are provided.
- the main memory interface 700 controls access to the main memory 710 via the main memory interface 720.
- the main memory 710 may be the same chip as the data processing apparatus 100 or a separate chip! /.
- FIG. 2 shows an example of a task pool for multitask control that manages the status of each task.
- the status of each task TASK0 to TASKk is represented by task management information.
- the task management information includes, for example, task ID (TID—0 to TID—k), task status (ST—0 to ST—k). ), Execution priority 13 ⁇ 4 0 to 13 ⁇ 41 1, and preferential execution flag 1 ⁇ 0 to 1 ⁇ 1 are included.
- Task management information in the data processing device 100 is stored in the task management processor 300.
- the task ID is a code uniquely assigned to identify each task.
- the task status is (1) the task is waiting for all conditions that can be executed (Waiting), and (2) all the conditions that can be executed are satisfied and waiting for the start of execution. This is a status code that indicates whether the status is (Ready) or (3) the task is being executed and is waiting for completion of execution (Running).
- the execution priority is a code indicating the urgency of the task execution.
- the execution flag indicates whether a condition group necessary for starting execution of the task, such as completion of execution of a task having a specific ID or completion of preparation of initial data, is established.
- a task management program for realizing multitask control operates as follows.
- a task group whose task status is "Ready” is executed next based on a predetermined scheduling policy such as the highest execution priority and the oldest task that has been added to the task pool. Select one task to be performed. In addition, it notifies the selected task of permission to start execution and updates the task status from “Ready” to “Running”.
- Task pool off-chip memory 71 or peripheral circuit 600 Stored in the on-chip memory (not shown) and all task management control is implemented by the software of the main processor 200, it takes a long time to search the task pool required for task selection. In addition, the occurrence of access to the main memory, etc., and the search time increase according to the number of tasks held in the task pool, makes it difficult to ensure real-time performance.
- the task management processor 300 is a circuit that enables efficient multitask control by guaranteeing the time order in addition to the parallel search operation depending on the number of tasks. The details of are explained.
- FIG. 3 shows an example of the task management processor 300.
- the task management processor 300 includes a main processor interface 310, an array access arbitration unit 320, a task state management array 330, a priority determination unit (priority determination circuit) 340, an array update control unit 350, a task ID table (data table). 360 and task management processor expansion interface 370, 380.
- the main processor interface 310, the array access arbitration unit 320, and the array update control unit 350 constitute a control circuit that performs task management control using the storage element array in response to an operation command from the main processor 200.
- 311 is an array access arbitration unit control node
- 312 is a task state management array control bus
- 313 is a task state management array search signal.
- 314 and 315 are array update control unit control signals
- 316 is a task ID table control bus.
- 321-0 to 321-255 are task state management entry control signals
- 331-0 to 331-255 are task state management entry comparison signals.
- 341—0 to 341—255, 371—0 to 371—255, 391—0 to 391—255, 393—0 to 393—255 are task state management entry status signals
- 342 is a priority determination signal
- 351, 381, 392 and 394 are external array update control signals
- 352 is an array update control signal 352.
- the main processor interface 310 includes a control register group that defines the operation of the task management processor 300, and controls control register access between the internal bus 500 and the task management processor unit.
- the task state management array 330 has 256 task state management entries. As a task pool configured by hardware, the task state management array 330 is reduced through the task state management array control node 312. At least the task status and execution priority of each task are stored, and task status management entry comparison signals 331-0 to 331-255 are output according to the contents of the task status management array search signal 313.
- Each task state management entry comprises a multi-bit storage element having a data shift function and a data comparison function, and has a function as a CAM. As will be described in detail later, each task state management entry can be further shifted in data between corresponding bit positions of adjacent task state management entries.
- the array access arbitration unit 320 is connected to the access control signal that arbitrates the array access arbitration unit control bus 311 from the main processor interface 310 and the array update control signal 352 from the array update control unit 350.
- Task state management entry status signal generated by the task management processor expansion interface 370 based on the task status management entry status signal 391 0 to 391—255 output by the task management processor (not shown) adjacent to the left side)
- the array access arbitration unit 320 controls read / write access to each task state management entry of the task state management array 330.
- the instruction is given from the main processor interface 310, the task management processor expansion interface 370, and the array update control unit 350.
- the array access arbitration unit 320 controls the read / write operation for the shift operation between task state management entries.
- the priority determination unit 340 uses, for example, the entry 0 (333-0) as the highest priority from the comparison signal indicating the coincidence state among the task state management entry comparison signals 331-0 to 33 1-255. Select one entry according to the specified priority, such as entry 255 (333-255) as the lowest priority, and output a priority judgment signal 342 that identifies the selected entry. Furthermore, the priority determination unit 340 generates a task state management entry state generated by the task management processor extended interface 380 and output to a task management processor (not shown) adjacent to the downstream side (right side in the figure). Outputs task status management entry status signals 341-0 to 341-255, which are the sources of signals 393-0 to 393-255.
- the task management processor extension interface 380 is a task management processor adjacent to the downstream side (right side of the figure). The determination result by the priority determination unit 340 can be output to a server (not shown).
- the array update control unit 350 receives an array update request in the external array update control signal 381 generated by the task management processor extension interface 380 from the external array update control signal 394, or in the main processor interface 310. If there is an array update request in the array update control unit control signal 314 that reflects the control register setting, the array update control unit 320 and the task ID table 360 are updated via the array update control signal 352. Requests shift processing of task status management entries and corresponding task IDs based on the request contents. Furthermore, in addition to outputting the external array update control signal 351 reflecting the requested shift processing content as the external array update control signal 392 via the task management processor expansion interface 370, the array update control unit control signal 315 executes the shift processing execution. The presence or absence is notified to the main processor interface 310.
- the task ID table 360 stores a task ID corresponding to each task stored in the task state management array 330 according to the task ID table control bus 316 as a task pool configured by hardware,
- the task ID corresponding to the priority determination signal 342 output by the priority determination unit 340 is output to the task ID table control bus 316.
- a shift process of the corresponding task ID is performed.
- the task ID table 360 uses a multi-bit storage element having a data shift function as one table entry so that data can be shifted in one direction between corresponding bit positions of adjacent table entries. Has multiple table entries.
- the task ID table 360 has a one-to-one correspondence between the table entries and the storage element array entries.
- the entry (data table entry) in the task ID table 360 is subjected to a data shift operation in synchronization with the data shift operation for the entry in the storage element array.
- the task ID table 360 outputs the task ID held by the table entry corresponding to one entry identified by the priority determination unit 340.
- Task management processor expansion interfaces 370 and 380 are task status inter-entry reentry status signals 341-0 to 341-0 based on comparison signals 331-0 to 331-255 output from each task status management entry of the task status management array. Control to transmit 341-255 to the same task status management entry of the adjacent task management processor, or not to transmit it if necessary.
- external array update control signals 394 and 392 that control the shift operation of the task state management entry are also transmitted between adjacent task management processors, and the task update management unit 350 causes the task state management entry contents to be adjacent to each other. Control so that there is no conflict between processors.
- the same task state management entries of each task state management array can be logically combined and operated as a single entry, so the size of the entries can be scaled. It is possible to change to Needless to say, the task management processor expansion interface 370, 380, task state management entry state signal 341—0 to 341—255, 371 -0 to 371 -255, 391- 0 to 391-255, 393— 0 to 393—255, and part or all of the external array update control signals 351, 381, 392, 394 can be deleted to reduce the hardware scale of the task management processor 300.
- the task status management entry status signals 391-0 to 391-255 from the previous stage indicate that the comparison results in the previous stage do not match, they are positioned as signals that limit the validity of the comparison results by the corresponding entries in the task status management array 330. It is done.
- FIG. 4 shows a specific example of the main processor interface 310.
- the main processor interface 310 includes a control register access control unit 317, a control register 318, and a control register access bus 319.
- the control register access control unit 317 responds to an access request from the internal bus 500, and uses the control register 318, the array access arbitration unit control bus 311 and the task state management array control bus 312 via the control register access bus 319. It controls access to the task ID table 360 via the task status management array 330 and the task ID table control bus 316 via the route. Furthermore, according to the contents of control register 318, task status management array search signal 313 and array update control unit control signal 314 are output, and according to the contents of array update control unit control signal 315 and priority determination signal 342 , Update the contents of control register 318.
- the control register 318 is a search request field 318-1, which indicates the presence / absence of a search request for the task state management array 330, and a code string including a predetermined task state and execution priority as a search key for the task state management array 330 Or a search key field 318-2 for storing a predetermined code for searching for an empty entry position in the task state management array 330, a search result valid field 318-2 indicating the validity of the search result, and if the search result is valid Task ID field 318-4, entry position field 318-5 for storing the task ID corresponding to each, and the entry position in the task state management array 330, and the array update control unit 350 requesting task state management entry shift processing Task status update array update request field 318-6, contents of the shift process, eg Specify the displacement force of "ONE SHOT" (performs one shift per request) or "FULL” (performs a maximum (number of entries—1) shifts per request) Task state management array update mode field to be executed 3
- FIG. 5 shows a specific example of the task state management array.
- the task state management array 330 includes an entry access control unit 332, 256 task state management entries 333-0 to 333-255, an inter-entry shift data bus 334-1 to 334-255, and an entry access bus 335.
- each task state management entry has an enable field 333-0-1 to 333-255-1 that indicates whether the contents of the entry are valid, of the task information stored in the entry.
- Task status field indicating the task status 333— 0— 2 to 333 — 255— 2
- the entry access control unit 332 relays access from the task state management array control bus 312 to each task state management entry 333-0 to 333-255.
- Task state management entries 333-0 to 333-255 with entry numbers 0 to 255 respectively are read, write, and shift operations specified by task state management entry control signals 321-0 to 321-255.
- the contents of the entry are output to the entry access bus 335 in response to a request such as, or the predetermined data on the entry access bus 335, some! / Perform operations such as writing the contents to the entry (shift one step downstream).
- the search request and search key on the task state management array search signal 313 the contents of the entry are checked for consistency with the search key, and the result is output to the task state management entry comparison signal 331-0 to 331-255. To do.
- FIG. 6 shows an example of the task state management entry.
- Task state management entry 333—1 is (m
- Task state management cell 800 0-800 m
- task state management cell comparison bus 811 the sum of the bit widths of the enable field 333-1 1, task status field 333-1 2, and execution priority field 333-1-3 shown in FIG. 5 is m + 1.
- the task state management entry control signal 32 1 1 is the entry shift antenna 321—1, the entry access antenna 321—1-2, the task state management entry state signal 371—1 (see Figure 3). ) Force Generated adjacent array Entry match signal 321-1-3.
- Each of the task state management cells 800-0 to 800-111 operates as a memory circuit with 1-bit shift and comparison functions, and includes the following input / output terminals.
- LS, ZLS Task state management array system expressed in positive logic and negative logic, respectively.
- SK, ZSK Search key input to cells expressed in positive logic and negative logic, respectively, corresponding to the relevant bit in the search key field included in the task state management array search signal 313 and its inversion Connect.
- CB Expressed in negative logic, is a comparison output from the cell indicating the comparison result of 1-bit data input to the terminal SK and held in the cell.
- Task state management cell comparison signal 81 Connect to the signal corresponding to the bit of 0—0 to 810—m.
- the task state management cell comparison bus 811 is connected to the task state management cell comparison signals 810-0 to 810-m output from the (m + 1) task state management cells 800-0 to 800-m. This is a bus that is configured to be able to execute AND operation in negative logic expression by Yard OR.
- the task state management entry comparison unit 820 displays an entry match state when the task state management cell comparison bus 81 1 and the adjacent array entry match signal 321—1-3 indicate a match state.
- the task state management entry comparison signal 331 Output to 1.
- the task state management entry comparison unit 820 can be positioned as an AND circuit.
- task state management entries 333-2 to 333-254 can also be applied by appropriately associating the symbols in FIG.
- the task state management entries 333-0 and 333-255 are each except that the shift data output SO is not connected and an appropriate fixed value (not shown) is input to the shift data input SI.
- the configuration shown in Fig. 6 is applicable.
- FIG. 7 shows a first example of the task state management cell
- FIG. 8 shows a second example of the task state management cell.
- the function of each input / output terminal is the same as that of the corresponding input / output terminal in Fig. 6.
- the terminal ⁇ in FIG. 7 is an operation clock signal of a data processing device not shown in FIGS.
- FIG. 7 shows a first example of the task state management cell
- FIG. 8 shows a second example of the task state management cell.
- the function of each input / output terminal is the same as that of the corresponding input / output terminal in Fig. 6.
- the terminal ⁇ in FIG. 7 is an operation clock signal of a data processing device not shown in FIGS.
- the terminals () SE1 and 0 SE2 in FIG. 8 are signals indicating that the rising edge and the
- the task management processor 300 when performing multitask control in the data processing device 100, the task management processor 300 detailed in FIG. 3 to FIG. 9 is used from the multitask control program operating on the main processor 200.
- the main points are summarized below.
- the task management processor 300 stores at least a task ID, a task state, and an execution priority in the task pool, and the contents are set by the main processor 200.
- the task status is specified by one of "Waiting”, “Ready”, or “Running”
- the execution priority is specified by one of 0 (highest) to 255 (lowest).
- execution priority the same execution priority may be set for multiple tasks.
- the task status management entry 333—0 to 333—255 priority corresponds to the FIF O exit, and the oldest 333-0 in the time sequence is the highest and 333-255 is the lowest.
- the entry priority is different for each entry, and is different from the execution priority. V, the priority is never duplicated! /.
- Task completion The task status management entry that stores the task ID, task status, and execution priority of the task is invalidated.
- Task interruption due to a predetermined switching factor such as an interrupt The task status of the corresponding task is updated from "Running" to "Ready".
- FIG. 10 and FIG. 11 show a task control flow by the task management program operating on the main processor 200.
- step F110 as the initialization of the task management processor 300, all task state management entries are invalidated and initial values are written to the control registers. However, a value 0 indicating entry 0 (333-0) is written in the empty entry pointer field 318-8.
- the task management program monitors the state of the task management processor 300 (step F120), and waits until the state of the task management processor 300 becomes a non-busy state.
- the task management processor 300 enters a non-busy state, the necessary processing is performed depending on whether a task addition or switching request is issued.
- the task addition request is accepted (step F130)
- a task ID and execution priority are assigned to the task
- the task status management entry indicated by the empty entry pointer field 318-8 and the corresponding entry in the task ID table are assigned.
- the contents are updated (step F131) and the contents of the empty entry pointer field 318-8 are incremented (step F132).
- step F140 When a task switching request is received (step F140), the processing contents differ depending on the factor (step F150). First, if the request is due to task completion, the enable field of the task state management entry storing the completed task information is invalidated (step F151), and the empty entry pointer field 318-8 is decremented (Step F152) and array alignment processing (Step F153) for eliminating the misalignment inside the FIFO caused by the invalidation are sequentially executed. If the request is a predetermined task interruption request that is not a task completion, the task status in the task information corresponding to the task being executed is updated from “Running” to “Ready” (step F154).
- the task state management array update request field 318-6 and the task state management array update mode field 318-7 are assigned an array by writing to the control register. Alignment request (step F210) and wait until array alignment processing is completed (step F220). The operation of the task management processor in response to the array alignment request will be described later with reference to FIGS.
- step F155 When the task completion or suspension processing is completed, a task to be executed next is searched (step F155), and when one executable task is selected (step F160), The task status is updated from “Ready” to “Running” (step F161), and the task is notified of execution permission.
- next task search (step F155) is as illustrated in FIG.
- the search key field 318-2 a search key indicating a candidate for a task to be executed next, for example, the enable field is “valid”, the task status field is “Ready”, and the execution priority field is set.
- Sets “0 (highest priority)” (step F310), and requests a search in the task state management array 330 by writing to the search request field 318-1 (step F320).
- step F330 If the contents of the search result valid field 318—3 indicate that the search result is valid and valid next task information matching the search key is found (step F330), the task ID field 318—4 and the entry position field 318—5 Is received as the task ID and entry number corresponding to the task to be executed next (step F331). If no valid next task is found, the execution priority in the search key is sequentially incremented to 255 (lowest priority) and the search request is repeated (steps F340 and F341).
- the task management processor 300 responding to the search request (step F320) in the task state management array 330 performs a search according to the search key and receives the comparison result 340 receives the entry priority of the comparison result.
- the highest entry will be identified and given to task ID table 360.
- the task management processor 300 can easily guarantee the time order of entries uniquely, the required task ID is identified by adding the priority according to the time order to the search results by the CAM. be able to. As a result, priority control of task selection in consideration of the time order can be performed quickly and easily.
- the execution priority increment and the re-search request are not limited to the method in which the main browser processor processes all execution priorities as described above, but the execution priority within a predetermined range.
- the search target and the processing of the main processor 200 are selected by adopting a method that automatically performs re-search in the task management processor 300 regardless of the main processor 200. It is also possible to reduce the load, realize flexible, real-time performance, and multitask control.
- Array alignment means that when a task that is being executed is completed and the task information is deleted from the task state management entry in the task state management array that constitutes the FIFO, the valid entry is not found by shifting the adjacent entry. This process eliminates continuity. This makes it easy to guarantee the time order within the task state management array, and multitasking control is simplified by determining the next entry to which a task should be added because there are consecutive valid entries. As a result, the processing time for task switching can be reduced.
- a search key including the contents of the search key field 318-2 is normally output as a task state management array search signal 313 (step F410), and the operation state of the task management processor is set to "non-display". Set to "Busy" state (step F411).
- the search processing is executed, and the search result valid field 318-3, task ID field 318-4, entry position is executed according to the result.
- Update the contents of field 318-5 step F340).
- the array update control unit 350 updates the processor operating state to the “busy” state (step F421), and updates control.
- a signal corresponding to the content of the signal is output to the array update control signal 35 2.
- the array access arbitration unit 320 requests a shift operation to the task state management array 330 via the entry shift enable for the task state management entry to be shifted, and the shift process is executed. (Step F422).
- the contents of the task ID table 360 are also updated consistent with the contents of the task state management array 330 in response to the array update control signal 352.
- step F423 The content of the above shift operation is notified to the adjacent processor by the external array update control signal 351 (step F423).
- the shift operation is executed without any contradiction among all the task management processors connected.
- the processor operation state is updated to a “non-busy” state, and monitoring is performed for subsequent processing requests.
- the main processor issues an array alignment request.
- the array alignment request from the main processor is received via the task state management array update request field 318-6 (step F430)
- the array update processing (step F431) described in detail below is executed.
- a special search key whose enable field is "invalid” and whose task status field and execution priority field are both "comparison mask”.
- the operation state of the task management processor 300 is updated to the “busy” state, and then the contents of the shift counter CNT in the array update control unit 350 are updated.
- step F512 It is initialized to 0 (step F512), and the empty entry with the highest priority, that is, the entry number with the smallest entry number is searched for (empty entry) (step F513). Shift all task state management entries with the entry number (step F521), and transfer the contents of the shift operation to the adjacent processor.
- Step F522 If “FULL” is specified in the task status management array update mode field 318-7 (step F530), the shift counter CNT is incremented (step F531), and the shift counter Repeat the search for empty entries until the CNT contents are 254, that is, (the number of entries in the task status management entry-1) (step F540) No empty entries exist, or shift 254 times in "FULL" mode
- the operation state of the task management processor 300 is updated to the “non-busy” state (step F541), and the search key included in the task state management array search signal 313 is reset as the original search key. (Step F542) makes it possible to accept subsequent processing requests.
- the task management program completes or suspends only one task at a time. As long as the rules regarding the order of use of task state management entries are observed, the task state can be changed by one entry shift operation. The misaligned state of the management array is resolved. Data processing device that avoids problems that may be included in the task management program In order to improve reliability, you should perform "FULL" shift regularly! /.
- the main processor 200 and the task management processor 330 are not necessarily limited to being mounted on the same chip.
- Array 330 and table 360 may be configured in the same or different arrays.
- the present invention is not limited to the case where it is applied to task control, but can be widely applied to other data management that must be managed in consideration of real-time characteristics.
Abstract
Description
Claims
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US12/280,005 US20090320034A1 (en) | 2006-03-27 | 2006-03-27 | Data processing apparatus |
JP2008507296A JP5024899B2 (ja) | 2006-03-27 | 2006-03-27 | データ処理装置 |
PCT/JP2006/306089 WO2007110906A1 (ja) | 2006-03-27 | 2006-03-27 | データ処理装置 |
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US8201177B2 (en) * | 2007-11-19 | 2012-06-12 | International Business Machines Corporation | Scheduling a workload based on workload-related variables and triggering values |
US8255908B2 (en) * | 2007-12-19 | 2012-08-28 | Nokia Corporation | Managing tasks in a distributed system |
JP6445718B2 (ja) * | 2015-04-14 | 2018-12-26 | 華為技術有限公司Huawei Technologies Co.,Ltd. | プロセス管理方法、装置、およびデバイス |
US20180025289A1 (en) * | 2016-07-20 | 2018-01-25 | Qualcomm Incorporated | Performance Provisioning Using Machine Learning Based Automated Workload Classification |
US20180024859A1 (en) * | 2016-07-20 | 2018-01-25 | Qualcomm Incorporated | Performance Provisioning Using Machine Learning Based Automated Workload Classification |
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JP2004326767A (ja) * | 2003-04-25 | 2004-11-18 | Internatl Business Mach Corp <Ibm> | マルチスレッド・プロセッサにおいて命令スレッドのインタリービングをランダム化するための方法および装置 |
JP2005078450A (ja) * | 2003-09-01 | 2005-03-24 | Oki Electric Ind Co Ltd | タスク制御方法とタスク切替装置 |
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US4710933A (en) * | 1985-10-23 | 1987-12-01 | Texas Instruments Incorporated | Parallel/serial scan system for testing logic circuits |
US4872169A (en) * | 1987-03-06 | 1989-10-03 | Texas Instruments Incorporated | Hierarchical scan selection |
DE69227664T2 (de) * | 1991-10-15 | 1999-04-22 | Hewlett Packard Co | Hardwarekonfiguriertes Betriebssystemkern für einen Multitaskprozessor |
US6055649A (en) * | 1997-11-19 | 2000-04-25 | Texas Instruments Incorporated | Processor test port with scan chains and data streaming |
JP2001075820A (ja) * | 1999-09-07 | 2001-03-23 | Oki Electric Ind Co Ltd | リアルタイムos装置 |
JP2006040149A (ja) * | 2004-07-29 | 2006-02-09 | Toshiba Corp | 半導体集積回路装置 |
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JP2004326767A (ja) * | 2003-04-25 | 2004-11-18 | Internatl Business Mach Corp <Ibm> | マルチスレッド・プロセッサにおいて命令スレッドのインタリービングをランダム化するための方法および装置 |
JP2005078450A (ja) * | 2003-09-01 | 2005-03-24 | Oki Electric Ind Co Ltd | タスク制御方法とタスク切替装置 |
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