WO2007108534A1 - 電圧制御発振回路 - Google Patents
電圧制御発振回路 Download PDFInfo
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- WO2007108534A1 WO2007108534A1 PCT/JP2007/056025 JP2007056025W WO2007108534A1 WO 2007108534 A1 WO2007108534 A1 WO 2007108534A1 JP 2007056025 W JP2007056025 W JP 2007056025W WO 2007108534 A1 WO2007108534 A1 WO 2007108534A1
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- voltage
- circuit
- temperature
- oscillation
- frequency
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- 230000010355 oscillation Effects 0.000 title claims abstract description 131
- 239000003990 capacitor Substances 0.000 claims abstract description 23
- 238000001514 detection method Methods 0.000 claims description 60
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 22
- 238000000034 method Methods 0.000 description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 230000002542 deteriorative effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 230000005236 sound signal Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L1/00—Stabilisation of generator output against variations of physical values, e.g. power supply
- H03L1/02—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only
- H03L1/022—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature
- H03L1/023—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature by using voltage variable capacitance diodes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/113—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using frequency discriminator
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Definitions
- the present invention relates to a voltage controlled oscillation circuit (hereinafter referred to as a VCO (Voltage Contaminated Oiled Oscillator) circuit) including temperature detection means, and a wireless communication apparatus including the same.
- VCO Voltage Contaminated Oiled Oscillator
- Patent Document 1 discloses a phase locked loop circuit (hereinafter referred to as a PLL (Phase Locked Loop) circuit) using a VCO circuit having a wide oscillation frequency range.
- PLL Phase Locked Loop
- FIG. 11 is a block diagram showing a configuration of a PLL circuit 100 according to the prior art described in Patent Document 1.
- the resonant circuit formed by the variable capacitance diode CV, the capacitors C2 and C3, and the inductor L1 connected in parallel to each other is a variable capacitance diode CV and a capacitor C2.
- C 3 and the inductor L 1 have a predetermined resonance frequency, and the oscillator 6 generates and outputs an oscillation signal having an oscillation frequency corresponding to the resonance frequency using a resonance circuit.
- the resonant frequency of the VCO circuit 200 is roughly adjusted by first applying the output voltage V of the constant voltage source 18 to the variable capacitance diode CV by the switch SW3 and controlling the switches SW1 and SW2 to select a band,
- the voltage is finely adjusted by the PLL circuit 100 by applying a voltage from a low-pass filter (hereinafter referred to as LPF) 11 to the variable capacity diode CV via the voltage application terminal Tin by the switch SW3.
- LPF low-pass filter
- FIG. 12 and FIG. 13 show the voltage V applied to the variable capacitance diode CV (hereinafter referred to as “V”) which indicates the temperature change from low temperature to high temperature and high temperature to low temperature in the PLL circuit 100 of FIG.
- V variable capacitance diode CV
- the initial lock range which is the initial voltage range locked to the OSC, is set.
- f to f indicate the lower limit or upper limit of each band B1 to B4.
- variable capacitance applied voltage V is above the initial lock range ⁇
- the PLL circuit 100 locks in the low temperature lock position P11. after that,
- f to f are the lower limits or the respective bands B1 to B4.
- variable capacitance applied voltage V is the lower limit ⁇ of the initial lock range
- the PLL circuit 100 locks at the high temperature lock position P13. After that, when the temperature drops, the characteristics of the oscillation frequency f generally increase.
- Patent document 1 Patent 3488180.
- the PLL circuit 100 forces a predetermined temperature margin on both sides of the initial locking range in order to take into account the temperature fluctuation after the initial locking.
- the problem is that the oscillation frequency range is narrowed by the temperature margin.
- the oscillation frequency range is, for example, by increasing each set of switches SW1 and SW2 and capacitors CI and C2 connected in series to switches SW1 and SW2, respectively, in the resonance circuit of VCO circuit 200 in FIG. Expandable Force
- the size of the resonant circuit is increased, and when the VCO circuit is incorporated into a semiconductor integrated circuit, the parasitic capacitance added to the resonant circuit is increased and the phase noise of the VCO circuit is degraded.
- the current of the VCO circuit it is possible to suppress the influence of the phase noise deterioration due to the increase of the parasitic capacitance. In this case, the power consumption increases.
- the frequency control sensitivity f / V
- the oscillation frequency range can be expanded by setting the OSC T high, but in this case, the variable capacitance applied voltage
- An object of the present invention is to solve the above problems and to provide a voltage controlled oscillation circuit having a wide oscillation frequency range that does not deteriorate phase noise, and a wireless communication apparatus including the same.
- a voltage control oscillation circuit detects temperature and generates and outputs a first control voltage for coarse adjustment corresponding to the detected temperature; Switching means for selecting one of the second control voltage for fine adjustment and the first control voltage for coarse adjustment, and adjustment based on the control voltage selected by the switch means.
- Oscillation circuit having an oscillation frequency corresponding to the resonance frequency using a resonance circuit having a predetermined resonance frequency and including a variable capacitance element having a capacitance value, at least one capacitor, and an inductor, and using the resonance circuit And an oscillating means for generating and outputting a signal.
- the temperature detection means is operated by a power supply voltage, and the applied power supply voltage is controlled according to a power supply control signal inputted.
- the voltage controlled oscillation circuit further includes current control means for controlling the current of the oscillation means in accordance with the temperature detected by the temperature detection means.
- the temperature detection means holds the first control voltage constant when the switch means selects the first control voltage. It features.
- the voltage controlled oscillator circuit further includes a phase locked loop circuit that generates the second control voltage based on an oscillation signal output from the voltage controlled oscillator circuit.
- a wireless communication apparatus is a wireless communication apparatus that transmits and receives a wireless signal. And a frequency conversion means for frequency-converting a radio signal using the control type oscillation circuit and an oscillation signal from the voltage control oscillation circuit.
- the temperature is detected and the first control voltage for coarse adjustment corresponding to the detected temperature is generated. Since the temperature detection means to output is provided, the temperature margin of the oscillation frequency can be reduced, and if the wide oscillation frequency range can be obtained without deteriorating the phase noise, an advantageous effect is produced.
- FIG. 1 is a block diagram showing a configuration of a PLL circuit 1 according to a first embodiment of the present invention.
- FIG. 2 is a circuit diagram showing an example of a detailed configuration of a temperature detection circuit 4 and a voltage generation circuit 5 of FIG.
- FIG. 3 A characteristic diagram showing the relationship between a variable capacitance applied voltage V and an oscillation frequency f, which shows temperature change to low temperature power and high temperature in the PLL circuit 1 of FIG.
- FIG. 4 is a characteristic diagram showing the relationship between a variable capacitance applied voltage V and an oscillation frequency f, which shows temperature change to high temperature power and low temperature in the PLL circuit 1 of FIG.
- FIG. 5 is a flowchart showing a channel selection process in the PLL circuit 1 of FIG. 1;
- FIG. 6 is a block diagram showing a configuration of a PLL circuit 1A according to a second embodiment of the present invention.
- FIG. 7 is a block diagram showing a configuration of a PLL circuit 1B according to a third embodiment of the present invention.
- FIG. 8 is a block diagram showing a configuration of a PLL circuit 1C according to a fourth embodiment of the present invention.
- FIG. 9 is a circuit diagram showing an example of a detailed configuration of a temperature detection circuit 4C and a voltage generation circuit 5 of FIG.
- FIG. 10 is a block diagram showing a configuration of a wireless communication apparatus provided with the PLL circuit 1 of FIG.
- FIG. 11 is a block diagram showing a configuration of a PLL circuit 100 according to the prior art.
- FIG. 12 is a characteristic diagram showing the relationship between the variable capacitance applied voltage V and the oscillation frequency f, which shows the temperature change from low temperature to high temperature in the PLL circuit 100 of FIG.
- FIG. 13 is a characteristic diagram showing the relationship between the variable capacitance applied voltage V and the oscillation frequency f, in which the high-temperature force in the PLL circuit 100 of FIG. 11 also indicates the temperature change to a low temperature. Explanation of sign
- LNA low noise amplifier
- Tvc Power control terminal.
- FIG. 1 is a block diagram showing a configuration of a PLL circuit 1 according to a first embodiment of the present invention.
- a PLL circuit 1 is used, for example, to generate a local oscillation signal in a tuner or the like, and a VCO circuit 2, a reference frequency divider 7, an oscillation frequency divider 8, and a phase comparator 9 , A charge pump 10, a low pass filter (hereinafter referred to as "LPF") 11, a frequency adjustment controller 12, and a reference frequency generator 19.
- LPF low pass filter
- Each component in PLL circuit 1 is formed on one IC chip.
- the reference frequency generator 19 generates a reference frequency signal having a predetermined reference frequency, and outputs the reference frequency signal to the reference frequency divider 7.
- the reference frequency divider 7 divides the input reference frequency signal by a predetermined dividing ratio, and divides the divided reference frequency signal f into a phase comparator 9 and a frequency divider.
- the oscillation frequency divider 8 receives the input oscillation frequency signal f
- the OSC is divided by a predetermined division ratio, and the oscillation frequency signal f after division
- the DIV is output to the phase comparator 9 and the frequency adjustment controller 12.
- the phase comparator 9 compares the phase of the input reference frequency signal f after division and the phase of the oscillation frequency signal f after division, and
- the DC voltage is output to the VCO circuit 2 through the charge pump 10 and the LPF 11 as the comparison result signal.
- the frequency adjustment controller 12 receives the frequency-divided reference frequency signal f
- the difference with the DIV frequency is detected, and according to the detected difference, selection of coarse adjustment and fine adjustment and selection of bands (details will be described later) are performed.
- the VCO circuit 2 includes a temperature detection circuit 4, a voltage generation circuit 5, an oscillator 6, switches SW 1, SW 2, SW 3, capacitors CI, C 2, C 3, a variable capacitance diode CV, an inductance It comprises with LI.
- the capacitors C2 and C3, the variable capacitance diode CV, the switches SW1 and SW2, and the inductance L1 are the capacitance values of the variable capacitance diode CV and the capacitors C2 and C3, and the inductance value of the inductor L1.
- the temperature detection circuit 4 detects a temperature, and outputs a signal of a temperature detection result corresponding to the detected temperature to the voltage generation circuit 5.
- the voltage generation circuit 5 generates and outputs a voltage corresponding to the signal of the temperature detection result from the temperature detection circuit 4.
- the switch SW3 selects the contact a or the contact b according to the control signal input through the control terminal Tel, and applies the output voltage from the voltage generation circuit 5 to the variable capacitance diode CV when the contact a is selected.
- the contact point b is selected, the DC voltage from the LPF 11 is applied to the variable capacitance diode CV via the voltage application terminal Tin.
- the capacitor C1 and the variable capacitance diode CV are connected in series with each other to form a series circuit, and the series circuit is provided between the oscillator 6 and the ground potential.
- the connection point of capacitor C1 and variable capacitance diode CV is connected to the common terminal of switch SW3.
- the capacitance value of the variable capacitance diode CV is determined by the bias voltage applied via the switch SW3.
- the capacitor C1 separates the DC bias voltage applied to the variable capacitance diode CV from the bias
- the switches SW1 and SW2 are controlled by respective control signals inputted from the frequency adjustment controller 12 via the control terminals Tc2 and Tc3 respectively, and when turned on, the capacitors C2 and C3 are connected in series with the capacitor C1 and the variable capacitance diode CV. Connect in parallel with the circuit, and when off, disconnect capacitors C2 and C3, respectively, in series with capacitor C1 and capacitive diode CV.
- the inductance L1 is connected in parallel with the series circuit of the capacitor C1 and the variable capacitance diode CV.
- the oscillator 6 has an oscillation frequency f corresponding to the resonance frequency using the above-described resonance circuit.
- the oscillation signal f output from the oscillation signal output terminal Tout is input to the oscillation frequency divider 8, and the phase comparator 9, the charge pump
- FIG. 2 is a circuit diagram showing an example of a detailed configuration of temperature detection circuit 4 and voltage generation circuit 5 of FIG.
- the temperature detection circuit 4 includes current sources 13 and 14, resistors R1 and R2, and a comparator 15.
- the voltage generation circuit 5 includes constant voltage sources 21 and 22 and a switch SW4. To be configured.
- Current source 13 is connected to power supply potential Vdd, and changes with a predetermined temperature characteristic of voltage V between base emitter of bipolar transistor constituting current source 13
- the voltage source 14 is connected to the power supply potential Vdd, and outputs a constant current regardless of temperature change.
- the resistors Rl and R2 respectively convert the current supplied by the current sources 13 and 14 into a voltage and apply them to the non-inverted input terminal (+) and the inverted input terminal (one) of the comparator 15, respectively.
- a predetermined threshold determined by the resistance ratio of the resistors R1 and R2 is obtained.
- the output voltage of the comparator 15 can be changed according to whether it is less than the value temperature.
- the comparator 15 has a voltage level that is lower than a predetermined threshold temperature and OV at a low temperature, and is a predetermined power supply voltage at a temperature higher than a predetermined threshold! /. Output a signal having a voltage level.
- the switch SW4 of the voltage generation circuit 5 outputs the output voltage V of the constant voltage source 21 through the contact a and the contact a of the switch SW3 of FIG. Is applied to the variable capacitance diode CV as a control voltage for coarse adjustment, and the output of the comparator 15 is
- the output voltage V of the constant voltage source 22 is used as the control voltage for coarse adjustment through the contact b and the contact a of the switch SW3 in FIG.
- FIG. 3 is a characteristic diagram showing the temperature change from low temperature to high temperature in the PLL circuit 1 of FIG. 1 and showing the relationship between the variable capacitance applied voltage V and the oscillation frequency f.
- the solid line is
- the temperature detected by the temperature detection circuit 4 is lower than or equal to a predetermined threshold temperature
- the relationship between the variable capacitance applied voltage V and the oscillation frequency f is shown, and the alternate long and short dash line indicates
- V and V are the output lower limit voltage and output upper limit charge of charge pump 10 respectively
- bands B1 to B4 Indicates pressure.
- the characteristics of bands B1 to B4 are the relationship between the variable capacitance applied voltage V and the oscillation frequency f by the combination of the switches SWl and SW2 of the VCO circuit 2 in FIG.
- switch SW1 and SW2 are both on in band B1, only switch SW1 is on in band B2, only switch SW2 is on in band B3, and switch SW1 and SW2 are both off in band B4. It is. f to f
- ALl AL5 indicates the lower limit or upper limit oscillation frequency in each band B1 to B4, and oscillates from oscillation frequency f to oscillation frequency f in band B1, and oscillation frequency f in band B2
- ALl AL2 AL2 oscillates from oscillation frequency f, and in band B3, oscillation frequency f to oscillation frequency f
- AL3 AL3 It oscillates at AL4 and oscillates from oscillation frequency f to oscillation frequency f in band B4.
- the VCO circuit 2 in Fig. 1 is in the frequency range from the oscillation frequency f to the oscillation frequency f.
- V is the output voltage of the constant voltage source 22
- V is the output voltage of the constant voltage source 21
- V is the lower limit value of the initial lock range.
- the DC voltage from the LPF 11 is applied to the variable capacitance diode CV by W 3, and the oscillation frequency f is finely adjusted and locked by the PLL circuit 1. In addition, because of the fine adjustment operation,
- T 2 OSC is locked at the cold lock position PI, which is f. After that, if the temperature rises, oscillation
- the characteristic of the frequency f is totally reduced.
- variable capacitance application voltage V decreases.
- variable capacitance diode cv The temperature of the low-voltage side of the variable capacitance applied voltage V is applied to the variable capacitance diode cv.
- the initial lock range can be expanded by the reduced temperature margin, that is, the oscillation frequency range can be expanded.
- the temperature margin is reduced, and the initial lock range and the oscillation frequency range are expanded as compared with FIG. 12 describing the operation of the conventional PLL circuit 100.
- FIG. 4 is a characteristic diagram showing the relationship between the variable capacitance applied voltage V and the oscillation frequency f, which shows temperature change to high temperature power and low temperature in the PLL circuit 1 of FIG.
- the solid line is
- V and V and bands B1 to B4 are the same as in FIG. f ⁇ f is each band B1
- Circuit 2 has an oscillation frequency in the frequency range from oscillation frequency f to oscillation frequency f
- V is the output voltage of the constant voltage source 22 and V indicates the upper limit value of the initial lock range when the lower limit value of the initial lock range is the voltage V
- the DC voltage from the LPF 11 is applied to the variable capacitance diode CV, and the oscillation frequency f is finely adjusted and locked by the PLL circuit 1.
- the fine adjustment operation at the time of coarse adjustment The states of the set switches SW1 and SW2 are not changed.
- the variable capacitance application voltage V is the lower limit V of the initial lock range, and the oscillation frequency f is f
- the characteristics increase as a whole, but the PLL circuit 1 changes the variable capacitance applied voltage V to the voltage V.
- variable capacitance application voltage V increases.
- the voltage V is applied to the variable capacity diode CV by the switch SW4 of the voltage generation circuit 5, and the temperature margin on the high voltage side of the variable capacity applied voltage V is determined.
- the initial lock range can be expanded by the reduced temperature margin, that is, the oscillation frequency range can be expanded.
- the temperature margin is reduced, and the initial lock range and the oscillation frequency range are expanded! / Sl compared to FIG. 13 which describes the operation of the PLL circuit 100 according to the prior art.
- FIG. 5 is a flowchart showing a tuning process when the PLL circuit 1 of FIG. 1 is used as a tuner.
- the target oscillation frequency is f.
- step S50 of FIG. 5 the temperature is detected by the temperature detection circuit 4, and it is determined in step S51 whether the detected temperature is lower than a predetermined threshold temperature. At this time, the process proceeds to step S52, and when NO, the process proceeds to step S53. In step S52, after the output voltage V of the constant voltage source 21 is selected and output by the switch SW4, the step is performed.
- step S54 After the output voltage V of the constant voltage source 22 is selected and output by the switch SW4 in step S53, the process proceeds to step S54. Note that steps S50 to S53 are temperature determination processing.
- step S 54 the control voltage for coarse adjustment from voltage generation circuit 5 is applied to variable capacitance diode CV by switch SW 3, and in step S 55, for example, band B 3 is selected as an initial value by switches SW 1 and SW 2. .
- step S56 the frequency adjustment controller 12 divides the reference frequency f and the divided oscillation frequency f.
- a control signal for reselecting an appropriate band according to the difference is applied to switches SW1 and SW2 to detect an oscillation frequency f.
- step S59 the oscillation frequency f is equal to or higher than the lower limit frequency f and the upper limit
- step S60 a DC voltage which is a control voltage for fine adjustment from the LPF 11 is applied to the variable capacitance diode CV by the switch SW 3 to thereby form a closed loop with the PLL circuit 1 and the VCO circuit 2, step S6 1 So that the oscillation frequency f becomes the target oscillation frequency f by the PLL circuit 1
- FIG. 10 is a block diagram showing a configuration of a wireless communication apparatus provided with the PLL circuit 1 of FIG.
- the wireless communication apparatus includes a PLL circuit 1, an antenna 30, a circulator 31, a low noise amplifier (hereinafter referred to as LNA) 32, and a band pass filter (hereinafter referred to as BPF) 33, 36. , Mixers 34 and 37, a power amplifier (hereinafter PA) 35, and a non-base processing circuit 38.
- PLL circuit 1 an antenna 30, a circulator 31, a low noise amplifier (hereinafter referred to as LNA) 32, and a band pass filter (hereinafter referred to as BPF) 33, 36.
- BPF band pass filter
- the radio reception signal received by antenna 30 is amplified to a level necessary for low-pass frequency conversion via circulator 31 and LNA 32, and then desired by BPF 33. It filters out the radio reception signal in the reception band and outputs it.
- the mixer 34 receives the oscillation signal f from the PLL circuit 1 and the desired reception band from the BPF 33.
- the signal is mixed with the radio reception signal of the frequency converter to convert the frequency to an intermediate frequency signal having a predetermined intermediate frequency and output to the baseband processing circuit 38.
- the transmission signal from the baseband processing circuit 38 is mixed with the oscillation signal f from the PLL circuit 1 by the mixer 37 and transmitted with a predetermined transmission frequency.
- the transmission signal in the desired transmission band is band pass filtered by the BPF 36 and transmitted wirelessly via the PA 35, the circulator 31 and the antenna 30.
- the temperature detection circuit 4 for detecting a temperature, and a control voltage for coarse adjustment corresponding to the detected temperature are generated and output. Since the voltage generation circuit 5 is provided, the temperature margin of the oscillation frequency can be reduced, and a wide oscillation frequency range which does not deteriorate the phase noise can be obtained.
- a force having two temperature divisions at low temperature and high temperature in the temperature detection circuit 4 and the voltage generation circuit 5, a force having two temperature divisions at low temperature and high temperature.
- the present invention is not limited to this configuration, and three or more temperatures may be used. It may have a degree division.
- temperature detection circuit 4 outputs a plurality of different temperature detection signals depending on the temperature, and voltage generation circuit 5 operates so as to switch a plurality of output voltages according to the input temperature detection signal. Good. At this time, the output voltage of the voltage generation circuit 5 may be continuously changed according to the temperature detected by the temperature detection circuit 4.
- temperature detection circuit 4 and voltage generation circuit 5 have the configuration shown in FIG. 2, the present invention is not limited to this configuration, and any other configuration can be used as long as it can output a voltage corresponding to temperature. A little
- the present invention is not limited to this configuration, and one or three capacitors may be provided to obtain a desired oscillation frequency range and frequency control sensitivity. More than one capacitor may be connected in parallel with the variable capacitance diode CV.
- the resonance circuit includes a variable capacitance diode CV, capacitors C2 and C3, and switches SW1 and SW2.
- the present invention is not limited to this configuration.
- a capacitive element using a gate capacitance of a MOS transistor or the like may be used. It may be another configuration.
- VCO circuit 2 is an unbalanced type.
- the present invention is not limited to this configuration, and may be a balanced type using, for example, a differential circuit.
- the current source 13 outputs a current that changes according to the temperature characteristic of the voltage V between the base and the emitter of the bipolar transistor that constitutes the current source 13.
- the voltage source 14 outputs a constant current regardless of the temperature change.
- the present invention is not limited to this configuration, and the current source 14 is set to output a current that changes in the temperature characteristic of the voltage V between the base and the emitter of the bipolar transistor that constitutes the current source 14.
- FIG. 6 is a block diagram showing a configuration of a PLL circuit 1A according to a second embodiment of the present invention.
- a PLL circuit 1A according to the present embodiment includes a VCO circuit 2A in place of the VCO circuit 2 of FIG. 1 in comparison with the PLL circuit 1 according to the first embodiment shown in FIG. Is different.
- the VCO circuit 2A differs from the VCO circuit 2 of FIG. 1 in that the temperature detection circuit 4A and the voltage generation circuit 5A are provided instead of the temperature detection circuit 4 and the voltage generation circuit 5.
- the PLL circuit 1A is the same as the PLL circuit 1 according to the first embodiment shown in FIG. 1 in the other points, and the detailed description of the components denoted by the same reference numerals is omitted.
- temperature detection circuit 4A and voltage generation circuit 5A are operated by the power supply voltage, and the applied power supply voltage is controlled in accordance with the power supply control signal inputted through power supply control terminal Tvc. Ru. Specifically, at the time of coarse adjustment, that is, when the output voltage of the voltage generation circuit 5A is selected by the switch SW3, the temperature detection circuit 4A and the voltage generation circuit 5A are applied with predetermined power supply voltages, and at the time of fine adjustment That is, when the DC voltage from the LPF 11 is selected by the switch SW3 via the voltage application terminal Tin, the power supply voltage of the temperature detection circuit 4A and the voltage generation circuit 5A is cut off or the current is reduced by the power control signal.
- the other operations are the same as those of the PLL circuit 1 of FIG. 1 according to the first embodiment, and therefore the description thereof is omitted.
- the power supply voltage is applied to the temperature detection circuit 4A and the voltage generation circuit 5A at the time of coarse adjustment of the oscillation frequency, and the temperature at the time of fine adjustment. Since the power supply voltage of the detection circuit 4A and the voltage generation circuit 5A is cut off or the current is reduced, power consumption can be reduced compared to the PLL circuit 1 according to the first embodiment.
- FIG. 7 is a block diagram showing a configuration of a PLL circuit 1B according to a third embodiment of the present invention.
- a PLL circuit 1B according to the present embodiment includes a VCO circuit 2B instead of the VCO circuit 2 of FIG. 1 in comparison with the PLL circuit 1 according to the first embodiment shown in FIG. Is different.
- VCO circuit 2B includes oscillator 6B instead of oscillator 6 in comparison with VCO circuit 2 of FIG. 1, and a current control circuit connected between temperature detection circuit 4 and oscillator 6B.
- the difference is that the road 20 is further provided.
- the PLL circuit 1B is the same as the PLL circuit 1 according to the first embodiment shown in FIG. 1 in the other points, and the detailed description of the components given the same reference numerals is omitted. .
- current control circuit 20 controls the current of oscillator 6 B according to the signal of the temperature detection result from temperature detection circuit 4. Specifically, when the signal of the temperature detection result of the temperature detection circuit 4 indicates that it is higher than the predetermined temperature, the current of the oscillator 6B is increased, and the signal of the temperature detection result of the temperature detection circuit 4 is When it is indicated that the temperature is below the predetermined threshold temperature, the current of the oscillator 6 B is decreased, thereby optimizing the current flowing to the oscillator 6 according to the operating temperature. In this case, since the signal of the temperature detection result of the temperature detection circuit 4 is shared by the voltage generation circuit 5 and the current control circuit 20, the current flowing to the oscillator 6B according to the operating temperature is increased with little increase in circuit scale. It can be optimized to maintain good phase noise characteristics over a wide range of temperatures and reduce the current consumption of oscillator 6B.
- the temperature detection result of the temperature detection circuit 4 is used to optimize the current flowing to the oscillator 6B in accordance with the operating temperature. Power consumption can be reduced as compared to the PLL circuit 1 according to the first embodiment.
- FIG. 8 is a block diagram showing a configuration of a PLL circuit 1C according to a fourth embodiment of the present invention.
- a PLL circuit 1C according to the present embodiment includes a VCO circuit 2C instead of the VCO circuit 2 of FIG. 1 in comparison with the PLL circuit 1 according to the first embodiment shown in FIG. Is different.
- the VCO circuit 2C is different from the VCO circuit 2 of FIG. 1 in that a temperature detection circuit 4C is provided instead of the temperature detection circuit 4 of FIG.
- the PLL circuit 1C is the same as the PLL circuit 1 according to the first embodiment shown in FIG. 1 in the other points, and the detailed description of the components given the same reference numerals is omitted.
- FIG. 9 is a circuit diagram showing a detailed configuration of temperature detection circuit 4 C and voltage generation circuit 5.
- a temperature detection circuit 4C is different from the temperature detection circuit 4 of the PLL circuit 1 according to the first embodiment shown in FIG. 2 in the resistance R3 connected between the resistance R2 and the ground potential.
- it further comprises a switch SW5 controlled on and off by the output signal of the comparator 15 and connected in parallel to the resistor R3.
- the temperature detection circuit 4 C is controlled by the output signal from the comparator 15, and the value of the resistor connected to the current source 14 by the switch SW 5 is the resistance value of the resistor R 2 and the resistor R 2. It switches with the sum of resistance value of resistance and resistance value of resistance R3.
- the reference voltage on the current source 14 side can be switched by the output signal from the comparator 15, and the same operation as that of the hysteresis comparator becomes possible. Since a lockup time of several milliseconds or less is generally required for channel selection, the resistance value of resistor R3 should be set to have a hysteresis width that is equal to or greater than the temperature fluctuation range within this time.
- the temperature detection circuit 4C has hysteresis characteristics.
- the output voltage of the voltage generation circuit 5 changes during execution of the channel selection process.
- the output voltage of the voltage generation circuit 5 is coarsely adjusted when the switch SW3 in FIG. 8 selects the output voltage of the voltage generation circuit 5 Can be held constant. Also, since the resistance value is switched by the switch SW5! /, Only the current consumption does not increase.
- the voltage generation circuit can be used during coarse adjustment of the oscillation frequency without increasing the current consumption.
- the output voltage of 5 can be held constant.
- the temperature detection circuit 4C has the circuit configuration of FIG. 9 as an example of the configuration for realizing the hysteresis characteristic, but the present invention is not limited to this configuration, and the other configurations are not limited. It may be a configuration. Further, although the output voltage of the voltage generation circuit 5 is held constant by the hysteresis characteristics, the output logic of the temperature detection circuit 4C may be held using a logic circuit or the like.
- each PLL circuit 1, 1A, IB, 1C When a radio apparatus using each PLL circuit 1, 1A, IB, 1C according to the first to fourth embodiments is used as a tuner or the like, broadcasts in a wide frequency range can be received and good. High-quality video and audio signals can be reproduced by the proper phase noise characteristics.
- the first control voltage for rough adjustment corresponding to the detected temperature is detected. Since the temperature detection means for generating and outputting pressure is provided, the temperature margin of the oscillation frequency can be reduced, and a wide oscillation frequency range can be obtained without deteriorating the phase noise.
- the voltage controlled oscillation circuit according to the present invention and the wireless communication apparatus provided with the same can be used, for example, in a communication system or the like.
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
Abstract
Description
Claims
Priority Applications (3)
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CN2007800100455A CN101405941B (zh) | 2006-03-23 | 2007-03-23 | 电压控制振荡电路 |
JP2008506346A JP4542598B2 (ja) | 2006-03-23 | 2007-03-23 | 電圧制御発振回路 |
US12/294,177 US7982551B2 (en) | 2006-03-23 | 2007-03-23 | Voltage controlled oscillator having temperature detecting circuit |
Applications Claiming Priority (2)
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JP2006080292 | 2006-03-23 | ||
JP2006-080292 | 2006-03-23 |
Publications (1)
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WO2007108534A1 true WO2007108534A1 (ja) | 2007-09-27 |
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PCT/JP2007/056025 WO2007108534A1 (ja) | 2006-03-23 | 2007-03-23 | 電圧制御発振回路 |
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US (1) | US7982551B2 (ja) |
JP (1) | JP4542598B2 (ja) |
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WO (1) | WO2007108534A1 (ja) |
Cited By (1)
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WO2010104891A1 (en) * | 2009-03-09 | 2010-09-16 | Qualcomm Incorporated | Vco tuning with temperature compensation |
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US20110260761A1 (en) * | 2008-10-17 | 2011-10-27 | Freescale Semiconductor, Inc. | Temperature compensation in a phase-locked loop |
KR101541706B1 (ko) * | 2009-01-19 | 2015-08-05 | 삼성전자주식회사 | 온도 감지 발진 회로 및 이를 포함하는 반도체 메모리 장치 |
US8140040B1 (en) * | 2009-09-11 | 2012-03-20 | Qualcomm Atheros, Inc | Method and apparatus for a temperature compensated phase locked loop supporting a continuous stream receiver in an integrated circuit |
CN102118160B (zh) * | 2009-12-30 | 2013-10-23 | 意法半导体研发(深圳)有限公司 | 产生时钟信号的电路和方法 |
JP2011155489A (ja) * | 2010-01-27 | 2011-08-11 | Toshiba Corp | 半導体集積回路装置および発振周波数較正方法 |
US8248167B2 (en) * | 2010-06-28 | 2012-08-21 | Mstar Semiconductor, Inc. | VCO frequency temperature compensation system for PLLs |
TWI408526B (zh) * | 2010-11-19 | 2013-09-11 | Richtek Technology Corp | 具自動溫度補償之多段式電壓調節電路及方法 |
US8674772B2 (en) * | 2011-04-01 | 2014-03-18 | Mediatek Inc. | Oscillating signal generator utilized in phase-locked loop and method for controlling the oscillating signal generator |
US20120326795A1 (en) * | 2011-06-27 | 2012-12-27 | Broadcom Corporation | Vco calibration scheme |
US9004756B2 (en) | 2012-04-10 | 2015-04-14 | Freescale Semiconductor, Inc. | Temperature sensor |
JP5306512B1 (ja) * | 2012-04-27 | 2013-10-02 | ラピスセミコンダクタ株式会社 | 半導体装置、計測機器、及び補正方法 |
US9344094B2 (en) * | 2013-03-15 | 2016-05-17 | Intel Corporation | Temperature compensated PLL calibration |
US9407199B2 (en) * | 2014-08-27 | 2016-08-02 | Freescale Semiconductor, Inc. | Integrated circuit comprising a frequency dependent circuit, wireless device and method of adjusting a frequency |
US9515666B2 (en) | 2014-08-27 | 2016-12-06 | Freescale Semiconductor, Inc. | Method for re-centering a VCO, integrated circuit and wireless device |
CN106130544B (zh) * | 2016-06-15 | 2021-10-29 | 上海兆芯集成电路有限公司 | 自动频带校准方法与系统 |
EP3340467B1 (en) * | 2016-12-22 | 2022-10-05 | NXP USA, Inc. | Digitally controlled oscillator with temperature compensation |
CN107356348B (zh) * | 2017-07-20 | 2019-07-05 | 京东方科技集团股份有限公司 | 一种温度传感器及其温度检测方法 |
CN111756371A (zh) * | 2020-07-03 | 2020-10-09 | 上海奥令科电子科技有限公司 | 温度补偿方法和辅助电路、压控振荡装置 |
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- 2007-03-23 CN CN2007800100455A patent/CN101405941B/zh not_active Expired - Fee Related
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Also Published As
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JPWO2007108534A1 (ja) | 2009-08-06 |
CN101405941A (zh) | 2009-04-08 |
US7982551B2 (en) | 2011-07-19 |
US20090231044A1 (en) | 2009-09-17 |
CN101405941B (zh) | 2011-06-22 |
JP4542598B2 (ja) | 2010-09-15 |
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