WO2007102335A1 - Convertisseur a-n du type à comparaison séquentielle, procédé de fabrication d'un dispositif à circuits intégrés à semi-conducteurs et procédé de fabrication d'un dispositif à circuits intégrés à semi-conducteurs - Google Patents

Convertisseur a-n du type à comparaison séquentielle, procédé de fabrication d'un dispositif à circuits intégrés à semi-conducteurs et procédé de fabrication d'un dispositif à circuits intégrés à semi-conducteurs Download PDF

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Publication number
WO2007102335A1
WO2007102335A1 PCT/JP2007/053584 JP2007053584W WO2007102335A1 WO 2007102335 A1 WO2007102335 A1 WO 2007102335A1 JP 2007053584 W JP2007053584 W JP 2007053584W WO 2007102335 A1 WO2007102335 A1 WO 2007102335A1
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Prior art keywords
successive approximation
converter
conversion
semiconductor integrated
integrated circuit
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PCT/JP2007/053584
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English (en)
Japanese (ja)
Inventor
Masayoshi Igarashi
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Matsushita Electric Industrial Co., Ltd.
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Publication of WO2007102335A1 publication Critical patent/WO2007102335A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/004—Reconfigurable analogue/digital or digital/analogue converters
    • H03M1/007—Reconfigurable analogue/digital or digital/analogue converters among different resolutions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/80—Simultaneous conversion using weighted impedances
    • H03M1/802—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices
    • H03M1/804—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices with charge redistribution

Definitions

  • the present invention relates to a successive approximation AD converter and a method for manufacturing and designing a semiconductor integrated circuit device incorporating the same, and in particular, an AD converter capable of high-speed operation and high conversion accuracy.
  • ⁇ For products that can be easily created separately from AD converters.
  • Figure 4 (a) shows an example of a 6-bit successive approximation AD converter.
  • reference numeral 700 denotes an analog input, which is a signal converted into a digital signal by the successive approximation AD converter.
  • [0004] 710 is a digital output, and the signal obtained by digitizing the analog input 700 is the most significant bit (hereinafter referred to as MSB) to the least significant bit (hereinafter referred to as LSB). Up to 1 bit is output sequentially in this order.
  • Reference numeral 720 denotes a capacitance group, which is composed of capacitive elements 721 to 726. Each of these capacitative elements 721 to 726 has one node connected in common, and the capacities of the capacitative elements 721 to 726 are 16C, 8C, 4C, 2C, and 1C, respectively, where the unit capacitance is 1C. , 1C.
  • the capacitive element 721 corresponds to the most significant bit (MSB) after digital conversion
  • the capacitive element 726 corresponds to the least significant bit (LSB).
  • Reference numeral 730 denotes a switch group, which includes switches 731 to 736.
  • the switch 731 also has three single-pole single-throw switches 731a, 731 ⁇ , and 731 repulsion, and one node of these three switches 731a, 731 ⁇ , and 731 ⁇ is connected to the other node of the capacitor 721 in common.
  • Single input switch 731a analog input to the other node 700 power Single pole single throw switch 73
  • the other node of lp is positive reference potential (VDD) 740 power Single pole single throw switch 731 ⁇ is negative to the other node Reference potential (GND) 741 is connected to each other.
  • VDD positive reference potential
  • GND node Reference potential
  • Each of the switches 732 to 736 has the same configuration as that of the switch 731, and one of the three single-pole single-throw switches connected in common is connected to the other node of the capacitive elements 722 to 726.
  • Reference numerals 740 and 741 are a positive reference potential generating circuit and a negative reference potential generating circuit, which output a positive reference potential (VDD) and a negative reference potential (GND).
  • Reference potential generator 750 is a reference potential having a value of (VDD—GND) X (1Z2).
  • 760 is a switch for short-circuiting between two inputs of a comparator 770, which will be described later. When the output 710 is reset, the switch 760 is turned ON.
  • Reference numeral 770 denotes a comparator, which generates a potential of a node (hereinafter also referred to as a compare line CL) of the capacitor elements 721 to 726 constituting the capacitor group 720 and a reference potential generation circuit 750. Compared with the reference potential, a binary signal of “1” or “0” is output as output value 710 depending on the magnitude.
  • Reference numeral 780 denotes a control circuit that controls the switching of the switch group 730 by generating the initialization signal 781, the sample signal 782, and the redistribution comparison signal 783, and sequentially compares the analog input 700 and the reference potential 750. Run the action.
  • [0011] 792 is an END signal generator, which generates an END signal 795 when the successive approximation is completed up to LSB.
  • Reference numeral 793 denotes a register.
  • the generated END signal 795 is used as a flag, and the MSB force output from the comparator 770 stores the successive comparison result data 794 up to the LSB.
  • FIG. 4B is a timing chart of the control signals 781 to 783 until the analog input 700 is converted into a 6-bit digital signal. This cycle is represented by Cycle7.
  • the time required for Cycle 7 is equal to the total time required for each cycle T70 and T77.
  • Fig. 4 (c) shows the state of the switch that is turned on and off at the timing shown in Fig. 4 (b).
  • “ ⁇ ” indicates that the corresponding switch is simply on.
  • “ ⁇ ” is connected to this switch when the corresponding switch is turned on. It shows that the charge stored in the capacitive element is compared with the total charge stored in the capacitor group 720.
  • the single-pole single-throw switches 731a to 736a are all turned off and charged until just before that, the electric charge is held (held), and the hold is completed.
  • only the single-pole single-throw switch element 73 lp is closed (turned on), and the polarity of the potential connected to the capacitor element 721 is switched from negative (GND) to positive (VDD) and stored in the capacitance group 720 during sampling.
  • the total amount of charge stored is compared with the amount of charge stored in the capacitor 721
  • the comparator 770 obtains “1” as the output value 710 for the MSB.
  • the output values 710 of the capacitive elements 723 to 726 are sequentially obtained up to the LSB by performing comparison in the same manner as the capacitive element 721 in the cycles of T72 to T77.
  • V -V (in) + V (ref).
  • the comparator 770 compares the potential V of the compare line CL with the value of the reference potential V (ref).
  • V ⁇ V (ref) that is, V (in) + (lZ2) V (+) ⁇ 0
  • the comparator 770 will set "1" as the MSB.
  • comparator 770 sets MSB to "0"
  • V -V (in) + V (ref) + (1/2) V (+) + (1/4) V (+) (2)
  • V -V (in) + V (ref) + (1/4) V (+) (3)
  • the comparator 770 compares the potential V of the compare line CL with the value of the reference potential V (ref) to determine the value of the one bit lower than the MSB. Continue until you get S.
  • the conversion time (Cycle 7) of the successive approximation type AD conversion ⁇ is the sum of the sampling time (T71) and the successive approximation time (T72 + T73 + T74 + T75 + T76 + T77). It is determined.
  • Patent Document 1 Japanese Patent Laid-Open No. 2001-267925 (Page 3-4, Fig. 1)
  • AD converter there are various types of requirements for the AD converter. For example, there are cases where high-precision AD conversion is required and high-speed AD conversion is required.
  • AD converters that individually adjust the capacitance values of the capacitance groups to optimum values according to the required conversion accuracy and conversion speed are individually configured. Therefore, there is a problem that the cost of the semiconductor integrated circuit device is increased.
  • the present invention has been made in order to solve the above-described problems of the prior art, and in order to have various conversion accuracy and conversion speed according to the request of the AD converter customer, It is an object of the present invention to provide a successive approximation AD converter capable of easily creating a comparative AD converter, a semiconductor integrated circuit device incorporating the AD converter, a method for manufacturing the semiconductor integrated circuit device, and a design method therefor. As! Speak.
  • the successive approximation type AD converter includes an input means for inputting an analog signal, the analog signal input from the input means, respectively, A plurality of selection means for selecting any one of the reference signal or the second reference signal, one node connected to each of the plurality of selection means, and the other node connected to each other, A plurality of capacitance means having a predetermined capacitance value, a comparison means for comparing a potential of nodes commonly connected to the plurality of capacitance means and a reference potential for successive comparison and outputting a comparison value as a digital signal And a conversion speed variable means for making the conversion speed of AD conversion variable according to the required conversion accuracy of AD conversion.
  • the successive approximation AD converter according to claim 2 of the present invention provides the successive approximation according to claim 1.
  • the conversion speed varying means varies the conversion speed of AD conversion by setting the capacitance values of the plurality of capacitance means.
  • the successive approximation type AD converter according to claim 3 of the present invention is the successive approximation type AD converter according to claim 2, wherein the setting of the capacitance value by the conversion speed variable means is the plurality of Each of the capacitive means is divided into two or more child capacitances connected in parallel to each other, and is performed by switching the capacitance selection means connected to each of the child capacitances in series with each other. .
  • a semiconductor integrated circuit device includes the successive approximation AD converter according to any one of claims 1 to 3.
  • the successive approximation AD converter includes an input means for inputting an analog signal, the analog signal input from the input means, or the first reference signal, or A plurality of selection means for selecting any one of the second reference signals, one node connected to each of the plurality of selection means, and the other node connected to each other, each having a predetermined capacity
  • a plurality of capacitance means having a value; a comparison means for comparing a potential of nodes commonly connected to the plurality of capacitance means with a reference potential for successive comparison; and outputting a comparison value as a digital signal; and the comparison means
  • Output bit length setting means for setting the bit length of the digital signal of N bits (N is an integer of 2 or more) to be output to the N bits or less according to the required AD conversion accuracy. is there.
  • the successive approximation type AD converter according to claim 6 of the present invention is the successive approximation type AD converter according to claim 5, wherein the output bit length setting means is one of the plurality of capacitance means. The output bit length is set depending on whether or not the section is electrically disconnected.
  • the successive approximation type AD converter according to claim 7 of the present invention is the successive approximation type AD converter according to claim 6, wherein the output bit length setting means is output from the comparison means.
  • the bit length of the digital signal can be set to any value up to N bits.
  • a semiconductor integrated circuit device includes the successive approximation AD converter according to any one of claims 5 to 7.
  • the method for manufacturing a semiconductor integrated circuit device according to claim 9 of the present invention is not claimed in claim 1.
  • a step of preparing masks having different partial patterns depending on the AD conversion speed that the successive approximation AD converter should have, and the AD conversion speed that the successive approximation AD converter should have A step of selecting a mask having a pattern corresponding to the conversion speed, and a step of transferring the circuit pattern of the successive approximation AD converter to a semiconductor substrate using the mask group including the selected mask. is there.
  • the method for manufacturing a semiconductor integrated circuit device according to claim 10 of the present invention is the method for manufacturing a semiconductor integrated circuit device according to claim 9, wherein a pattern of a part of the mask is the sequential pattern.
  • This is a circuit pattern of a circuit corresponding to a part of a circuit constituting the conversion speed variable means of the comparative AD converter.
  • the partial pattern of the mask has the successive approximation type AD. This is a circuit pattern corresponding to a part of the circuit constituting the output bit length setting means of the converter.
  • a design method of a semiconductor integrated circuit device is the method of designing the successive approximation type AD conversion according to any one of claims 1 to 3 and 5, or 7 to 7.
  • the masks in the mask group used at the time of manufacturing the semiconductor integrated circuit device are partially connected to each other according to the AD conversion speed that the successive approximation type AD converter should have.
  • Including a step of preparing a mask having a different pattern, a step of selecting a mask having a pattern corresponding to the AD conversion speed according to an AD conversion speed that the successive approximation AD converter should have, and the selected mask A step of transferring the circuit pattern of the successive approximation type AD converter to the semiconductor substrate using the mask group, so that the manufacturing method of the semiconductor integrated circuit device can be executed. Circuit To design, it is intended.
  • a semiconductor integrated circuit device design method according to claim 13 of the present invention is the same as the semiconductor integrated circuit device design method according to claim 12, wherein a pattern of a part of the mask is obtained. Is a circuit pattern of a circuit corresponding to a part of the circuit constituting the conversion speed variable means of the successive approximation AD converter.
  • the pattern of a part of the mask is the pattern of the design method of the semiconductor integrated circuit device according to claim 12. This is a circuit pattern of a circuit corresponding to a part of the circuit constituting the output bit length setting means of the successive approximation AD converter.
  • the present invention it is possible to obtain an optimal AD conversion time or AD conversion accuracy according to the required accuracy with one type of AD converter configuration, for example, two types or more conventionally.
  • This system can be realized by having only one type of AD conversion, reducing the cost of successive approximation AD converters or semiconductor integrated circuit devices with built-in successive approximation AD converters. There is a big effect in doing.
  • the present invention it is possible to easily create the AD variation by selecting a mask at the time of manufacturing the semiconductor integrated circuit device in accordance with the specification of the conversion speed that the AD converter should have. There is an effect that a manufacturing method of a semiconductor integrated circuit device that can be realized is obtained.
  • the present invention by designing the AD converter circuit so that the above-described manufacturing method can be realized, the masks used in manufacturing the semiconductor integrated circuit device are partly connected to each other.
  • the semiconductor integrated circuit device design method can be obtained, which can realize the separate creation of the AD converter with almost no increase in cost.
  • FIG. 1 (a) is a diagram showing a configuration of a successive approximation AD converter according to Embodiment 1 of the present invention.
  • FIG. 1 (b) is a diagram showing an operation mode of the successive approximation AD converter according to the first embodiment of the present invention.
  • FIG. 2 (a) is a diagram showing a configuration of a successive approximation AD converter according to Embodiment 2 of the present invention.
  • FIG. 2 (b) is a diagram showing an operation mode of the successive approximation AD converter according to the second embodiment of the present invention.
  • FIG. 3 (a) is a diagram showing a configuration when the successive approximation AD converter according to the third embodiment of the present invention is manufactured at a high conversion speed.
  • FIG. 3 (b) is a diagram showing a configuration when the successive approximation AD converter according to Embodiment 3 of the present invention is manufactured with good conversion accuracy.
  • FIG. 3 (c) is a diagram showing a configuration when the successive approximation AD conversion according to Embodiment 3 of the present invention is manufactured so as to have a high conversion speed.
  • FIG. 3 (d) is a diagram showing a configuration when the successive approximation AD converter according to the third embodiment of the present invention is manufactured with good conversion accuracy.
  • FIG. 3 (e) is a flowchart showing a manufacturing process of a semiconductor integrated circuit device having a successive approximation AD converter according to Embodiment 3 of the present invention.
  • FIG. 4 (a) is a diagram showing a configuration of a conventional successive approximation AD converter.
  • FIG. 4 (b) is a diagram showing an operation mode of a conventional successive approximation AD converter.
  • FIG. 4 (c) is a diagram showing switch switching states in each operation mode of the conventional successive approximation AD converter.
  • Negative side reference potential generator 150 250, 350, 450, 550, 650 Reference potential generator
  • FIG. 1 is a diagram for explaining a successive approximation AD converter according to Embodiment 1 of the present invention.
  • FIG. 1 (a) shows its circuit configuration
  • FIG. 1 (b) shows its control signal. It is an explanatory diagram, and shows an example of a successive approximation AD converter with a resolution of 6 bits.
  • the configuration of the first embodiment is the same as that described in FIG. 4 except for the conversion mode signal 184 output from the control circuit 180 and the configuration of the capacitor group 120.
  • the capacitance values of the individual capacitive elements of the capacitive group constituting the successive approximation AD converter are fixed, and therefore the sampling time is constant.
  • the capacitance values of the capacitive elements (capacitance means;) 121, 122, 123, 124, 125, 126 can be varied from the capacitance variable switches 121s, 122s, 123s, 124s, 125s, 126s.
  • the sampling time can be varied.
  • the variable capacity switches 121 s, 122 s, 123 s, 124 s, 125 s, and 126 s are ON / OFF controlled by a conversion mode signal 184.
  • reference numeral 100 denotes an analog input (input means), which is a signal converted into a digital signal by the successive approximation AD converter.
  • [0056] 110 is a digital output, and the signal obtained by digitizing the analog input 100 has an MSB power of L Bits are sequentially output up to SB in this order.
  • Reference numeral 120 denotes a capacitor group, which includes capacitor elements 121 to 126. One node of these capacitive elements 121 to 126 is connected in common to each other, and each of these capacitive elements 121 to 126 is divided in parallel. In this parallel division, for example, one capacitor element is divided into a plurality of child capacitors (child capacitors 121a and 121b in the example of the capacitor element 121), and these child capacitors are connected in parallel to each other, thereby being equivalent to the original capacitor element. It is configured to be a simple capacitive element.
  • each of the child capacitors 121a and 121b of the capacitor 121 (capacitance value 16C) is 8C
  • each of the child capacitors 122a and 122b of the capacitor 122 (capacitance value 8C) is respectively 4C
  • each of the sub-capacitors 123a and 123b of the capacitative element 123 (capacitance value 4C) is 2C
  • each of the sub-capacitors 124a and 124b of the capacitative element 124 (capacitance value 2C) is 1C
  • each of the capacitative element 125 (capacitance value 1C)
  • Each of the child capacitors 125a and 125b has a capacitance value of 0.5C
  • each of the child capacitors 126a and 126b of the capacitor 126 (capacitance value 1C) also has a capacitance value of 0.5C.
  • variable capacity switches 121s, 122s, 123s, 124s, 125s, and 126s are directly connected to the sub-capacities 121j, 122b, 123b, 124b, 125b, and 126b, respectively, and are all simultaneously It is configured to turn ON or OFF.
  • the capacity variable switches 121s, 122s, 123s, 124s, 125s and 126s are all ON, the capacity variable switches 121s, 122s are completely equivalent to the capacity values of the capacity group shown in FIG. , 123s, 124s, 125s, 126s forces S
  • the capacitance value is 1Z2 compared to the capacitance value of the capacitance group in FIG. 4 (a).
  • variable capacitance switches 121s, 122s, 123s, 124s, 125s, and 126s are controlled to be in the ON state by the conversion mode signal 184 (conversion mode 1), the operation is as shown in FIG. This is the same as the operation of the conventional technique shown in FIG.
  • the capacitance values of the capacitance group 120 are 8C, 4C, 2C, 1 C, 0.5 C, 0.5 C.
  • the capacitive element 121 having the largest capacitance value corresponds to the MSB after digital conversion
  • the capacitive element 126 having the smallest capacitance value corresponds to the LSB.
  • Reference numeral 130 denotes a switch group, which includes switches 131 to 136.
  • Switch 131 consists of three single-pole single-throw switches 131a, 131 ⁇ , and 131 ⁇ force, and one of these nodes has capacity 121.
  • the other node of the single-pole single-throw switch 13 la is connected to the analog input 100, and the other node of the single-pole single-throw switch 13 lp is connected to the positive reference potential (VDD) 140.
  • the other node of the single throw switch 131 ⁇ is connected to the negative reference potential (GND) 141, respectively.
  • the other switches 132 to 136 have the same configuration as that of the switch 131, and one node commonly connected to each other is connected to the other node of the capacitive elements 122 to 126, respectively.
  • Reference numerals 140 and 141 denote a positive reference potential generation circuit and a negative reference potential generation circuit, which output a potential that serves as a positive reference (VDD) and a potential that serves as a negative reference (GND), respectively.
  • Reference numeral 150 denotes a reference potential generating circuit, which has a value of (VDD—GND) X (1Z2).
  • [0062] 160 is a switch for short-circuiting between two inputs of a comparator 170, which will be described later. When the output 110 is reset, the switch is turned on.
  • Reference numeral 170 denotes a comparator, which compares the potential of the commonly connected nodes of the capacitive elements 121 to 126 constituting the capacitive group 120 with the reference potential generated by the reference potential generation circuit 150, and “1” Alternatively, a binary signal of “0” is output as output value 110.
  • Reference numeral 180 denotes a control circuit, which includes an initialization signal 181, a sample signal 182, and a redistribution comparison signal 18.
  • Reference numeral 190 denotes conversion speed variable means, which changes the conversion speed of this AD conversion by changing the capacitance value of the capacitor group 120 under the control of the control circuit 180.
  • Reference numeral 192 denotes an END signal generator.
  • the END signal is obtained when the successive approximation is completed up to LSB.
  • Reference numeral 193 denotes a register, and the generated END signal 195 is used as a flag, and the MSB force output from the comparator 170 also stores the successive comparison result data 194 up to the LSB.
  • FIG. 1B is a timing chart of the control signals 181 to 183 until the analog input 100 is converted into a 6-bit digital signal. This cycle is expressed as Cyclel.
  • the required time for Cyclel is also the total power of the required time for each cycle from T10 to T17.
  • the single-pole single-throw switches 13la to 136a are all turned off, so that the charge that has been charged up to that point is held. Only the single-pole single-throw switch 131p is closed (turned on), the polarity of the potential connected to the capacitor 121 is switched from negative (GND) to positive (VDD), and the charge stored in the capacitor group 120 during sampling The total amount and the amount of charge stored in the capacitor 121 are compared. For example,
  • the output values 110 are sequentially obtained up to LSB in the same manner as the capacitive element 121 in the cycles of T12 to T17 for the capacitive elements 122 to 126, respectively.
  • the capacitance value of each capacitive element is the same as the original value, AD conversion is performed at a normal conversion speed (conversion mode 1), and each capacitive element
  • the same AD converter ⁇ has two modes: a mode that performs high-speed AD conversion (conversion mode 2) by halving the capacitance value of the capacitor. By turning the capacitance variable switch on or off, these two modes Since the AD converter is configured so that it can be used by switching between any of the modes, it is possible to reduce the amount of AD conversion that was previously required to one.
  • the parallel splitting capacities are configured so that the respective capacities are 1: 1, and the splitting ratio of the capacities is limited to 1: 1. It is not a thing. It is also possible to easily realize three or more operation modes by dividing each capacitive element into three or more child capacitors in parallel with each other.
  • FIG. 2 is a diagram for explaining a successive approximation AD converter according to Embodiment 2 of the present invention.
  • FIG. 2 (a) shows its circuit configuration
  • FIG. 2 (b) shows its control signal. It is an explanatory diagram, and shows a 6-bit successive approximation AD converter as an example.
  • the configuration of the second embodiment is the same as that described in FIG. 4 except that a conversion mode signal 284 output from the control circuit 280 and an upper bit conversion switch (output bit length variable switch) 291 are provided. It is.
  • the output bit length is constant because all the storage capacitors of the individual capacitive elements of the capacitive group constituting the successive approximation AD converter are valid, and therefore the sampling time is also reduced.
  • the output bit length setting means 290 for controlling the bit length of the AD converted digital data is mounted and the output bit length of the output bit length setting means 290 is fixed.
  • Length variable switch 291 is either ON state force or OFF state By switching to, whether to enable the higher-order bit of the successive approximation AD converter or not, and setting the switch 260 off time according to the sample signal 282, it is optimal for each state. The configuration is such that the sampling time can be obtained.
  • reference numeral 200 denotes an analog input, which is a signal that is converted into a digital signal by the successive approximation AD converter.
  • [0102] 210 is a digital output, and a signal obtained by digitizing the analog input 200 is sequentially output bit by bit from MSB to LSB in this order.
  • Reference numeral 220 denotes a capacitor group, which includes capacitor elements 221 to 226. Capacitance elements 221 to 226 are 16C, 8C, 4C, 2C, 1C, and 1C, respectively, where the unit capacity is 1C. Capacitance element 221 corresponds to the MSB after digital conversion, and capacitance element 226 corresponds to the LSB.
  • Reference numeral 230 denotes a switch group, which includes switches 231 to 236.
  • Switch 231 also has three single-pole single-throw switches 23 la, 231 ⁇ , and 231 ⁇ , and one of the single-pole single-throw switches 23 la, 231 ⁇ , and 231 ⁇ is connected to the other node of capacitive element 221.
  • the other node of the single-pole single-throw switch 2 31 a is connected to the analog input 200
  • the other node of the single-pole single-throw switch 23 lp is connected to the positive reference potential (VDD) 240
  • the other node of the single-pole single throw switch 23 In Are connected to the negative reference potential (GND) 241 respectively.
  • the other switches 232 to 236 have the same configuration as that of the switch 231, and one commonly connected node of the switches 232 to 236 is connected to the other node of the capacitor elements 222 to 226.
  • Reference numerals 240 and 241 denote a positive reference potential generation circuit and a negative reference potential generation circuit, which respectively output a positive reference potential (VDD) and a negative reference potential (GND).
  • 260 is a switch for short-circuiting between two inputs of the comparator 270, which will be described later.
  • the switch is turned ON when the output 210 is reset.
  • Reference numeral 270 denotes a comparator that compares the potential of the capacitor group 220 with the reference potential 250 and outputs a binary signal of “1” or “0” as an output value 210.
  • Reference numeral 280 denotes a control circuit, which controls the switching of the switch group 230 by generating an initialization signal 281, a sample signal 282, a redistribution comparison signal 283, and a conversion mode signal 284, and performs analog input and reference The successive comparison operation with the potential is executed.
  • Reference numeral 291 denotes an output bit length variable switch, which is a switch controlled by a conversion mode signal 284, and is one of the nodes of the capacitive elements 221 to 226 constituting the capacitive group 270 and one of the nodes of the capacitive element 221.
  • the other capacitive elements 222 to 226 are connected to and disconnected from one of the commonly connected nodes.
  • Reference numeral 290 denotes output bit length setting means, which also includes a control circuit 280 and an output bit length variable switch 291.
  • Reference numeral 292 denotes an END signal generator, which generates an END signal 295 when the successive comparison is completed up to the LSB.
  • Reference numeral 293 denotes a register, which uses the generated END signal 295 as a flag, and stores the MSB force output from the comparator 270 as well as the successive comparison result data 294 up to the LSB.
  • the conversion bit length is 6 bits, and the operation in this case is the same as the operation of the conventional example shown in FIG.
  • FIG. 2B is a timing diagram of the control signals 281 to 283 until the analog input 200 is converted into a 5-bit digital signal. This cycle is expressed as Cycle2, and the time required for Cycle2 is indicated by the total time required for each timing from T20 to T26.
  • switches 232n to 236n are all connected, and capacitive elements 222 to 226 are given a negative potential (GND).
  • the single-pole single-throw switches 271a to 236a are all turned off, so that the charge that has been charged up to that point is held.
  • the single-pole single-throw switch element 232p is closed, the polarity of the potential to which the capacitive element 222 is connected is switched to the negative (GND) force also to the positive (VDD), and the total amount of charge stored in the capacitive group 220 and the capacitive element during sampling
  • the amount of charge stored in 222 is compared. For example, when the total charge amount stored in the capacitor group 220> the charge amount stored in the capacitor element 222, “1” is obtained as the output value 210.
  • the output values 210 are sequentially obtained up to LSB in the same manner as the capacitive element 222 in the cycles of T22 to T26 for the capacitive elements 223 to 226, respectively.
  • the bit length of the AD conversion output is changed to a normal AD converter.
  • a mode in which AD conversion is performed at the same conversion speed as the normal conversion speed conversion mode 1
  • a mode in which the bit length of the AD conversion output is shorter than the normal one and high-speed AD conversion is performed conversion mode 2
  • the same AD converter, and by turning the output bit length variable switch on or off the AD converter is configured so that it can be switched to one of these two modes. This makes it possible to reduce the number of AD converters that were previously required to one.
  • FIGS. 3 (a) and 3 (b) show a successive approximation AD converter corresponding to the first embodiment, but the figure numbers are changed to the 300s and 400s.
  • 3 (c) and 3 (d) show the successive approximation AD converter corresponding to the second embodiment, but the figure numbers are changed to the 500s and 600s.
  • FIG. 3 (e) is a flowchart showing a method for manufacturing a semiconductor integrated circuit device according to the third embodiment.
  • the successive approximation type AD converter for customer A has the switches 32 Is, 322s, 323s, 324s, 325s, The 326s force-insulated configuration (shown in Fig.
  • the successive approximation AD converter for customer B are configured so that the switches 421s, 422s, 423s, 424s, 425s, and 426s are conductive (Fig. 3 (b)), this is a wiring pattern among the mask groups used to transfer the circuit pattern to a semiconductor wafer when manufacturing a semiconductor integrated circuit device having a successive approximation AD converter. This can be realized simply by selecting the wiring mask that transfers the pattern from the one corresponding to Fig. 3 (a) and the one corresponding to Fig. 3 (b)! In the case of such a configuration, the conversion mode signal is not necessary, and a sample signal optimized for each configuration may be generated in the control circuit.
  • the wiring mask has only a circuit pattern of a circuit corresponding to a part of the circuit constituting the conversion speed varying means between the one corresponding to FIG. 3 (a) and the one corresponding to FIG. 3 (b). It is only necessary to prepare different ones, that is, a circuit pattern in which the switch of the conversion speed variable means is insulated (corresponding to Fig. 3 (a)) and a circuit pattern in which the switch is conductive (corresponding to Fig. 3 (b)). . That is, as shown in Fig. 3 (e), first, in step SO, the circuit of the successive approximation AD converter shown in Fig. 1 (a) is designed. The circuit shown in Fig. 1 (a) can be switched between high-speed specifications and high-precision specifications.
  • the wiring mask pattern corresponding to Fig. 3 (a) is insulated at the locations (321s, 322s, 323s, 324s, 325 s, 326s) corresponding to the switches 121s, 122s, 123s, 124s, 125s, 126s.
  • the pattern of the wiring mask corresponding to Fig. 3 (b) is the position corresponding to the switch 12 Is, 122s, 123s, 124s, 125s, 126s (421s, 422s, 423s, 424s, 425s, 426s).
  • step S3 the pattern is transferred onto the semiconductor substrate using the mask obtained in step SI.
  • all circuit elements constituting the successive approximation AD converter other than the switches 121s, 122s, 123s, 124s, 125s, and 126s are formed on the semiconductor substrate.
  • a wiring mask is selected according to whether the successive approximation type AD conversion required by the customer is a high-speed specification or a high-precision specification. That is, if the customer requires high-speed specifications, the wiring mask corresponding to Fig. 3 (a) is selected. If the customer requests high-precision specifications, the wiring mask corresponding to Fig. 3 (b) is selected.
  • step S7 by using the wiring mask selected in step S5 or S6 and transferring the pattern, the circuit elements already created in step S3 are self-aligned.
  • the part corresponding to the conversion speed variable means in the first embodiment is used as a part to give a difference in requirements for each customer, but FIG. 3 (c) and FIG. 3 (d) Shown in As described above, the same effect can be obtained as the portion corresponding to the output bit length variable switch 291 in Embodiment 2 (590 in FIG. 3C and 690 in FIG. 3D).
  • the conversion speed varying means and the output bit length setting means may have configurations other than those shown in the first to third embodiments. The same effect can be obtained when applied to successive approximation AD converters other than those shown in Fig. 3, and AD converters of other conversion methods.
  • the successive approximation AD converter according to the present invention has two types or more of conversion modes, and one type of AD converter that has conventionally been required in plural. It can be configured. This is effective in reducing the area of a semiconductor integrated circuit device incorporating a successive approximation type AD converter.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

Afin de satisfaire à diverses précisions de conversion et vitesses de conversion requises pour un convertisseur A-N, il est nécessaire de configurer indépendamment un convertisseur A-N par mise en correspondance de la valeur de capacité du groupe de capacité avec une valeur optimale conformément à une précision de conversion et une vitesse de conversion nécessaires. Cette mesure augmente le coût d'un dispositif à circuits intégrés à semi-conducteurs comprenant un convertisseur A-N incorporé. Selon l'invention, en plus de la configuration du convertisseur A-N du type à comparaison séquentielle classique, des commutateurs (121 à 126) sont utilisés pour servir de moyens de modification de capacité pour modifier la vitesse de conversion conformément à la précision requise pour le convertisseur A-N du type à comparaison séquentielle. Ces moyens de modification de capacité permettent d'obtenir un convertisseur A-N à haute précision par augmentation d'une valeur de capacité d'un convertisseur A-N ou un convertisseur A-N à grande vitesse par réduction de la valeur de capacité. Il est ainsi possible d'optimiser le temps de conversion et la précision de conversion conformément à la précision requise dans le même convertisseur A-N.
PCT/JP2007/053584 2006-03-01 2007-02-27 Convertisseur a-n du type à comparaison séquentielle, procédé de fabrication d'un dispositif à circuits intégrés à semi-conducteurs et procédé de fabrication d'un dispositif à circuits intégrés à semi-conducteurs WO2007102335A1 (fr)

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JP2006055517 2006-03-01

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04290310A (ja) * 1991-03-19 1992-10-14 Fujitsu Ltd アナログ・デジタルコンバータ
JPH08288847A (ja) * 1995-04-12 1996-11-01 Sharp Corp Ａ／ｄ変換器
JP2001024509A (ja) * 1999-07-05 2001-01-26 Matsushita Electric Ind Co Ltd 自己補正方式電荷再配分逐次比較型ａｄ変換器

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04290310A (ja) * 1991-03-19 1992-10-14 Fujitsu Ltd アナログ・デジタルコンバータ
JPH08288847A (ja) * 1995-04-12 1996-11-01 Sharp Corp Ａ／ｄ変換器
JP2001024509A (ja) * 1999-07-05 2001-01-26 Matsushita Electric Ind Co Ltd 自己補正方式電荷再配分逐次比較型ａｄ変換器

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