WO2007076503A3 - Non-volatile memory operated on. the basis of a two-step bit-line precharge operation and a two-pass sensing operation - Google Patents
Non-volatile memory operated on. the basis of a two-step bit-line precharge operation and a two-pass sensing operation Download PDFInfo
- Publication number
- WO2007076503A3 WO2007076503A3 PCT/US2006/062605 US2006062605W WO2007076503A3 WO 2007076503 A3 WO2007076503 A3 WO 2007076503A3 US 2006062605 W US2006062605 W US 2006062605W WO 2007076503 A3 WO2007076503 A3 WO 2007076503A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- volatile memory
- sensing
- basis
- line precharge
- step bit
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
Abstract
Power-saving techniques are employed in sensing a group of non-volatile memory cells in parallel. In one aspect, coupling of the memory cells to their bit lines are delayed during a precharge operation in order to reduced the cells' currents working against the precharge. In another aspect, a power-consuming precharge period is minimized by preemptively starting the sensing in a multi-pass sensing operation. High current cells not detected as a result of the premature sensing will still be able to be detected in a subsequent pass.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP06848784A EP1966803A2 (en) | 2005-12-29 | 2006-12-26 | Non-volatile memory operated on the basis of a two-step bit-line precharge operation and a two-pass sensing operation |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/322,427 | 2005-12-29 | ||
US11/323,569 | 2005-12-29 | ||
US11/323,569 US7733704B2 (en) | 2005-12-29 | 2005-12-29 | Non-volatile memory with power-saving multi-pass sensing |
US11/322,427 US7447094B2 (en) | 2005-12-29 | 2005-12-29 | Method for power-saving multi-pass sensing in non-volatile memory |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2007076503A2 WO2007076503A2 (en) | 2007-07-05 |
WO2007076503A3 true WO2007076503A3 (en) | 2007-11-15 |
Family
ID=38191878
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2006/062605 WO2007076503A2 (en) | 2005-12-29 | 2006-12-26 | Non-volatile memory operated on. the basis of a two-step bit-line precharge operation and a two-pass sensing operation |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP1966803A2 (en) |
TW (1) | TWI315878B (en) |
WO (1) | WO2007076503A2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI425516B (en) * | 2009-05-08 | 2014-02-01 | Macronix Int Co Ltd | Memory apparatus and method for operating the same |
US8659963B2 (en) | 2012-01-05 | 2014-02-25 | International Business Machines Corporation | Enhanced power savings for memory arrays |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56143592A (en) * | 1980-04-09 | 1981-11-09 | Toshiba Corp | Semiconductor memory device |
US4852064A (en) * | 1987-06-27 | 1989-07-25 | Samsung Electronics Co., Ltd. | Precharge circuit for use in a semiconductor memory device |
US6144600A (en) * | 1998-03-16 | 2000-11-07 | Nec Corporation | Semiconductor memory device having first and second pre-charging circuits |
WO2004029984A2 (en) * | 2002-09-24 | 2004-04-08 | Sandisk Corporation | Non-volatile memory and its sensing method |
US20050057966A1 (en) * | 2003-09-16 | 2005-03-17 | Micron Technology, Inc. | Boosted substrate/tub programming for flash memories |
US20050078524A1 (en) * | 2003-10-09 | 2005-04-14 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device |
US20050162951A1 (en) * | 2004-01-23 | 2005-07-28 | Dudeck Dennis E. | Method and apparatus for reducing leakage current in a read only memory device using shortened precharge phase |
-
2006
- 2006-12-26 WO PCT/US2006/062605 patent/WO2007076503A2/en active Application Filing
- 2006-12-26 EP EP06848784A patent/EP1966803A2/en not_active Withdrawn
- 2006-12-29 TW TW95149909A patent/TWI315878B/en not_active IP Right Cessation
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56143592A (en) * | 1980-04-09 | 1981-11-09 | Toshiba Corp | Semiconductor memory device |
US4852064A (en) * | 1987-06-27 | 1989-07-25 | Samsung Electronics Co., Ltd. | Precharge circuit for use in a semiconductor memory device |
US6144600A (en) * | 1998-03-16 | 2000-11-07 | Nec Corporation | Semiconductor memory device having first and second pre-charging circuits |
WO2004029984A2 (en) * | 2002-09-24 | 2004-04-08 | Sandisk Corporation | Non-volatile memory and its sensing method |
US20050057966A1 (en) * | 2003-09-16 | 2005-03-17 | Micron Technology, Inc. | Boosted substrate/tub programming for flash memories |
US20050078524A1 (en) * | 2003-10-09 | 2005-04-14 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device |
US20050162951A1 (en) * | 2004-01-23 | 2005-07-28 | Dudeck Dennis E. | Method and apparatus for reducing leakage current in a read only memory device using shortened precharge phase |
Also Published As
Publication number | Publication date |
---|---|
TW200741736A (en) | 2007-11-01 |
EP1966803A2 (en) | 2008-09-10 |
WO2007076503A2 (en) | 2007-07-05 |
TWI315878B (en) | 2009-10-11 |
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