WO2007063474A2

WO2007063474A2 - Charge pump circuit and integrated circuit

Info

Publication number: WO2007063474A2
Application number: PCT/IB2006/054447
Authority: WO
Inventors: Mohamed Bouhamame; Jean-Robert Tourret; Luca Lococo
Original assignee: Nxp B.V.
Priority date: 2005-11-30
Filing date: 2006-11-27
Publication date: 2007-06-07
Also published as: WO2007063474A3; EP1958321A2; CN101317320A; JP2009517997A

Abstract

A charge pump circuit for increasing a circuit voltage, comprising: a DC-DC up-converter (14) having an array of capacitors arranged to charge-pump to a higher voltage than the circuit voltage, the DC-DC up-converter having an output lead (8) arranged to output the higher voltage, a DC-DC down-converter (30) connected to the output lead, the DC-DC down-converter having an array of capacitors and diodes arranged to down-pump the higher voltage, and an ESP (Electrostatic Discharge Protection) circuit comprising a series (42) of N series-connected diodes arranged to sink current from the output lead, wherein N is an integer larger than two, each diode having its anode permanently connected to the output lead and its cathode permanently connected to a reference potential, wherein the series includes the diodes of the DC-DC down-converter.

Description

DESCRIPTION

CHARGE PUMP CIRCUIT AND INTEGRATED CIRCUIT

FIELD OF THE INVENTION

The present invention relates to a charge pump circuit and an integrated circuit.

BACKGROUND OF THE INVENTION

Typically, a charge pump circuit for increasing a DC voltage circuit may include:

- a DC-DC up-converter having an array of capacitors arranged to charge-pump to a higher voltage than the circuit voltage, the DC-DC up- converter having an output lead arranged to output the higher voltage, and

- a DC-DC down-converter connected to the output lead, the DC-DC down-converter having an array of capacitors and diodes arranged to down- pump the higher voltage.

The DC-DC up-converter has also diodes that prevent current sinking from the output lead through the DC-DC up-converter.

Current sinking through the DC-DC down-converter is only possible when it is activated. The DC-DC down-converter can be activated only when the DC-DC up-converter is disabled.

The above circuit is therefore not resistant to electrostatic discharge on the output lead because current sinking to a reference potential through the DC-DC up or down-converter is not always possible.

An example of such a conventional charge pump circuit is described in the following article:

« A linear high voltage charge pump for MEMS applications in 0.18 μm CMOS technology » Manuel Innocent, Piet Wambacq,

Stephane Donnay, Willy Sansen, and Hugo De Man - IMEC, Kapeldreef 75, Leuven Belgium. Accordingly, it is a desire of the invention to provide an improved charge pump circuit.

SUMMARY OF THE INVENTION

The invention provides a charge pump circuit having an ESP (Electrostatic Discharge Protection) circuit comprising a series of l\l series- connected diodes arranged to sink current from the output lead, wherein N is an integer larger than two, each diode having its anode permanently connected to the output lead and its cathode permanently connected to a reference potential, wherein the series includes the diodes of the DC-DC down-converter.

The DC-DC down-converter increases the discharging speed of the output lead by dynamically pumping charge. This is of great interest when the output lead is connected to, for example, a capacitive load.

The above DC-DC up-converter is more resistant to electrostatic discharge on the output lead because it includes the ESP circuit.

Furthermore, the total-on-chip area of this charge pump circuit is decreased because diodes are common to both the DC-DC down-converter and the ESP circuit.

The embodiments of the above circuit may have one or several of the following features:

- the sum of every forward bias voltage of the series-connected diodes is larger than the higher voltage generated by the DC-DC up-converter,

- the DC-DC down-converter comprises several down-pumping stages connected in series between the output lead and the reference potential, each stage having only one diode and only one capacitor, - the number of diodes of the DC-DC down-converter used in the series of the ESP circuit is strictly smaller than N,

- the DC-DC up-converter is a Dickson charge pump circuit, and - the capacitors used in the DC-DC up or down-converters are metal-to-metal capacitors.

The above embodiments of the charge pump circuit present the following advantages: - having a total diode forward bias voltage which is larger than the higher voltage reduces or cancels the leakage current that could flow from the output lead to the reference potential,

- DC-DC down-converter stages having only one diode and one capacitor reduce the on-chip area needed to implement the charge pump circuit,

- having a number of diodes in the DC-DC down-converter smaller than N reduces the on-chip area needed to implement the pump charge circuit,

- using a Dickson charge pump circuit reduces the on-chip area needed to implement the pump charge circuit, and

- using metal-to-metal capacitors reduces the capacitor leakage current and greatly improves the performance of the DC-DC up or down-converter.

The invention also relates to an integrated circuit having the above charge pump circuit.

These and other aspects of the invention are apparent from and will be elucidated in the following description, drawings and claims.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic diagram of a portion of an integrated circuit having a charge pump circuit,

Figure 2A and 2B are time charts of clock signals used within the charge pump circuit of Figure 1 , and

Figure 3 is a flow chart of a method of operating the charge pump circuit of Figure 1. DETAILED DESCRIPTION

Figure 1 shows an integrated circuit 2. Functions or constructions well-known to a person of ordinary skill in the art will not be described in detail hereinafter. More precisely, Figure 1 shows a portion of the integrated circuit on- chip area in which a charge pump circuit 4 is implemented to increase a DC circuit voltage V_dd-

Circuit 4 has an input lead 6 receiving voltage V_dd and an output lead 8 which outputs a higher DC voltage V_Ouτ- Lead 8 is connected to an on-chip load 10. For example, load 10 is a capacitive load having a capacitor 12.

A DC-DC up-converter 14 is directly connected between leads 6 and 8 so as to charge-pump lead 8 to the higher voltage V_Ouτ-

For example, converter 14 is a Dickson charge pump converter. Such a converter is described in, for example, the following reference:

« On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique » J. F. Dickson - IEEE J. Solid-State Circuits, Vol. 11, No. 3, pp.374-378, June 1976.

Converter 14 has M charge pumping stages M₁ series connected between leads 6 and 8. For simplicity, Fig. 1 only shows stages M₁, M₂, M₃ and M_m.

Each stage M₁ has:

- one voltage input I₁,

- one voltage output O₁, and - one clock signal input Cl₁.

Input I₁ of first stage M₁ is directly connected to lead 6. The other inputs I₁ are directly connected to the output of the preceding stage M_1-1.

The output Om of last stage M_m is connected to lead 8 through a diode 20 having its cathode directly connected to lead 8. Clock inputs Cl₁ are connected to a clock signal generator 24 through a multiplexer 26. Generator 24 generates one clock signal Φ and one clock signal Φ .

Signals Φ and Φ have opposite phases, i.e. the signal Φ phase is shifted by 180° from the signal Φ phase.

Figures 2A and 2B illustrate signals Φ and Φ according to time. Clock inputs Cl₁ of stages M₁ having an odd index i are connected to signal Φ . Clock inputs Cl₁ of stages M₁ having an even index i are connected to signal Φ .

Each stage M₁ includes:

- only one diode D₁ having its anode connected to input I₁ and its cathode connected to output O₁, and

- only one capacitor C₁ connected between output O₁ and clock input Cl₁.

The capacity of each capacitor C₁ is smaller than, for example, 5pif. Here, capacity is equal to 1 pif. Each capacitor C₁ is a metal-to-metal capacitor. For example, the structure of capacitor C₁ is the one disclosed in Fig.2 of the following reference:

« Capacity limits and matching properties of integrated capacitors » Roberto Aparicio, and AIi Hajimiri, IEEE, vol.37, n °3, Mars 2002. Each diode D₁ has a forward bias voltage V_d which is, for example, equal to 0.7V. The forward bias voltage is the voltage drop due to the diode when the diode is conducting.

Circuit 4 has also a DC-DC down-converter 30 which is connected between lead 8 and a reference potential V_rΘf. Reference potential V_rΘf is, for example, ground.

Converter 30 has an array of capacitors and diodes arranged to down-pump voltage V_Ouτ-

Converter 30 has one input 32 directly connected to lead 8 and one output 34 connected to reference potential V_rΘf. Converter 30 has L down-pumping stages R₁ connected in series between input 32 and output 34. Each stage R₁ has:

- one voltage input l'i,

- one voltage output O',, and - one clock input Cl',.

Input l'i is directly connected to input 32 and output O', is directly connected to the anode of a diode 36. The cathode of diode 36 is directly connected to output 34. The other outputs O', are connected to the input l'_l+i of the next stage R₁₊₁. For simplicity, only stages R₁, R₂, Rι_-i and R_L are shown in Figure 1.

Input clock Cl', is connected to signal Φ if index i is odd and otherwise connected to signal Φ .

Each stage R₁ has: - only one diode D', having its anode connected to input T₁ and its cathode connected to output O',, and

- only one capacitor C₁ connected between output O', and clock input Cl¹,.

Diodes D', are identical to, for example, diodes D₁. Here, for the purpose of illustration, capacitor C₁ has a capacity which is smaller than that of capacitor C₁. For example, capacitor C₁ has a capacity which is at least twice smaller than the capacity of capacitor C₁. Here, the capacity of capacitor

Cr is equal to 0.5 pif. Having a smaller capacitor CV than capacitor C₁ reduces the on-chip area needed to implement circuit 4. Output 34 is connected to reference potential V_rΘf through a series 40 of K_diodes E₁. For simplicity, only diodes E₁, E₂, E₃, E_K--ι, E_κ are shown in

Figure 1.

The anode of each diode E₁ is connected to output 34 and each cathode is connected to reference potential V_rΘf. Diodes E₁ are identical to, for example, diodes D',.

As can be seen from the layout of circuit 4, lead 8 is directly and permanently connected to reference potential V_rΘf through a series 42 of N diodes, wherein N is equal to L+K+1. More precisely, series 42 of diodes includes: - the L series-connected diodes D',,

- diode 36, and

- the K series-connected diodes E₁. Series 42 of N. diodes form an ESP circuit. Diodes D', and diode 36 are common to both converter 30 and the ESP circuit.

The number N of diodes in the ESP circuit is chosen to comply with the following relation:

N.V_d > Vouτ (1 )

wherein:

-V_OUT is the voltage generated by converter 14, and - Vd is the forward bias voltage of diodes D',, 26 and E₁.

Consequently, there is no leak of current through the N. series- connected diodes as long as V_Ouτ remains smaller than N.V_d.

Multiplexer 26 is able to sequentially activate converters 14 and 30. More precisely, multiplexer 26 is able to connect signal Φ and Φ alternately to clock inputs Cl₁ and clock inputs Cl',.

For example, multiplexer 26 has two controllable interrupters 44 and 46 for connecting and disconnecting each input clock Cl₁ from signals Φ and Φ . Multiplexer 26 has also two controllable interrupters 48 and 50 which are able to connect and disconnect each input clock Cl', from clock signal Φ and Φ . Interrupters 44, 46, 48 and 50 are designed in such a way that, when interrupters 44 and 46 are closed, interrupters 48 and 50 are open, and vice- versa. The switching of interrupters 44, 46, 48 and 50 is controlled through a control input port 52.

The operation of circuit 4 will now be described with reference to Figure 3.

Initially, in step 60, controller 26 closes interrupters 44 and 46 and opens interrupters 48 and 50 to only activate converter 14 and disable converter 30. Subsequently, a charge pumping step 62 takes place. During step 62, converter 14 increases voltage V_dd to obtain voltage V_Ouτ- The operation of converter 14 is well-known and will not be described in detail.

If necessary for whatever reason, in step 64, multiplexer 26 is controlled through port 52 to open interrupters 44 and 46 and close interrupters 48 and 50. In step 64, converter 14 is therefore disabled and converter 30 is activated.

When activated, in step 66, converter 30 operates like converter 14 to down-pump voltage V_Ouτ- Step 66 will therefore not be described in detail. In step 66, current flows from load 10 to reference potential V_rΘf through diodes D',, diode 36 and diodes E₁. Activating converter 30 allows a quicker discharge of load 10 than if only diodes were used.

In parallel with steps 60 to 66, in step 70, voltage V_Ouτ becomes larger than N.V_d if there is an electrostatic discharge on lead 8. Thus, in step 70, diodes D', , diode 36 and diodes E₁ conduct. A current sinks through converter 30 and diode series 40. This rapidly decreases V_Ouτ and helps to protect circuit 4 against electrostatic discharge.

It should be noted that the ESP circuit works even if converter 30 is disabled because diodes automatically start to conduct once the voltage between their terminals becomes larger than voltage V_d. Thus, circuit 4 is always protected against electrostatic discharge in every situation.

Many other embodiments are possible. For example, the number L does not need to be equal to number M. Preferably, number L is smaller than number M in order to reduce the on-chip area needed to implement circuit 4. The number K of diodes E₁ may be as small as zero.

DC-DC up-converter 14 can be replaced by a DC-DC up-converter having a different structure. For example, a structure similar to that disclosed in Figure 3C of WO98/20401 may be used. Converter 14 can also be replaced by a DC-DC up-converter having the structure disclosed in the following article:

« Power efficient charge pump in deep submicron standard CMOS technology » Roberto Pelliconi, David Jezzi, Andrea Baroni, Marco Pasotti, Pier Luigi Rolandi - STMicroelectronics - Central R&D

Claims

1. A charge pump circuit for increasing a circuit voltage, comprising:

- a DC-DC up-converter (14) having an array of capacitors arranged to charge-pump to a higher voltage than the circuit voltage, the DC-DC up- converter having an output lead (8) arranged to output the higher voltage,

- a DC-DC down-converter (30) connected to the output lead, the DC- DC down-converter having an array of capacitors and diodes arranged to down-pump the higher voltage, and

- an ESP (Electrostatic Discharge Protection) circuit comprising a series (42) of J\l series-connected diodes arranged to sink current from the output lead, wherein N is an integer larger than two, each diode having its anode permanently connected to the output lead and its cathode permanently connected to a reference potential, wherein the series includes the diodes of the DC-DC down-converter.

2. The circuit according to claim 1 , wherein the sum of every forward bias voltage of the series-connected diodes is larger than the higher voltage generated by the DC-DC up-converter (14).

3. The circuit according to any one of the preceding claims, wherein the DC-DC down-converter (30) comprises several down-pumping stages (R₁) connected in series between the output lead and the reference potential, each stage having only one diode and only one capacitor.

4. The circuit according to any one of the preceding claims, wherein the number of diodes of the DC-DC down-converter (30) used in the series of the ESP circuit is strictly smaller than N.

5. The circuit according to any one of the preceding claims, wherein the DC-DC up-converter (14) is a Dickson charge pump circuit.

6. The circuit according to any one of the preceding claims, wherein the capacitors used in the DC-DC up or down-converters (14, 30) are metal- to-metal capacitors.

7. An integrated circuit having an on-chip charge pump circuit (4) according to any one of the preceding claims.