CN102035373B - DC boosting matrix circuit structure - Google Patents
DC boosting matrix circuit structure Download PDFInfo
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- CN102035373B CN102035373B CN201010564521.1A CN201010564521A CN102035373B CN 102035373 B CN102035373 B CN 102035373B CN 201010564521 A CN201010564521 A CN 201010564521A CN 102035373 B CN102035373 B CN 102035373B
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Abstract
Capacitance matrix DC-DC pressure build-up technique, belongs to power technique fields.In the boosting charge pump of many multiplication of voltages, the electric current being difficult to realize peace rank exports, and simultaneously when pump electric capacity is more, drive circuit is more complicated.The present invention proposes a kind of new capacitance matrix formula charge pump construction, is characterised in that: pump electric capacity can direct-coupling between input circuit and output loop, realize charging while uninterruptedly discharge; When the quantity of pump electric capacity increases, the drive circuit quantity of charge pump switches can not increase; Whole capacitance matrix only has two row switches, and often row switch has a common port.This charge pump can realize the high-power charge pump of many multiplication of voltages, and output ripple voltage is the 1/N of single file electric capacity ripple voltage simultaneously, and N represents capacitance matrix electric capacity line number.
Description
Technical field
The invention belongs to power technique fields.
Background technology
In the booster circuit that current requirements is larger, what generally adopt is the circuit that inductance or transformer are formed, because its structure is simple, cost is low and be widely used.But the booster circuit that inductance or transformer are formed, will consider the peak voltage problem of electromagnetic radiation and inductive nature during design, the working stress of switching device is larger.From Patent database searching to patent related to the present invention have: 200410081176.0,200810224477.2,200880120685.6,90104016.9,99114073.7,99227369.2.
Summary of the invention
The DC boosting matrix circuit be made up of electric capacity, diode, switch, circuit structure as shown in Figure 1: one end of out-put supply is connected to one end of the first row electric capacity, the other end of out-put supply is connected to the other end of last column electric capacity by diode; One end of input power is connected with last column capacitance respectively by first row switch, and the other end of input power is connected with first row electric capacity respectively by secondary series switch; With between two electric capacity adjacent in a line electric capacity with two diodes in parallels in the same way, and in two diodes one or two just public diode; Sequentially directly connect in the same way between same column capacitance.
Fig. 1 is the capacitance matrix circuit that 3 row 3 arrange, and the right is input voltage, and the left side is output voltage.Dotted line representation switch control line, section setting-out represents output voltage sample line.
Operation principle.If by the job order of monolithic processor controlled switch be:
S1, S4 connect, and S2, S3, S5, S6 disconnect; After the first row electric capacity C1, C2, C3 charging complete, disconnect S1, S4;
S2, S5 connect, and S1, S3, S4, S6 disconnect; After second row electric capacity C4, C5, C6 charging complete, disconnect S2, S5;
S3, S6 connect, and S1, S2, S4, S5 disconnect; After the third line electric capacity C7, C8, C9 charging complete, disconnect S3, S6.After this above-mentioned steps is repeated ...
In Fig. 1,3 electric capacity of every a line are connected by 4 diode combinations in the same way.Such as the first row electric capacity C1, C2, C3, be connected by four diode D1, D2, D3, D4 in the same way: the positive pole of C1, the positive pole of D1 are in parallel, and the negative pole of C1, the positive pole of D3 are in parallel; The positive pole of the positive pole of C2, the negative pole of D1, D2 is in parallel, and the positive pole of the negative pole of C2, the negative pole of D3, D4 is in parallel; The positive pole of C3, the negative pole of D2 are in parallel, and the negative pole of C3, the negative pole of D4 are in parallel.Meanwhile, diode D3, D4 are again second row electric capacity C4, C5, C6, form with four diode D3, D4, D5, D6 in the same way the public diode that like combinations is connected.Be connected to the not common end of switch S 1 after the positive pole of D1 is in parallel with the positive pole of electric capacity C1, after the negative pole of diode D4 and the negative pole parallel connection of electric capacity C3, be connected to the not common end of switch S 4.The common port of switch S 1 is connected on the Uin+ of input power Uin, the Uin-of the public termination input power Uin of switch S 4.So when switch S 1, S4 connect simultaneously, input power Uin charges to the first row electric capacity C1, C2, C3:
The charge circuit of C1 is: Uin+, S1, C1, D3, D4, S4, Uin-;
The charge circuit of C2 is: Uin+, S1, D1, C2, D4, S4, Uin-;
The charge circuit of C3 is: Uin+, S1, D1, D2, C3, S4, Uin-.
As from the foregoing, every electric capacity all have passed through two diodes and two switched charges, and namely every capacitor charging voltage is equal.And because diode combinations is connected between electric capacity in the same way, between adjacent two electric capacity, can not discharge loop be formed.Such as discharge loop will be formed between C2 and C1: C2 then will can be blocked discharge path by D1 to C1 electric discharge; C1 then will can be blocked discharge path by D3 to C2 electric discharge.Ignore the pressure drop of switch S 1, S4, if diode drop is UD, represent the voltage of the first row electric capacity with the voltage U c1 of C1.
Then Uc1=Uin-2*UD.
After S1, S4 disconnect, connect charge switch S2, S5 of the second row electric capacity, to second row electric capacity C4, C5, C6 charging:
C4 charge circuit is: Uin+, S2, C4, D5, D6, S5, Uin-;
C5 charge circuit is: Uin+, S2, D3, C5, D6, S5, Uin-;
C6 charge circuit is: Uin+, S2, D3, D4, C6, S5, Uin-.
The charge circuit of the second row every electric capacity still have passed through 2 diodes and 2 switches, and charging voltage is still equal; The voltage of the second row electric capacity is represented, then Uc4=Uin-2*UD with the voltage U c4 of C4.
After switch S 2, S4 disconnect, connect charge switch S3, S6 of the third line electric capacity, charge to electric capacity C7, C8, C9:
The charge circuit of C7 is: Uin+, S3, C7, D7, D8, S6, Uin-;
The charge circuit of C8 is: Uin+, S3, D5, C8, D8, S6, Uin-;
The charge circuit of C9 is: Uin+, S3, D5, D6, C9, S6, Uin-.
The charge circuit of the third line every electric capacity still have passed through 2 diodes and 2 switches, and charging voltage is still equal, represents the voltage of the third line electric capacity, then Uc7=Uin-2*UD with the voltage U c7 of C7.
After this, each element in matrix repeats above-mentioned steps under the control of single-chip microcomputer.From upper analysis, the voltage of every electric capacity in capacitance matrix is equal Uin-2*UD.In the capacitance matrix that M row N is capable, every capacitance voltage Uc=Uin-(M-1) * UD.As can be seen from Figure 1: Uout=Uc1+Uc4+Uc7, i.e. capacitance matrix Uout=3* (Uin-2*UD).
Stable state sequential chart is as Fig. 2.The control impuls that Cp provides for single-chip microcomputer, width is t1, and the cycle is tcp, is located at the trailing edge switch conduction of pulse, and rising edge switch cuts out, and the charging interval is the t2 in Fig. 2.Pulse duration t1 is Dead Time.Because when same power supply is simultaneously to two row capacitor chargings, the positive switch that there will be input power forms short circuit between negative switch.When such as connecting S1, S4, Uin charges to the first row electric capacity C1, C2, C3, connect S2, S5 again allows Uin charge to second row electric capacity C4, C5, C6 simultaneously, then because connect while S2, S4, power supply directly will define short circuit by Uin+, S2, D3, D4, S4, Uin-, so single power supply must set up Dead Time.In Fig. 2: Uc1, Uc4, Uc7 represent the voltage of the first row, the second row, the third line electric capacity respectively; S1S4, S2S5, S3S6 represent the drive waveforms of 3 groups of switches respectively; Uout is output voltage.
As can be known from Fig. 1, the discharge loop of every electric capacity all have passed through load resistance, and electric capacity is direct discharged in series.Formula according to waiting capacity series connection: the Reciprocals sums of each electric capacity " inverse of total capacity equal to connect " is known, total capacitance is less than single capacitance, the discharging current of capacitance matrix can be less than charging current, and the more discharging currents of line number will be less, output voltage also can rise get Geng Gao simultaneously.
As from the foregoing, if control the length that each takes turns the switched charge time, nature can the charging voltage of control capacitance change with sinusoidal rule, as long as this design just passable in the program of single-chip microcomputer.Sinusoidally to change and frequency is 100HZ if control output voltage, at output by inverter bridge circuit, allow export and just often change a sinusoidal half cycle oppositely, namely output voltage is sinusoidal wave.This waveform does not need other filtering or shaping circuit, because inherently exported by electric capacity, by can direct termination alternating current machine after inverter bridge, and impulse current when not having quasi sine inverter (square wave) dragging motor and voltage.
From output to matrix, every column capacitance is parallel discharge simultaneously again after directly series connection, reduces the internal resistance of capacitance matrix powering load, while charging, is not interrupted electric discharge.From input to matrix, often row electric capacity is that parallel connection is charged simultaneously, and each electric capacity of this row is again directly be connected in each row simultaneously.Namely, when giving a line capacitor charging, be simultaneously to each row charging of capacitance matrix.Except switching dead, any time all can have a line electric capacity to charge simultaneously.
It is soft start that this capacitance matrix starts nature, and during closedown, voltage declines continuously, does not impact load.
Accompanying drawing explanation
Fig. 1: the circuit structure diagram of capacitance matrix.
The sequential chart of Fig. 2: Fig. 1 circuit working.
Fig. 3: the sequential chart of two-supply circuit work.
Embodiment
Realize the 4 multiplication of voltage charge pumps that a pure direct current exports.As the sequential chart of the dual power supply of Fig. 3, the output waveform of capacitance matrix will be stablized many, because the charging interval of 1 power supply just in time can be used as the Dead Time of another power supply.Each rising edge switch motion of setting single-chip microcomputer pulse CP, a square-wave pulse cycle of single-chip microcomputer is t, and total cycle of capacitance matrix is T=4*t.It can thus be appreciated that often row capacitor charging t of capacitance matrix, electric discharge 3*t.Two power supplys are wheel current charges, have filled up deadband lower limit voltage, at the rising edge two row switch counteragent (namely at synchronization, a power supply disconnects, and another power supply is connected) simultaneously of each pulse.Uin1 is the charge power supply of the first row, the second row electric capacity, and Uin2 is the charge power supply of the third line, fourth line, the alternation that the switch of two power supplys is paired.When the switch S 1 of such as Uin1, S5 connect, the switch S 2 of Uin1, the switch S 3 of S6 and Uin2, S4, S7, S8 disconnect; When switch S 3, the S7 connection of Uin2, the switch S 4 of Uin2, the switch S 1 of S8 and Uin1, S2, S5, S6 disconnect.The drive singal of switch represents charging when being low level, and Uin1=Uin2=Uin.
The voltage getting C1, C4, C7, C10 sequentially represents the voltage of the first row, the second row, the third line, fourth line, and represents with Uc1, Uc4, Uc7, Uc10 respectively.Often row electric capacity have passed through the charging interval of a t, experienced by the discharge time of 3*t.Because of Uout=Uc1+Uc4+Uc7+Uc10, and can have a line capacitor charging in each T/4, three row electric capacity discharge simultaneously, and do not have Dead Time, so exporting Uout is straight line.As the Uout line in Fig. 3.
Claims (5)
1. the DC boosting matrix circuit structure be made up of electric capacity, diode, switch, this matrix circuit structure comprises: one end of out-put supply is connected to one end of the first row electric capacity, and the other end of out-put supply is connected to the other end of last column electric capacity by diode; One end of input power is connected with last column capacitance respectively by first row switch, and the other end of input power is connected with first row electric capacity respectively by secondary series switch; With between two electric capacity adjacent in a line electric capacity with two diodes in parallels in the same way, and in two diodes one or two just public diode; Sequentially directly connect in the same way between same column capacitance.
2. DC boosting matrix circuit structure as claimed in claim 1, " one end of out-put supply is connected to one end of the first row electric capacity, and the other end of out-put supply is connected to the other end of last column electric capacity by diode " wherein specifically comprises: the first row electric capacity is electric capacity three (C3), electric capacity two (C2), electric capacity one (C1); One end (Uout+) that diode one (D1) diode two (D2) is parallel to out-put supply is passed through by one end of diode two (D2), electric capacity one (C1) in one end of electric capacity three (C3), one end of electric capacity two (C2); Last column electric capacity is electric capacity nine (C9), electric capacity eight (C8), electric capacity seven (C7); The other end of electric capacity nine (C9) is connected to the other end of electric capacity eight (C8) by diode eight (D8), the other end of electric capacity eight (C8) is connected to the other end of electric capacity seven (C7) by diode seven (D7), the other end of electric capacity nine (C9) passes through by the other end of diode ten (D10), electric capacity seven (C7) other end (Uout-) that diode nine (D9) is parallel to out-put supply by the other end of diode 11 (D11), electric capacity eight (C8) simultaneously; And diode one (D1) diode two (D2) diode eight (D8) diode seven (D7) is in the same way in capacitance matrix.
3. DC boosting matrix circuit structure as claimed in claim 1, " one end of input power is connected with last column capacitance respectively by first row switch; the other end of input power is connected with first row electric capacity respectively by secondary series switch " wherein specifically comprises: first row switch is switch one (S1), switch two (S2), switch three (S3), and last column capacitance is electric capacity one (C1), electric capacity four (C4), electric capacity seven (C7); The not common end of switch one (S1), one end of electric capacity one (C1) are connected in parallel, one end of the not common end of switch two (S2), the other end of electric capacity one (C1), electric capacity four (C4) is connected in parallel, one end of the not common end of switch three (S3), the other end of electric capacity four (C4), electric capacity seven (C7) is connected in parallel, and the common port of the common port of switch one (S1), the common port of switch two (S2), switch three (S3) is parallel to one end (Uin+) of input power; Secondary series switch is switch four (S4), switch five (S5), switch six (S6), and first row electric capacity is electric capacity three (C3), electric capacity six (C6), electric capacity nine (C9); One end of the not common end of switch four (S4), the other end of electric capacity three (C3), electric capacity six (C6) is connected in parallel, one end of the not common end of switch five (S5), the other end of electric capacity six (C6), electric capacity nine (C9), to be connected in parallel, the not common end of switch six (S6), the other end of electric capacity nine (C9) are connected in parallel, and the common port of the common port of switch four (S4), the common port of switch five (S5), switch six (S6) is parallel to the other end (Uin-) of input power.
4. DC boosting matrix circuit structure as claimed in claim 1, wherein " with between two electric capacity adjacent in a line electric capacity with two diodes in parallels in the same way; and in two diodes one or two just public diode " specifically comprise: in the first row, have electric capacity three (C3), electric capacity two (C2) and diode two (D2), diode four (D4), have electric capacity six (C6), electric capacity five (C5) and diode four (D4), diode six (D6) in a second row; One end of electric capacity three (C3), the other end of diode two (D2) are connected in parallel, one end of diode two (D2), one end of electric capacity two (C2) are connected in parallel, the other end of electric capacity three (C3), the other end of diode four (D4) are connected in parallel, and one end of diode four (D4), the other end of electric capacity two (C2) are connected in parallel; One end of electric capacity six (C6), the other end of diode four (D4) are connected in parallel, the other end of electric capacity six (C6), the other end of diode six (D6) are connected in parallel, one end of diode four (D4), one end of electric capacity five (C5) are connected in parallel, and one end of diode six (D6), the other end of electric capacity five (C5) are connected in parallel; Diode two (D2) is not common diode, and diode four (D4) is public diode.
5. DC boosting matrix circuit structure as claimed in claim 1, " sequentially directly connecting in the same way between same column capacitance " wherein specifically comprises: in same row, have electric capacity three (C3), electric capacity six (C6), electric capacity nine (C9); The other end of electric capacity three (C3), one end of electric capacity six (C6) are connected in parallel, and the other end of electric capacity six (C6), one end of electric capacity nine (C9) are connected in parallel.
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| CN105529917A (en) * | 2016-01-21 | 2016-04-27 | 中山芯达电子科技有限公司 | High efficiency fast voltage generating circuit |
| CN106208696A (en) * | 2016-08-31 | 2016-12-07 | 顺德职业技术学院 | The program control DC voltage booster circuit of Waterwheel-type |
| CN107979303B (en) * | 2016-10-23 | 2021-04-09 | 北京华隆浩宏机电工程有限公司 | AC-DC reversible matrix circuit |
| CN107276203A (en) * | 2017-06-20 | 2017-10-20 | 昆明理工大学 | A kind of photovoltaic battery panel low-voltage electric power storage and high-voltage discharge device, its control method and application |
| CN112290651A (en) * | 2020-10-18 | 2021-01-29 | 马东林 | Capacitive energy storage matrix structure and charge-discharge control method thereof |
| CN112332684B (en) * | 2020-11-23 | 2023-09-15 | 江苏华鹏智能仪表科技股份有限公司 | AC-DC synchronous rectification circuit and control method thereof |
| CN113992034B (en) * | 2020-12-07 | 2023-08-08 | 马东林 | Alternating current voltage regulating circuit and control method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1474500A (en) * | 2002-08-05 | 2004-02-11 | 电子科技大学 | Circuit and method for realizing DC transformer using switch capacitor array |
| CN1761136A (en) * | 2004-10-11 | 2006-04-19 | 天利半导体（深圳）有限公司 | Charge pump circuit |
| CN101317320A (en) * | 2005-11-30 | 2008-12-03 | Nxp股份有限公司 | Charge pump circuit and integrated circuit |
| CN101752910A (en) * | 2008-12-03 | 2010-06-23 | 光宝科技股份有限公司 | Power supply device with variable voltage output |
-
2010
- 2010-11-29 CN CN201010564521.1A patent/CN102035373B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1474500A (en) * | 2002-08-05 | 2004-02-11 | 电子科技大学 | Circuit and method for realizing DC transformer using switch capacitor array |
| CN1761136A (en) * | 2004-10-11 | 2006-04-19 | 天利半导体（深圳）有限公司 | Charge pump circuit |
| CN101317320A (en) * | 2005-11-30 | 2008-12-03 | Nxp股份有限公司 | Charge pump circuit and integrated circuit |
| CN101752910A (en) * | 2008-12-03 | 2010-06-23 | 光宝科技股份有限公司 | Power supply device with variable voltage output |
Non-Patent Citations (1)
| Title |
|---|
| 电荷泵电路的动态分析;徐志伟等;《固体电子学研究与进展》;20010330;第21卷(第1期);21-28 * |
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Effective date of registration: 20200930 Address after: 215200 No. 1188 west two ring road, Shengze Town, Wujiang District, Suzhou, Jiangsu. Patentee after: Suzhou Shengze science and Technology Pioneer Park Development Co.,Ltd. Address before: 610211 Sichuan Province, Chengdu city Shuangliu County Street West Road No. 33 2 Hong Kong sheep double unit 1 Building No. 705 Patentee before: Ma Donglin |