Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03C—MODULATION
  • H03C3/00—Angle modulation
  • H03C3/02—Details
  • H03C3/09—Modifications of modulator for regulating the mean frequency
  • H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
  • H03C3/0991—Modifications of modulator for regulating the mean frequency using a phase locked loop including calibration means or calibration methods
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03C—MODULATION
  • H03C3/00—Angle modulation
  • H03C3/02—Details
  • H03C3/09—Modifications of modulator for regulating the mean frequency
  • H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
  • H03C3/0941—Modifications of modulator for regulating the mean frequency using a phase locked loop applying frequency modulation at more than one point in the loop
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03C—MODULATION
  • H03C3/00—Angle modulation
  • H03C3/02—Details
  • H03C3/09—Modifications of modulator for regulating the mean frequency
  • H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
  • H03C3/095—Modifications of modulator for regulating the mean frequency using a phase locked loop applying frequency modulation to the loop in front of the voltage controlled oscillator
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03C—MODULATION
  • H03C3/00—Angle modulation
  • H03C3/02—Details
  • H03C3/09—Modifications of modulator for regulating the mean frequency
  • H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
  • H03C3/0966—Modifications of modulator for regulating the mean frequency using a phase locked loop modulating the reference clock
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03C—MODULATION
  • H03C3/00—Angle modulation
  • H03C3/02—Details
  • H03C3/09—Modifications of modulator for regulating the mean frequency
  • H03C3/0908—Modifications of modulator for regulating the mean frequency using a phase locked loop
  • H03C3/0975—Modifications of modulator for regulating the mean frequency using a phase locked loop applying frequency modulation in the phase locked loop at components other than the divider, the voltage controlled oscillator or the reference clock

Definitions

• the present application relates to the field of angle or phase modulation of a carrier signal.
• Angle or phase modulators are typically used in digital transmitters to encode messages in the phase of the output signal from the transmitter .
• High speed links require a large modulation bandwidth in the phase modulator.
• One method of modulation is to configure a single wide band loop so that all the modulation is performed inside the loop. In this manner, the loop stabilizes around the modulation.
• the main problem with using a single wide band loop is that a lot of noise is present.
• a dual path modulation system can be used. This dual path modulation system typically keeps the main loop relatively narrow so that the noise can be controlled.
• using a narrow band main loop leaves fairly wide band modulations where the higher frequencies outside the main loop still have to be calibrated so that the overall gain is flat.
• One dual-path method to is to use an angle or phase modulating system including a phase locked loop and apply the phase information to the main loop reference while simultaneously applying modulation directly to an analog voltage controlled oscillator used for the transmitter signal.
• the main loop reference is also called a direct path.
• the modulation is applied to a voltage controlled oscillator (VCO) via an auxiliary modulation path separate from the direct path.
• VCO voltage controlled oscillator
• Figure 1 illustrates an exemplary block diagram of a conventional dual path angle modulator 10 as described in U.S. Patent No. 6,094,101, which is incorporated herein by reference.
• the output of the main loop VCO 28 is mixed, via mixer 30, with the output of an offset PLL 32 to produce an IF (intermediate frequency) output signal frequency equal to the difference between the main loop VCO frequency and the offset loop frequency.
• the IF output signal is the feed back signal needed to measure the output phase and is processed in the remainder of the circuitry, which is all digital, to produce a control signal for the main loop VCO 28.
• the main loop VCO 28 produces the desired output signal phase.
• the digital circuitry has two paths, one low frequency path directly through the loop and a high frequency path with a scaling gain of MS.
• the scaling factor MS is adjusted for flat overall frequency response, and provides for balancing of the gain among the low-frequency, or direct, path and the high-frequency, orauxiliary, modulation path. Determination and application of the proper value of MS requires a calibration procedure .
• a known modulation signal is applied and the output is measured.
• the known modulation signal is generated by the phase modulation generator 12, which is applied to the digital synthesizer 18 to output the signal S.
• An analog to digital converter (ADC) 34 such as a Sigma-Delta frequency to digital converter, provides a measured signal M which is a digital representation of the analog frequency output from the VCO 28.
• a logic circuit 36 receives the signal S and the signal M, and outputs an error signal ⁇ representing the frequencyerror between the signal S and the signal M.
• the error signal ⁇ is filtered using a digital filter, represented as the Kl block 20 and the K2/s block 22 in Figure 1.
• the output of the Kl block 20 is a frequency error signal and the output of the K2/s block 22 is a phase error signal.
• the frequency error signal and the phase error signal are directed to a DAC 26 via a summing logic circuit 24.
• the scaling factor FS is used to add angle modulation waveform to the frequency error signal and the phase error signal via the summing logic circuit 24.
• the output signal of the DAC 26 is applied through resistors Rl and R2 to an integrating capacitor Cl.
• the voltage stored on the integrating capacitor Cl is applied to the VCO 28.
• the auxiliary modulation path is used to modify a modulation voltage applied to the VCO 28 in the main loop.
• the modulation signal generated by the phase modulation generator 12 is applied to a modulation DAC 42 via an MS multiplier 38.
• the MS multiplier 38 applies the scaling factor MS to the modulation signal.
• An output signal of the modulation DAC 42 is applied to the VCO 28 via the integrating capacitor Cl .
• the modulating signal of the auxiliary path is scaled by the gain parameter MS, via the MS multiplier 38, and also scaled by the scaling factor FS, via the FS multiplier 40, and applied to the main loop at the summing logic circuit 24.
• the calibrationprocedure is eitherdonemanuallyusing swept frequency techniques ordone automaticallyusing special calibration signals .
• approaches are intrusive to the normal operation of such an angle or phase modulator because the calibration procedure can not be performed while the system is in operation. Instead, operation of the system must be suspended, and only during such a lapse time can the calibration procedure be performed.
• Many conventional systems are designed to operate in bursts, which provide the necessary lapse time to perform the calibration procedure. Examples of such systems include GSM systems, other cellular networks, or any network using TDMA (time division multiple access).
• a transmitter included within such a system operates in a stand-by mode for a portion of the time.
• the transmitter When it is time to transmit, the transmitter is awakened from stand-by mode, a calibration procedure is executed, the transmission is made, and the transmitter goes back to stand-by mode.
• CDMA code division multiple access
• the transmitter is operating at all times, and there are no natural periods or intervals of down time where a calibration procedure can be performed. It is critical to the operation of a dual path modulator that both paths have exactly the same gain, so calibration of the two paths is still necessary.
• the present application is directed to a multiple path angle modulator in which a closed secondary loop is added to a main control loop to automatically adjust a scaling factor related to high frequency gain to the angle modulation.
• This improves conventional dual path modulators and provides a real time method for balancing the two or more phase modulation paths in a closed loop phase modulator. This is done by taking advantage of the fact that the desired phase modulation signal is distributed in frequency such that components fall into the frequency response of all the modulation paths .
• Any subsequent discussion referring to frequency or phase refers in general to frequency, phase, and phase differential, where appropriate.
• the main control loop can be configured as a primary path to process the low frequency portion of the phasemodulation signal
• the secondary loop is configured as an auxiliary path to process the high frequency portions of the phase modulation signal.
• the secondary loop senses calibration information and uses it to calibrate the gain within each loop.
• additional auxiliary paths are configured to further de-couple the frequency spectrum.
• the two or more phase modulation paths are balanced when the output phase of a phase locked loop VCO in the main control loop exactly matches the input phase, thereby meeting calibration requirements for the gain in each path.
• a varying frequency input signal can be applied to the multiple path angle modulator.
• the term "a phase lock loop” refers generally to "a frequency control loop” and "a phase control loop” since the circuit is not restricted to being “locked” to a single frequency or phase.
• the output phase is. detected or measured and compared to the input or desired phase .
• the difference signal between these two phase signals is determined and used to systematically adjust the gain of each of the paths until the detected or measured output signal phase matches the input signal phase.
• the low frequency path is fixed and is used to maintain control of the center frequency of the output signal from the VCO.
• the described angle modulator In contrast to conventional dual path angle modulators that require a lapse time to perform a calibration procedure, the described angle modulator continuously calibrates each path while the system performs its primary operation. In other words, the angle modulator described in this application uses a calibration process running in thebackgroundduringnormal operations , thereby eliminating the need for a system shut down or calibration specific timing, such as a lapse time, to balance the modulation paths. In other systems that require a lapse time, a command is required to initiate the calibration procedure. Within the system as presently described, calibration is continuously performed as a background process.
• a modulating circuit includes a phase control loop and a modulating loop.
• the phase control loop outputs an analog angle modulation signal in response to an input desired angle modulation signal.
• the phase control loop includes a difference logic circuit to receive as input a first bit stream representing the desired angle modulation signal and a second bit stream representing the analog angle modulation signal and to output an output bit stream representing a difference quantity between the first bit stream and the second bit stream, and a controlledoscillator to output the analog anglemodulation signal .
• the modulating loop is coupled to receive the output bit stream from the difference logic circuit and coupled to an input terminal of the controlled oscillator.
• the modulation loop includes a modulation gain circuit to receive the output bit stream and to automatically output a gain parameter, and a multiplier to receive as input the gain parameter and an input bit stream representing the desired angle modulation signal and to output a calibrating modulation signal to the input terminal of the controlled oscillator .
• the phase control loop also includes a control circuit to receive the output bit stream from the difference logic circuit and to output a filtered analog difference signal.
• the input terminal of the controlled oscillator includes a summing circuit to receive as input the filtered analog difference signal from the control circuit and the calibrating modulation signal from the multiplier.
• the modulation gain circuit can comprise a gate circuit and an accumulator.
• the gain parameter comprises an accumulated value within the accumulator representative of the accumulated difference quantities output by the difference logic circuit.
• the gate circuit can comprise an exclusive OR gate or an AND gate.
• the accumulator can be configured to adjust a rate by which the difference quantity converges tpwards zero.
• the gate circuit can utilize an absolute value of a magnitude of the difference quantity output by the difference logic circuit .
• amodulating circuit comprises aphase control loop to output an analog anglemodulation signal in response to an input desired angle modulation signal and a modulating loop coupled to the forwardportion of the phase control loop .
• a forward portion of the phase control loop includes a control circuit to receive as input a bit stream representing a difference quantity between the analog angle modulation signal and the desired angle modulation signal and to output a filtered analog difference signal , and a controlled oscillator to output the analog angle modulation signal.
• the modulation loop includes a modulation gain circuit to receive the bit stream representing the difference quantity between the analog angle modulation signal and the desired angle modulation signal and to automatically output a gain parameter, and a multiplier to receive as input the gain parameter and an input bit stream representing the desired angle modulation signal and to output a calibrating modulation signal.
• the controlled oscillator receives as input the calibrating modulation signal and the filtered analog difference signal.
• the forward portion of the phase control loop can comprise a summing circuit to receive the calibrating modulation signal and the filtered analog difference signal and to output a controlling signal to the controlled oscillator.
• the phase control loop can include a difference logic circuit to receive as input a first bit stream representing the desired angle modulation signal and a second bit stream representing the analog angle modulation signal and to output the output bit stream representing the difference quantity between the analog angle modulation signal and the desired angle modulation signal to the control circuit.
• the modulation gain circuit can comprise a gate circuit and an accumulator.
• the gain parameter comprises an accumulated value within the accumulator representative of the accumulated difference quantities output by the difference logic circuit.
• the gate circuit can comprise an exclusive OR gate or an AND gate.
• the accumulator can be configured to adjust a rate by which the difference quantity converges towards zero.
• the gate circuit can utilize an absolute value of a magnitude of the difference quantity output by the difference logic circuit .
• the gate circuit can comprise a qualifier and a FIR filter.
• a modulating circuit comprises a controlled oscillator to output an analog angle modulation signal , a digital synthesizer to receive an input desired angle modulation signal and to output a first digital bit stream representing the angle modulation signal, a difference logic circuit coupled to receive the first digital bit stream from the digital synthesizer and a second digital bit stream representing the analog angle modulation signal, wherein the difference logic circuit outputs an output bit stream representing a difference quantity between the analog anglemodulation signal and the desired anglemodulation signal, a control circuit coupled to the difference logic circuit to receive the output bit stream, wherein the control circuit outputs a filtered analog difference signal, a modulation gain circuit coupled to the difference logic circuit to receive the output bit stream, wherein the modulation gain circuit outputs a gain parameter, a multiplier coupled to receive an input bit streamrepresenting the desiredanglemodulation signal andcoupled to the modulation gain circuit to receive the gain parameter, wherein the multiplier outputs a
• the controlled oscillator, the difference logic circuit, the control circuit , and the summing circuit form a phase control loop .
• the output bit stream from the difference logic circuit drives a forward path of the phase control loop.
• the difference logic circuit, the modulation gain circuit, the multiplier, and the summing circuit form a modulation loop.
• the modulation loop is coupled to the forward path of the phase control loop.
• the modulation gain circuit automatically determines the modulation gain such that a direct modulation gain of the phase control loop and a gain of the modulation loop are substantially equal.
• the modulation gain circuit can comprise a gate circuit and an accumulator.
• the accumulator outputs the gain parameter.
• An accumulated value representative of the accumulated difference quantities output by the difference logic circuit comprises the gain parameter.
• the gate circuit can comprise an exclusive OR gate, wherein the exclusive OR gate utilizes a sign and a magnitude of the difference quantity output by the difference logic circuit .
• the gate circuit can also comprise an AND gate, wherein the AND gate can utilize either a positive magnitude of the difference quantity output by the difference logic circuit or a negative magnitude of the difference quantity output by the difference logic circuit.
• the accumulator can be configured to adjust a rate by which the difference quantity converges towards zero.
• the gate circuit can be configured to utilize an absolutevalue of amagnitude of the difference quantity output by the difference logic circuit .
• the gate circuit can comprise a qualifier and a FIR filter.
• the modulation gain circuit can comprise an accumulator and a through gate.
• a modulating circuit comprises means for generating an analog angle modulation signal, means for generating an output bit stream representing a difference quantity between the analog angle modulation signal and an input desired angle modulation signal, means for adapting the output bit stream into a filtered analog difference signal, means for automatically determining a gain parameter in response to the output bit stream, means for multiplying the input desired angle modulation signal by the gain multiplier to generate a calibrating modulation signal, and means for combining the calibration modulation signal and the filtered analog signal into an input signal for the means for generating the analog angle modulation signal, wherein the means for generating the analog angle modulation signal generates the analog angle modulation signal in response to the input signal.
• FIG. 1 illustrates an exemplary block diagram of a conventional dual path angle modulator.
• FIG. 2 Figure 2 illustrates a conceptual block diagram of a dual path angle modulator.
• Figure 3 illustrates a block diagram of a first embodiment of the dual path angle modulator.
• FIG. 4 Figure 4 illustrates an exemplary block diagram of the accumulator included in the dual path anglemodulator of Figure 3.
• Figure 5 illustrates an expanded accumulator with convergence management .
• FIG. 6 Figure 6 illustrates a block diagram of another dual path angle modulator.
• the dual path angle modulator of the present application is configured to de-couple a narrow band including the center frequency from the wide band signal, and design the main control loop to process the narrow band signal.
• the forward path of the main control loop is said to be a low frequency path.
• An auxiliary modulation loop, or high frequency path is coupled to the main control loop to process the remaining portion of the wide band signal not processed by the main control loop.
• the dual path angle modulator provides a means for automatically sensing when the gain is too low and increasing it, or when the gain is too high and decreasing it.
• a feedback signal M is a digital representation of the analog output signal from the VCO.
• a directly synthesized signal S is a digital representation of the desired input signal.
• An error signal ⁇ is determined as the difference between the signal S and the signal M.
• the error signal ⁇ is zero. Even though circuit artifacts such as phase noise keep this from being true at all times , over the long term, the error signal ⁇ continuously converges towards zero.
• the gain scaling factor MS is applied to the high frequency path.
• a second feed-forward scaling factor FS is fixed and determined by the operational requirements of the output circuit.
• FIG. 2 illustrates a generalized block diagram of the dual path angle or phase modulator.
• the dual path angle modulator 50 includes a primary control loop and a secondary, or auxiliary, modulation loop.
• the primary loop includes a phase locked loop with a VCO 60 that generates an analog output signal.
• the analog output signal is provided as feedback to a difference logic circuit 54.
• the difference logic circuit 54 outputs the error signal ⁇ .
• the secondary loop includes a modulation gain normalizing block 64 that automatically and continuously determines the gain parameter MS based on the error signal ⁇ .
• the mean of the error signals ⁇ are zero.
• FIG. 3 illustrates a block diagram of a first embodiment of the dual path angle modulator 100 of the present application.
• the dual path angle modulator 100 of Figure 3 is similar to the dual path angle modulator 10 of Figure 1 with the addition of the auxiliary modulation loop that includes a gate 144 and a processing circuit 150 to provide a feedback loop within the auxiliary modulation path.
• the modulation gain normalization block 64 of Figure 2 comprises the gate 144 and the processing circuit 150.
• the dual path angle modulator 100 is an embodiment of the apparatus for performing the measurement and adjustment functions described above in relation to Figure 2.
• the processing circuit 150 is an accumulator.
• the error signal ⁇ includes a sign and some measure of magnitude over time .
• the gate 144 can take various embodiments that take advantage of different combinations and usages of the signs and magnitudes. For, example, an XOR gate utilizes both sign and magnitude, and converges very quickly. An AND gate only looks at one sign, such as only processing positively signed values while ignoring negatively signed values. The AND gate converges less quickly than the XOR gate. A THROUGH option ignores sign and only uses the magnitude.
• the output of the gate is a modified error signal ⁇ f .
• the accumulator 150 accumulates the modified error signals ⁇ ' .
• the numbers ( error signals ⁇ ' ) going to the accumulator 150 are negative when the gain is too low. If the gain is too high, then the numbers are positive, which indicates that there is too much gain in the forward path.
• the modulation is a zero-mean process because the accumulator 150 accumulates errors both positive and negative, so there is guaranteed convergence to an accumulated value within the accumulator 150. This accumulated value is the gain parameter MS. As the accumulator 150 converges towards the gain parameter MS, the error signal ⁇ heads towards zero . When the error signal ⁇ is zero , the value in the accumulator 150 corresponds to the optimal gain parameter MS.
• the frequency constant block 114 represents a carrier signal.
• a modulation is generated by the phasemodulation generator 112 , which is added to the carrier signal, via the summing circuit 116, to generate a desired input signal.
• the digital synthesizer 118 converts the desired input signal to a numeric stream, the desired input signal S.
• the Kl block 120 and the K2/s block 122 act as digital filters.
• the signal coming out of the Kl block 120 is the frequency error and the signal coming out of the K2/s block 122 is the phase error.
• the error signal ⁇ is also directed to the gate 144, which provides the modified error signal ⁇ ' to the accumulator 150.
• the FS multiplier 140 and the Sigma Delta DAC 126 function similarly as in Figure 1.
• the configuration of the resistors and the capacitors are exemplary. and can take other embodiments.
• the dual path angle modulator 100 of Figure 3 modifies the structure of Figure 1 in such a way that the gain parameter MS is automatically determined without need for an external process and on an on-going basis.
• the MS multiplier 138 receives the gain parameter MS from the accumulator 150 to scale the modulation in the forward path of the auxiliary modulation loop.
• the gain parameter MS also influences the gain in the main control loop, as the scaled modulation signal output from the MS multiplier 138 is used as an input to the FS multiplier 140.
• the analog output signal from the VCO 128 is provided as feedback and converted to the digital signal M by the analog to digital converter 134.
• the analog to digital converter 134 can be a Sigma Delta frequency to digital converter. Both signal S and signal M has full bandwidth information, including the modulation.
• the Kl digital filter 120 and the K2/s digital filter 122 in the main control loop function as a low pass filter. The main control loop processes the narrow band center frequency, but the information related to high bandwidth errors are present in the error signal ⁇ . This error information is processed within the gate 144 and the accumulator 150 to determine the gain parameter MS.
• the gain parameter MS is too low, then the signal M does not equal the desired signal S. As a result, the high frequency modulation components of the signal M do not subtract completely the high frequency modulation components from the signal S, and so an error signal ⁇ results. Since there is not enough high frequency components on this error signal ⁇ , the value stored within the accumulator 150 ramps up, making the gain parameter MS larger. The increased gain parameter MS is applied to the forward path of the auxiliary modulation loop, which acts to increase the normalized modulator gain up toward the normalized condition. Likewise, if the gain parameter MS is increased too high, then too much high frequency modulation is coming in on the signal M.
• the error signal ⁇ reflects that the gain is too high and the value in the accumulator 150 ramps down, making gain parameter MS smaller.
• a difference between the feedback signal M, which is a digital representation of the analog output signal from the VCO 128, and the signal S, which is a digital representation of the desired input signal is represented as the error signal ⁇ . Accordingly, until the output signal from the dual path angle modulator and the desired input signal coincide with each other in the calibration procedure, the value of the error signal ⁇ is presumed to alternately take positive andnegative values and to eventually converge to zero. For this reason, particular attention should be given during the process of generating the gain parameter MS based on the error signal ⁇ .
• the gate 144 operates on the error signal ⁇ . Variations in the implementation of the gate 144 yields different performance for the dual path angle modulator 100. Some options already identified are described in greater detail below. If the gate 144 is an exclusive-OR (XOR) gate, then the signed error signal ⁇ is sampled with normalized modulation using all samples of the error signal. Using the XOR gate, the accumulator 150 determines the value of MS according to:
• MS j+1 MS j + ( ⁇ sgn(S j ) ⁇ j
• the value k represents the number of most significant bits set to zero within the accumulator 150, which is explained in greater detail below.
• the gate 144 is an AND gate , only half the error signal ⁇ is output from the gate 144 and applied to the accumulator 150. In other words, half the error information is utilized.
• the AND gate outputs all positively signed error signal ⁇ values, and all negatively signed error signal ⁇ values are ignored.
• the AND gate outputs all negatively signed error signal ⁇ values, and all positively signed error signal ⁇ values are ignored. Use of the AND gate takes longer for the gain parameter MS to converge since only half the information is used.
• the accumulator 150 can determine the value of MS according to:
• the gate 144 can also be a simple wire, previously referred to as a THROUGH gate, where the error signal ⁇ passes directly to the accumulator 150. This is less effective but does eventually converge . In this case , all samples of the error signal ⁇ are used, and modulation information is ignored such that the accumulator determines the value of MS according to:
• Figure 4 illustrates an exemplary block diagram of the accumulator 150 included in the dual path angle modulator 100 of Figure 3.
• the difference measurements output from the gate 144 e.g. the modified error signal ⁇ ', enter the accumulator 150 on the least significant bits.
• the higher significant bits are set to zero.
• the symbol k defines the number of higher significant bits.
• the rate at which the accumulator 150 converges is controlled.
• Increasing k is accomplished by setting the value of the more higher significant bits to zero. This acts to slow down the convergence of the accumulator 150.
• the speed of the accumulator 150 is controlled by increasing the number of higher significant bits set to zero, which slows down the accumulator 150, or by reducing the number of higher significant bits set to zero, which speeds up the accumulator 150.
• the accumulator 150 can perform some filtering by only taking the top L most significant bits as the gain parameter MS. L is determined as a design practice based on how much filtering is desired and how fast the accumulator 150 is to respond. By entering the modified error signal ⁇ ' as the least significant bits within the accumulator 150 , and then taking the gainparameter value from the most significant bits , a natural filtering function is achieved. [0038] The automatic calibration loop converges to the correct gain parameter MS independent of the initial state of the accumulator 150. This is true even if the signal to noise ratio of the feedback signal M is poor. noisysy inputs result in a slight wandering of the desired gain parameter MS, causing distortion in the desiredmodulation anddegrading signalqualitymeasurements such as EVM. Accordingly, the automatic calibration loop could be designed to both sense that convergence is occurring, and also to narrow its loop bandwidth when converged. Narrowing the loop bandwidth is achieved by slowing down the correction variation rate within the accumulator 150.
• the expanded accumulator 250 of Figure 5 can automatically adjust the value of k by detecting small changes between successive values of the gain parameter MS.
• An alternative method would be to detect inputs to the accumulator near zero, but this latter method does not enjoy the averaging effects of the accumulator.
• the ACC N block 150 represents the accumulator of Figure 4.
• the expanded accumulator 250 takes the difference between successive outputs of the accumulator ACC N 150.
• the modified error signal ⁇ ' enters a manipulation block 152 under the control of the k select block 160 such that the number of higher significant bits set to zero equals k, as determined by the k select block 160.
• the accumulator ACC N 150 receives a bit stream in which the k most significant bits are set to zero and the remaining lower significant bits are the modified error signal ⁇ ' .
• the bit stream entering the ACC N 150 is shown in Figure 5 as the zeros on top to represent zeros as more significant bits.
• the function of the expanded accumulator 250 is to evaluate outputs of the accumulator ACC N 150, which is the gain parameter MS, and determine when the values are converging. In other words, taking the differences of sequential values MS 3 -I and MS j coming out of the accumulator ACC N 150 and as the difference, MS 3 - I - MS j , goes to zero, this provides implied information that the input, error signal ⁇ , has gone to zero.
• Each block R represents a clocked register.
• Each sequential value of MS is output from the accumulator ACC N 150 and stored in a register R 154 such that during a subsequent cycle, the current value, MS j , output from the accumulator 150 is compared to thepreviously storedvalue, MS j -i.
• the difference between these two values, MSj.i and MSj is determined by,logic circuit 156 and stored in a shift register 158, represented as the series of R blocks in Figure 5.
• the k select block 160 evaluates the difference to determine if the value of k is to be adjusted.
• the accumulator ACC N 150 is slowed down.
• the accumulator ACC N 150 is slowed by increasing the value of k, which coincides with more higher significant bits (k) being set to zero. In this manner, the expanded accumulator 250, shown in Figure 5 acts as a throttle mechanism for the accumulator ACC N 150.
• the speed by which the accumulator ACC N 150 subsequently converges is slowed by adding more higher order zeros (increase the value of k) .
• This mechanism can also be used to speed up the accumulator 150 by decreasing the value k.
• Occasion for slowing the accumulator ACC N 150 might occur when the determined difference is essentially noise .
• the impact of noise forces the value of MS to wander .
• the auxiliary modulation loop, including the accumulatorACC N 150 is continuously attempting to converge on a fixed value for the gain parameter MS, while noise in the system .acts to disrupt this convergence. It is observed that the noise contributes in small increments to the disruption of the convergence whereas if the error signal ⁇ is still significantly large, then convergence towards the gain parameter MS occurs in fairly large steps for a given time period.
• FIG. 6 illustrates a block diagram of another dual path angle modulator.
• the dual path angle modulator 200 of Figure 6 is similar to the first embodiment of the dual path angle modulator 100 of Figure 3 with the exception that a qualifier circuit 244 and finite input response (FIR) filter 246 replace the gate 144 of Figure 3.
• the intent of the gate is that there is some kind of conditioning applied to an input, such as the error signal ⁇ .
• the function of the qualifier circuit 244 and the FIR filter 246 is more complicated than agate .
• the qualifier circuit 244 measures the magnitude of the actual modulation, and only outputs those signals that fall within a particular range. The range and time of the input error signal ⁇ are limited using the qualifier 244.
• the qualifier circuit 244 refers to any type of circuit that functions to condition an input signal.
• the FIR filter 246 only filters those selected values of the error signal ⁇ that are output from the qualifier 244. Convergence using the second embodiment of the dual path angle modulator 200 is slower than the dual path angle modulator 100 of the first embodiment, which is desirable in certain situations, e.g. the presence of a high amount of noise.
• the qualifier circuit 244 and the FIR filter 246 in Figure 6 is similar to the functionality of the gate 144 in Figure 3, although the hardware is not related. Using the gate 144 in Figure 3, input error signal ⁇ is not being qualified, as is the qualifier circuit 244 and the FIR filter 246 in Figure 6, so the gate 144 is exposed to all measurements. This is the primary difference between the gate 144 and the qualifier circuit 244 and the FIR filter 246 combination.
• Running operation refers to processing a continuous stream of data .
• Block operation refers to processing of a block or blocks of data.
• N samples of the error signal ⁇ are used to calculate each update of the index j .
• Qualifiers are used on the ⁇ n 's.
• the variable h refers to the coefficients of the particular FIR filter. Use of this input filtering reduces the filtering requirements on the accumulator 150, allowing the accumulator 150 to run slower and have fewer bits in its construction. Acquisition of the gain parameter MS is somewhat slower, however the structure is more tolerant of noise.
• the FIR filter 246 is replaced by an infinite input response (HR) filter.
• HR infinite input response
• the error signals ⁇ are filtered using HR structures.
• the feedback used in HR structures suggests against the use of block operations.
• the accumulator 150 determines the value of MS according to:
• modulation is modified using methods similar to those in Least-Mean-Square (LMS) adaptive algorithms .
• the gate 144 is eliminated, such as the THROUGH gate option described above, and the accumulator 150 is configured to use the LMS adaptive algorithm.
• the dual path angle modulator of the present application includes amain control loop that is configured as a primary path to process the low frequency portion of the phase modulation signal, and an auxiliary modulation loop is configured as secondary path to process the high frequency portions of the phase modulation signal.
• the auxiliary modulation loop receives an error signal ⁇ that represents the difference between an output signal of the main control loop and a desired input modulation signal.
• the error signal ⁇ is manipulated and/or filtered before being input to an accumulator as a modified error signal ⁇ ' .
• the accumulator accumulates the values of the modified error signals ⁇ ' .
• the value of the accumulator is used as a gain parameter MS , which is used to normalize the gain within both the main control loop and the auxiliary modulation loop.
• the error signals ⁇ are continuously determined and used to update the gain parameter MS within the accumulator. In this manner, the dual path angle modulator continuously calibrates both paths as a background process.
• the first and second embodiments of the dual path angle modulator indicate that the error signal ⁇ can be manipulated and filtered using any type of gate, as in the first embodiment, or using a qualifier and FIR filter, as in the second embodiment. It is understood that the dual path angle modulator can manipulate and/or filter the error signal ⁇ using any other appropriate conventional type of circuitry.
• the angle or phase modulator is described above as a dual path modulator, the angle of phase modulator can be implemented to include more than two paths. In general, the angle of phase modulator is a multi-path angle or phase modulator.
• the present application has been described in terms of specific embodiments incorporating details to facilitate the understanding of the principles of construction and operation of the multiple path angle modulator. Many of the components shown and described in the various figures can be interchangedto achieve the results necessary, andthis description should be read to encompass such interchange as well. As such, references herein to specific embodiments and details thereof are not intended to limit the scope of the claims appended hereto. It will be apparent to those skilled in the art that modifications can be made to the embodiments chosen for illustration without departing from the spirit and scope of the application.

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