WO2007049850A1 - Dispositif de stockage de masse a fonctions xip et de stockage - Google Patents

Dispositif de stockage de masse a fonctions xip et de stockage Download PDF

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Publication number
WO2007049850A1
WO2007049850A1 PCT/KR2006/003226 KR2006003226W WO2007049850A1 WO 2007049850 A1 WO2007049850 A1 WO 2007049850A1 KR 2006003226 W KR2006003226 W KR 2006003226W WO 2007049850 A1 WO2007049850 A1 WO 2007049850A1
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WO
WIPO (PCT)
Prior art keywords
storage
xip
host
function
controller
Prior art date
Application number
PCT/KR2006/003226
Other languages
English (en)
Inventor
Un Sik Seo
Original Assignee
Mgine Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020050101570A external-priority patent/KR20050107369A/ko
Application filed by Mgine Co., Ltd. filed Critical Mgine Co., Ltd.
Priority to US12/083,328 priority Critical patent/US20090235013A1/en
Priority to JP2008537574A priority patent/JP2011517789A/ja
Publication of WO2007049850A1 publication Critical patent/WO2007049850A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0661—Format or protocol conversion arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0626—Reducing size or complexity of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators

Definitions

  • the present invention relates to a mass storage device for mobile phone having both XIP function and storage function, and more particularly to a mass storage device for mobile phone having both XIP function and storage function, in that a NAND flash memory is divided into an XIP (execute-in- place) area for executing a program code and a storage area for storing a mass data and a controller for directly arbitrating and controlling the XIP function and the storage control function is implemented, whereby each function of the NOR flash memory and the NAND flash memory can be implemented in one NAND flash memory.
  • a flash memory is a kind of a nonvolatile memory such as a ROM (read only memory) in that a recorded content once is stored without the supply of the power and a writing function is provided.
  • the flash memory is divided into a NOR flash memory having cells arranged in parellel between bit line and ground line and a NAND flash memory having cells arranged in series.
  • the NOR flash memory using a random access manner capable of reading and writing an arbitrary address irrelevantly to the order of the cells can be accessible in a bite unit.
  • the contacted electrodes are needed per each cell, there is a defect in that the cell area is very large in comparison with the NAND flash memory.
  • the corresponding block is selected and then, each cell connected to each other in series is read. Accordingly, the NAND flash memory can be accessible in a block unit.
  • the block means a unit capable of deleting with a deleting operation once and the page means a data size capable of reading or writing during a reading/writing operation.
  • the NAND flash memory has merits in comparison with the NOR flash memory in that the writing speed is fast, the cost is low and the capacity is large, thereby it can be widely used as a mass storage device.
  • it is impossible to be accessible in a bite unit and cannot provide a XIP function (execute-in-place) capable of directly executing the recorded data without moving it to a main memory.
  • the NAND flash memory is used as an auxiliary data storage device and a boot code for system booting is stored in the NOR flash memory having the XIP function.
  • FIG. 1 is a block diagram illustrating a conventional mass storage device for mobile phone.
  • the NAND flash memory 200 is used as the auxiliary data storage device and the boot code for system booting in a CPU 100 and a software for controlling the NAND flash memory as the storage device are stored in the NOR flash memory, as described above.
  • a DRAM 400 is a main memory used in the operation of the program and the system.
  • the program for controlling the NAND flash is moved to the DRAM 400 to be executed.
  • Korean patent application No. 10-2001- 54988 is disclosed in that a program code such as a boot code and so on is stored in the NAND flash memory and the corresponding program code is copied into a main memory during the execution of the program then, it reads out in a bite unit, thereby executing the program.
  • Korean patent No. 10-493884 is disclosed in that a serial flash controller device having a predetermined storage capacity is accessible to a serial flash memory to read the entire page pertaining to the necessary data, so that the requested data is transmitted to the main controller or is executed to support the XIP function in the serial flash memory.
  • the mass storage device capable of storing the program code and the mass data in one memory has been highly demanded.
  • an object of the present invention is to provide a mass storage device for mobile phone having both XIP function and storage function in that a NAND flash memory is divided into an XIP (execute-in-place) area for executing a program code and a storage area for storing a mass data and a controller for directly arbitrating and controlling the XIP function and the storage control function is implemented, so that two functions of the NOR flash memory and the NAND flash memory can be implemented in one NAND flash memory.
  • the present invention provides a mass storage device having both XIP function and storage function comprising: a NAND flash memory divided into an XIP (execute-in-place) area for storing a program code and a storage area for storing a mass data; and a controller for controlling the XIP area in such a manner that a host can be accessible to the XIP area through a NOR interface port at the request of an arbitrary access from the host and performing a storage interface function in such a manner that the host can be accessible to the storage area in a block unit through a storage interface port at the access request of a block unit from the host.
  • a NAND flash memory divided into an XIP (execute-in-place) area for storing a program code and a storage area for storing a mass data
  • a controller for controlling the XIP area in such a manner that a host can be accessible to the XIP area through a NOR interface port at the request of an arbitrary access from the host and performing a storage interface function in such
  • the controller comprises-' a XIP memory controller connected to the host through a NOR interface for controlling the XIP area in such a manner that the host can be accessible to the XIP area at the arbitrary access request of the host; a cache memory for temporarily storing data received from the host and the XIP area; a storage controller connected to the host through a storage interface for performing the storage interface function in such a manner that the host can be accessible to the storage area in the block unit at the access request of the block unit from the host!
  • a disk buffer for temporarily storing data recived from the host and the storage area; a system controller for selectively driving the XIP memory controller and the storage controller according to a data access manner requested from the host and controlling entire circuit operations', and a NAND controller interposed between the system controller and the NAND flash memory for controlling the NAND flash memory according to a NAND interface manner.
  • the XIP memory controller comprises a NOR host drive for supporting any operation at the request of the NOR flash interface and generating and renewing a memory manager table for the XIP and a XIP manager for converting an access address requested from the host into a physical address and performing a memory manager operation on a bad block;
  • the storage controller comprises a storage host drive for managing a protocol related to the storage and converting an information related to the storage into any data form suitable for the NAND flash and a storage manager for converting an access address requested from the host into a LUN (logical unit number) and performing a memory manager operation on the bad block;
  • the system controller serves to convert the physical address received from the XIP memory controller and the LUN (logical unit number) received from the storage controller into a block page address to be transmitted to the NAND controller.
  • the NAND controller comprises a flash translation layer for converting the requested physical address and logical unit number into an I/O command and a block address and managing and controlling a physical state of the NAND flash.
  • a part line of the address port, a data line, an output driving line, and a writing driving line can be used in common.
  • the NOR interface and the storage interface further comprise a waiting signal line for solving a difference between a data read time of the host and a data access time of a block unit in the NAND flash memory.
  • the NAND flash memory is divided into the XIP (execute-in- place) area for executing the program code and the storage area for storing the mass data and the controller for directly arbitrating and controlling the XIP function and the storage control function is implemented, thereby each function of the NOR flash memory and the NAND flash memory can be implemented in one NAND flash memory.
  • FIG. 1 is a block diagram illustrating a conventional mass storage device for mobile phone!
  • FIG. 2A is a block diagram illustrating a mass storage device for mobile phone according to one embodiment of the present invention
  • FIG. 2B is a block diagram illustrating a mass storage device for mobile phone according to another embodiment of the present invention.
  • FIG. 3 is a block diagram illustrating an interface structure of the present invention
  • FIG. 4 is a conceptional view illustrating a structure of a mass storage device for mobile phone according to the present invention from a standpoint of a CPU;
  • FIG. 5 is a stratified view illustrating a schematic construction of the controller according to the present invention.
  • FIG. 6 is a block diagram illustrating a detailed structure of the controller of FIG.5.
  • FIG. 7 is a waveform diagram illustrating a signal of the controller according to the present invention. [Best Mode]
  • FIG. 2A is a block diagram illustrating a mass storage device for mobile phone according to one embodiment of the present invention.
  • the mass storage device for mobile phone includes a CPU (central processing unit) 10, a NAND flash memory 30, a controller 20 interposed between the CPU 10 and the NAND flash memory 30, and a DRAM (dynamic random access memory) 35 as a main memory directly connected to the CPU 10.
  • CPU central processing unit
  • NAND flash memory a non-volatile memory
  • DRAM dynamic random access memory
  • the NAND flash memory 30 is divided into an XIP (execute-in-place) area 31 for storing a program code such as a boot code and so on and a storage area 33 for storing a mass data.
  • XIP executed-in-place
  • the partition ration of the XIP area 31 to the storage area 33 can be variable according to the environment or the purpose thereof.
  • the controller 20 serves to control the XIP area 31 in such a manner that the CPU 10 can be accessible to the XIP area 31 at the request of an arbitrary access from the CPU 10. Also, the controller performs a storage interface function in such a manner that the CPU 10 can be accessible to the storage area 33 in the block unit at the access request of a block unit from the CPU 10. The detailed construction thereof will be described in the explanation of FIG. 5 and FIG.6 below.
  • the controller 20 and the NAND flash memory 30 are mounted on one semiconductor package in the form of a multi-chip package.
  • a separate host drive for controlling the NAND flash memory 30 is not required, it can provide a convenience for use to a user.
  • FIG. 2B is a block diagram illustrating a mass storage device for mobile phone according to another embodiment of the present invention.
  • the NAND flash memory 30 and the DRAM 35 are connected to the CPU (host) 10 through the controller 20.
  • the controller 20 and the NAND flash memory 30 are also mounted on one semiconductor package in the form of a multi-chip package.
  • the separate host drive for controlling the NAND flash memory 30 is not required, it can provide a convenience for use to a user.
  • FIG. 3 is a block diagram illustrating an interface structure of the present invention.
  • the controller 20 includes a NOR interface 40 for interfacing with the CPU 10, a storage interface 50, and a NAND interface 60 for interfacing with the NAND flash memory 30.
  • the NOR interface 40 includes a chip sellection port (CS_XIP) for performing the XIP function as an interface accessible to a program code, an output controlling port (OE), a writing controlling port (WE) for recording a data in the NAND flash memory 30, an address port (ADDR) for inputting reading or recording address data, a data port (DQ) for inputting and outputting reading or recording data, and a waiting port (WAIT) for transmitting a wait signal to CPU 10 in order to solve the difference between a data reading time of the CPU 10 of a data access time of a block unit in the NAND flash memory 30.
  • CS_XIP chip sellection port
  • OE output controlling port
  • WE writing controlling port
  • ADDR address port
  • DQ data port
  • WAIT waiting port
  • the storage interface 50 includes a chip sel lection port (CS_IDE) for performing a storage interface controlling function through the CPU 10, a DMA request port (DREQ) for performing the DMA (direct memory access) function, and a DMA acknowledgement port (DACK) and so on.
  • CS_IDE chip sel lection port
  • DREQ DMA request port
  • DACK DMA acknowledgement port
  • a mass storage interface of various configurations such as an IDE/ATA, a hard disk manner, a SD (secure digital) card interface, multimedia card (MMC) interface, a memory stick interface and so on can be applied.
  • IDE/ATA protocol comprises an IDE (intelligent drive electronics) used as a hardware interface standard and ATA (advanced technology attachment) used as a protocol standard.
  • the output controlling port (OE), the writing controlling port (WE), a part line of the address port(ADDR), the data port (DQ) and the waiting port (WAIT) among the NOR interface ports can be used in common, so that the number of the connection ports can be decreased and the operation efficiency can be improved.
  • the NOR interface 40 for providing the XIP function has twenty six address lines and the storage interface 50 using the IDE/ATA interface has only three lines (0 to 2) among the address lines for addressing tracks and sectors.
  • the NAND interface 60 includes a chip sel lection port (CE) as an NAND flash memory access interface, input/output ports (1/00-7) for inputting and outputting the address, data and command, a command latch driving port (CLE) for latching the command inputted through the input/output ports, an address latch driving port (ALE) for latching the address inputted through the input/output ports (1/00-7), a writing driving port (WE) for recording the data inputted through the input/output ports (1/0 0-7) in the NAND flash memory 30, a reading driving port (RE) for transmitting the data outputted through the input/output ports (1/00-7), and a ready and busy port (R/B) for displaying a preparatory states of the present NAND flash memory 30.
  • CE chip sel lection port
  • CLE command latch driving port
  • ALE address latch driving port
  • WE writing driving port
  • RE for transmitting the data outputted through the input/output ports (1/00-7
  • R/B ready and busy port
  • FIG. 4 is a conceptional view illustrating a structure of a mass storage device for mobile phone according to the present invention from a standpoint of a CPU.
  • the CPU 10 recognizes the mass storage as two devices that is, one flash memory for XIP and one hard disk.
  • the CPU 10 recognizes that the XIP area 31 and the storage area 33 are physically and completely separated from each other. Accordingly, the present invention is characterized in that the different two flash memories (NOR flash memory and NAND flash memory) seems to be existed in the storage device using one NAND flash memory.
  • FIG. 5 is a stratified view illustrating a schematic construction of the controller according to the present invention and FIG. 6 is a block diagram illustrating a detailed structure of the controller of FIG. 5.
  • the controller 20 includes an internal clock generating portion 21, a XIP memory controller 22, a cache memory 23, a system controller 24, a storage controller 25, a disk buffer 26, a NAND controller 27, and a flash manager 28.
  • the XIP memory controller 22 is driven by a chip selection signal (nCS_XIP). Also, the XIP memory controller 22 serves to convert the address data inputted through the address port (ADDR) into a physical address and transmit it to the system controller 24. As shown in FIG. 5, in the XIP memory controller 22, a XIP host drive 70 and a XIP manager 75 for controlling the execution in place is installed through a software program or hard-wired to the chip. The XIP host drive 70 serves to support any operation (read, write, deletion and so on) at the request of the NOR flash interface. Also, the XIP (NOR) host drive 70 is any program for generating and controlling a memory manager table for the XIP.
  • the XIP manager 75 serves to convert the request address into a physical address, control the operation of the XIP memory controller 22 in a generation of a bad block, and perform the controlling and managing operations according to the kind of the NAND flash. Moreover, the XIP manager 75 serves to perform the determinating function of the priority order through the information exchange with the storage manager 85.
  • the data of the block unit read from the XIP area 31 of the NAND flash memory 30 is transferred to the cache memory 23 and only execution program code read from the cache memory 23 is transmitted to the DRAM 35 as the main memory. Also, in the XIP memory controller 22, the data read from the XIP area 31 of the NAND flash memory 30 and stored in the cache memory 23 and the storage information thereof are recorded in the specific place and the data stored in the cache memory 23 is transmitted to the DRAM 35 at the request of the same data, thereby shortening the data access time.
  • the storage controller 25 which is connected to the CPU 10 through the storage interface 50, performs the storage interface function in such a manner that the CPU 10 can be accessible to the storage area 33 in the block unit at the access request of the block unit from the CPU.
  • the storage controller 25 is driven by a chip selection signal (nCS_IDE). Also, the storage controller 25 serves to convert the address data inputted through the three lines among the address lines into a LUN (logical unit number) and transmit it to the system controller 24.
  • a storage host drive 80 and a storage manager 85 for the storage interface is installed through a software program or hard-wired to the chip.
  • the storage host drive 80 is any program for supporting and interpreting a protocol related to the storage and converting the information related to the interrupt manager and the storage into any data form suitable for the NAND flash.
  • the storage manager 85 serves to convert the request address into the LUN (logical unit number) and perform the manager operation on the bad block, the data protection for the urgent interruption of electric power, and the controlling and managing operations according to the kind of the NAND flash and so forth.
  • the storage manager 85 serves to perform the determinating function of the priority order through the information exchange with the XIP manager 75.
  • the data of block unit read from the storage area 33 of the NAND flash memory 30 is temporarily stored in the disk buffer 26 and then, transmitted to the CPU 10.
  • the system controller 24 serves to selectively drive the XIP memory controller 22 and the storage controller 25 according to the data access manner requested from the CPU 10 and control the entire circuit operations. Also, the system controller 24 serves to convert the physical address received from the XIP memory controller and the LUN (logical unit number) received from the storage controller 25 into a block page address capable of treating in the NAND controller 27 to be transmitted to the NAND controller 27, thereby the NAND flash memory 33 can be used in two interfaces that is, the NOR interface and the storage interface at the same time.
  • the system controller 24 serves to transmit a control signal to a demultiplexer, which the data lines of the cache memory 23 and the buffer 26 is inputted to, to selectively output the necessary data. For example, where the control signal of the system controller 24 is "0" , the data of the cache memory 23 is selectively outputted. Also, in case that the control signal of the system controller 24 is "1" , the data of the disk buffer 26 is selectively outputted.
  • system controller 24 can control the timing by outputting the wait signal (nWAIT). It will be described in the explanation of FIG.7.
  • the NAND controller 27 interposed between the system controller 24 and the NAND flash memory 30 serves to control the NAND flash memory 30 according to the NAND interface method. That is, The NAND controller 27 serves to read and record the data from the NAND flash memory 30 on the basis of the block page address received from the system controller 24.
  • a FTL (flash translation layer) 90 for managing and controlling the NAND flash memory 30 is installed through a software program or hard-wired.
  • the flash translation layer 90 serves to convert the requested physical address and logical unit number into an 1/0 command and a block address and maintain and manage the information on the bad block. Also, the flash translation layer 90 serves to assign the operation thereof during the reading, programming and deleting of the NAND flash and store and control the physical state of the NAND flash, thereby protecting the user' s data from the bad block.
  • FIG. 7 is a waveform diagram illustrating a signal of the controller according to the present invention.
  • the data reading of block unit is performed.
  • the code unit of the CPU 10 is very small, the time difference between them is generated.
  • the wait signal is provided (note a Wait of FIG. 7). Accordingly, where the code reading is performed without the wait time during the command code execution of the CPU 10, the code execution waiting of the CPU 10 is induced by the waiting signal generated from the storage device.
  • the memory bank of the CPU 10 for performing the code cannot receive the waiting signal, it can be used as an exceptional processing signal in the CPU 10.
  • a NAND flash memory is divided into the XIP (execute-in-place) area for executing the program code and the storage area for storing the mass data and the controller for directly arbitrating and controlling the XIP function and the storage control function is implemented, thereby each function of the NOR flash memory and the NAND flash memory can be implemented in one NAND flash memory.
  • the NAND flash memory is divided into the XIP (execute-in-place) area for executing the program code and the storage area for storing the mass data and the controller for directly arbitrating and controlling the XIP function and the storage control function is implemented, thereby each function of the NOR flash memory and the NAND flash memory can be implemented in one NAND flash memory.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Memory System (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

L'invention concerne un dispositif de stockage de masse pour téléphone mobile à fonction XIP et de stockage. Ledit dispositif de stockage de masse à fonction XIP et de stockage comprend une mémoire flash NON-ET divisée en une zone XIP (exécuter sur place) pour le stockage d'un code de programme et une zone de stockage pour stocker des données de masse, et un contrôleur conçu pour contrôler la zone XIP, de telle manière qu'un hôte peut accéder à la zone XIP via un port d'interface NON-OU, à la demande d'un accès arbitraire émanant de l'hôte, et pour réaliser une fonction d'interface de stockage, afin que l'hôte puisse accéder à la zone de stockage dans une unité de bloc, par le biais d'un port d'interface de stockage, à la demande d'accès d'une unité de bloc provenant de l'hôte.
PCT/KR2006/003226 2005-10-27 2006-08-17 Dispositif de stockage de masse a fonctions xip et de stockage WO2007049850A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/083,328 US20090235013A1 (en) 2005-10-27 2006-08-17 Mass Storage Device Having Both Xip Function and Storage Function
JP2008537574A JP2011517789A (ja) 2005-10-27 2006-08-17 直接実行制御機能とストレージ機能が複合された大容量保存装置

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2005-0101570 2005-10-27
KR1020050101570A KR20050107369A (ko) 2005-10-27 2005-10-27 모바일 기기를 위한 코드 직접 수행기능을 갖는 대용량저장장치 및 제어 방법
KR10-2006-0025969 2006-03-22
KR1020060025969A KR100610647B1 (ko) 2005-10-27 2006-03-22 직접실행제어 기능과 스토리지 기능이 복합된 대용량저장장치

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US20090106481A1 (en) * 2007-10-17 2009-04-23 Spansion Llc Hybrid flash memory device
US8560756B2 (en) * 2007-10-17 2013-10-15 Spansion Llc Hybrid flash memory device
JP2009123191A (ja) * 2007-11-15 2009-06-04 Genesys Logic Inc Ｎｏｒインターフェイスフラッシュメモリ装置及びそのアクセス方法
JP2009123185A (ja) * 2007-11-15 2009-06-04 Genesys Logic Inc フラッシュメモリ装置及びそのアクセス方法
JP2012510101A (ja) * 2008-11-24 2012-04-26 トムソン ライセンシング フラッシュ変換層を有するフラッシュ・ベースのメモリおよびファイル記憶方法
US9158469B2 (en) 2008-11-24 2015-10-13 Thomson Licensing Flash based memory comprising a Flash translation layer and method for storing a file therein
US9069488B2 (en) 2010-08-27 2015-06-30 Fxi Technologies As Electronic devices
US9134923B2 (en) 2010-08-27 2015-09-15 Fxi Technologies As Electronics device
US9451026B2 (en) 2010-08-27 2016-09-20 Millennium Enterprise Corporation Electronic devices

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