WO2007032067A1

WO2007032067A1 - Semiconductor device and its fabrication method

Info

Publication number: WO2007032067A1
Application number: PCT/JP2005/016943
Authority: WO
Inventors: Sergey Pidin
Original assignee: Fujitsu Limited
Priority date: 2005-09-14
Filing date: 2005-09-14
Publication date: 2007-03-22

Abstract

A logic embedded memory semiconductor device comprises an STI defining a plurality of active regions in a semiconductor substrate, a recess formed by removing part of the depth of the STI in a memory area, a capacitor storage electrode formed on the inner surface of the recess and extending along the top surface of an adjacent active region, a capacitor dielectric film formed on the capacitor storage electrode, a capacitor opposed electrode formed on the capacitor dielectric film, an access transistor formed in the active region along which the capacitor storage electrode extends and having a source and a drain one of which extends under the capacitor storage electrode to form an electrical connection, and a logic transistor formed in a logic area. The opposed electrode, capacitor dielectric electrode, and capacitor storage electrode constitute a memory capacitor, and the gate electrodes of the access transistor and logic transistor are formed using the same layer as the capacitor opposed electrode.

Description

Specification

Semiconductor device and manufacturing method thereof

Technical field

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a logic embedded memory and a manufacturing method thereof.

Background art

[0002] A logic-embedded memory including a logic (logic) circuit and a memory (memory) circuit has characteristics of a high transfer rate and low power consumption, and is indispensable for realizing a high-function, high-value-added system. ing. Dynamic random access memory (DRAM) consists of one transistor / capacitor and one memory cell. Although it is a volatile memory that loses its memory when the power is turned off, it can be driven without the need for a high voltage like a flash memory. Many capacitors dedicated to DRAMs are known to form a three-dimensional structure to improve the degree of integration. The three-dimensional structure manufacturing process is a special process that, when mixed with a logic circuit, reduces the reliability of the logic circuit.

In recent years, along with the improvement in the degree of integration of semiconductor devices, shallow trench isolation (STI) has been frequently used as an element isolation region in place of silicon local oxidation (LOCOS). As a surface flattening process, chemical mechanical polishing (CMP) is often used.

[0004] The memory capacitor of the logic embedded memory preferably has a planar structure in order to ensure reliability. However, when a planar structure capacitor is formed, the occupied area becomes large. There is a need for a capacitor that can ensure the same reliability as a planar capacitor and has a small footprint. There is a proposal to form a recess by excavating a part of the STI once formed, and to form a capacitor using the recess slope.

1A and 1B show a DRAM cell structure proposed in Patent Document 1. FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along the line AA ′ of FIG. 1A. In FIG. 1A, the active region AR surrounded by the shallow trench isolation STI is equivalent to two transistors on the left and right, and the central wide portion is a contact region connected to the bit line. Intersects with narrow areas on both sides The portion below the gate electrode G to be formed constitutes a channel. A partial force sandwiched between both gate electrodes G, for example, constitutes a common source region. A region outside both the gate electrodes G forms a drain region and a part of the capacitor. The main part of the capacitor is the area where the widths at both ends are widened.

[0006] As shown in FIG. 1B, an n-type wall NW is formed on a p-type substrate SUB. The shallow trench isolation STI is formed to an intermediate depth of n-rule NW and defines the active area AR (Fig. 1A). Using the resist mask, etch the STI-filled insulating film in the area surrounded by the broken line in Fig. 1A. A recess is formed in the STI, and the active region side wall shown in bold in FIG. 1A is exposed. After p-type impurities are implanted into the surface of the active region exposed from the resist mask to form a p-type region 55 that serves as a storage electrode of the capacitor, the resist mask is removed, the surface of the active region is oxidized, and a gate oxide film 57 is formed. At the same time as forming, a capacitor dielectric film 58 is formed.

[0007] Thereafter, a polycrystalline silicon film 60 is deposited and etched using a resist mask to form a gate electrode 60g and a capacitor counter electrode 60c. A low concentration p-type impurity is ion-implanted to form the source LDD region 61 and simultaneously form the drain region 62. After the sidewall spacer 64 is formed, ion implantation of high-concentration p-type impurities is performed to form a high-concentration source region 66, and the polycrystalline silicon films 60g and 60c are also doped into high-concentration p-type. After forming the oxide film 68 covering the capacitor portion, a silicide process is performed, and a silicide layer 69 is formed on the source region 66 and the gate electrode 60g.

[0008] After etching a part of the depth of the STI to expose the side wall of the active region, a capacitor is formed with the upper and side surfaces of the active region as one electrode, so that the electrode area of the capacitor is increased. It is said that the capacity can be increased. The process described as DRAM is the same as the MO transistor formation process except for STI etching and capacitor storage electrode formation ion implantation, and it is easy to mix with logic circuits.

[0009] Non-Patent Document 1 explains that it is important for planar-type DRAM-powered system-on-chip (SoC) applications that are suitable for mixed logic circuits. An example of creating the DRAM cell shown in Fig. 1C is reported. Access transistor force It is formed in the form having equivalent source / drain regions 66 and 62 Other than the above, it corresponds to the configuration shown in Fig. 1A and IB. Equivalent parts are indicated by the same reference numerals. In the comparative sample that does not form a recess with a 0.1 μm norail, the capacitance was 8 fFZ μm2, but with a sample that etched 0.15 μm deep recess into 0.35 zm deep STI, The desired capacity of 10 fFZ x m2 was obtained and the cell capacity was reported to have increased by 25%.

[0010] Patent Document 1: US Patent Publication No. 6,573,548

Non-Patent Document 1: Journal of The Electrochemical Society, 152 (1) G107-G109 (2005)

Disclosure of the invention

Problems to be solved by the invention

An object of the present invention is to provide a semiconductor device in which a logic circuit and a DRAM circuit are mixedly mounted, including a DRAM that can be manufactured without much change in a logic process and has a large capacitance per unit area. is there.

Another object of the present invention is to provide a highly reliable semiconductor device in which a logic circuit and a DRAM circuit are mounted, using an element isolation region by STI.

Another object of the present invention is to increase the capacitance of a capacitor in a form in which a capacitor is formed by digging a part of STI.

Means for solving the problem

[0013] According to one aspect of the present invention,

A semiconductor substrate having a logic region and a memory region;

A shallow trench formed by removing a semiconductor of a predetermined depth from one surface of the semiconductor substrate and defining a plurality of active regions;

An element isolation insulating film for filling the shallow trench;

A capacitor trench formed by removing a part of the element isolation insulating film from the memory region;

A capacitor storage electrode formed on the inner surface of the capacitor trench and extending to the upper surface of the adjacent active region;

A capacitor dielectric film formed on the capacitor storage electrode; A capacitor counter electrode formed on the capacitor dielectric film and constituting a memory capacitor facing the capacitor storage electrode;

An access transistor having one source Z drain region formed in an active region in which the capacitor storage electrode extends, enters under the capacitor storage electrode, and forms an electrical connection;

A logic transistor formed in an active region of the logic region;

The gate electrode of the access transistor and the logic transistor is formed using the same layer as the capacitor counter electrode.

Is provided.

The invention's effect

[0014] The storage electrode formed on the recess formed in the STI can have almost the entire area of the inner surface of the recess as the electrode area. Can be formed without using a special process, ensuring high reliability. Brief Description of Drawings

FIG. 1A-1C are a plan view and a cross-sectional view showing a conventional STI-use capacitor.

FIGS. 2A to 2C are cross-sectional views illustrating a method of manufacturing a logic embedded memory semiconductor device having an STI-use capacitor according to an embodiment of the present invention.

[FIG. 2-2] FIGS. 2D-2E are a plan view and a cross-sectional view showing a method of manufacturing a logic-embedded memory semiconductor device having an STI-use capacitor according to an embodiment of the present invention.

[FIGS. 2-3] FIGS. 2F-2H are cross-sectional views illustrating a method of manufacturing a logic embedded memory semiconductor device having an STI-use capacitor according to an embodiment of the present invention.

[FIG. 2-4] FIGS. 21-2J are cross-sectional views illustrating a method of manufacturing a logic embedded memory semiconductor device having an STI-use capacitor according to an embodiment of the present invention.

FIGS. 2K to 2L are cross-sectional views illustrating a method of manufacturing a logic embedded memory semiconductor device having STI-use capacitors according to an embodiment of the present invention.

[FIG. 2-6] FIGS. 2M-2N are cross-sectional views showing a method of manufacturing a logic embedded memory semiconductor device having STI-use capacitors according to an embodiment of the present invention. [FIG. 2-7] FIGS. 2O-2P are cross-sectional views illustrating a method of manufacturing a logic-embedded memory semiconductor device having STI-use capacitors according to an embodiment of the present invention.

[FIG. 3] FIGS. 3A-3C are a plan view and a cross-sectional view showing a method of manufacturing an STI-use capacitor according to another embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

2A to 2P show a method for manufacturing a logic-embedded memory semiconductor device according to an embodiment of the present invention. As shown in FIG. 2A, for example, an element isolation region 12 is formed in a p-type silicon semiconductor substrate 11 by shallow trench isolation (STI). For example, the surface of the silicon substrate is thermally oxidized to grow a buffer oxide film, and a silicon nitride film is formed thereon. A resist pattern having the shape of the active region AR is formed, and the silicon nitride film and the silicon oxide film are etched. Using the patterned silicon nitride film as a hard mask, the silicon substrate 11 is reactively etched to form a trench. For example, the upper end opening width of the trench is 200 nm and the trench depth is 300 nm. It is preferable to etch the trench side wall under an inclined condition.

[0017] After the silicon surface exposed in the trench is thermally oxidized to form a silicon oxide film liner 12x, a silicon nitride film liner 12η is formed by chemical vapor deposition (CVD). Silicon oxide film (undoped silicate glass USG) 12f is deposited by high-density plasma (HDP) CVD, and the trench is backfilled. Chemical mechanical polishing (CMP) is performed using the patterned silicon nitride film as a stopper to remove the deposition curtain on the silicon nitride film and planarize the surface. The silicon nitride film is removed by etching with hot phosphoric acid, and the nona oxide film is removed by etching with dilute hydrofluoric acid. In this way, the STI 12 that defines the active region AR is formed. The suffix after the number is used to distinguish each part, and when omitting the suffix, it indicates the whole. An n-well NW is formed by ion implantation using a resist mask. In the logic area, n-well and p-well are formed.

As shown in FIG. 2B, the surface of the active region AR is thermally oxidized to form a buffer oxide film 13.

This buffer oxide film protects the surface of the substrate silicon when the polycrystalline silicon film formed thereon is etched.

[0019] As shown in FIG. 2C, a photoresist film having a thickness of about 200 nm is applied, exposed and developed, and then subjected to STI. A photoresist pattern PR1 for etching is formed. If the width of the STI is 200 nm, for example, a stripe with a width of lOOnm is left in the center, and an aperture AP is formed that opens part of the active region beyond the edge of the STI region to be etched.

FIG. 2D shows an example of a planar shape of the opening pattern AP. The active region AR has a shape with a wide end, and the opening pattern AP is formed so as to surround the wide active region end. The STI insulating film exposed in the opening pattern AP is the etching target. Etch back the STI about 200nm deep by reactive etching. In reactive etching, for example, C4F8 / Ar / 02 is used as an etchant gas for silicon oxide, and CHF3 / Ar / 02 is used as an etchant gas for silicon nitride.

[0021] Note that in order to provide a function of an element isolation region, it is preferable that the remaining film thickness of STI remaining after removing a part of STI is lOnm or more. Further, in order to increase the area of the capacitor electrode to be formed, it is preferable to etch 3/5 (= 0.6) or more of the thickness of the STI (residual film thickness 2/5 or less). The 200 nm deep capacitor trench described above is 2/3 (= 0.67) of the 300 nm thick STI.

[0022] As shown in FIG. 2B, isolated capacitor trenches CT1 and CT2 are formed. The sidewall of the capacitor trench CT consists of an exposed silicon substrate (n-type wall NW) and a STI-carrying insulating film 12c remaining at the center and bottom. It is preferable to etch the side wall of the buried insulating film 12c under the condition of tilting. Referring to the plan view of FIG. 2D, the region between the outer periphery of the active region AR and the outer periphery of the aperture AP is etched back to form a capacitor trench.

As shown in FIG. 2F, a polycrystalline silicon film 15 is deposited to a thickness of about 20 nm by CVD using SiH 4 and H 2 gas at a substrate temperature of about 600 ° C. Add p-type impurity B at the same time as deposition, or perform ion implantation of B after deposition to impart conductivity. This polycrystalline silicon film 15 constitutes the storage electrode of the capacitor. The bottom surface of the capacitor trench CT, which is just the active region side surface, and the STI side surface can also be used as the capacitor area. However, in this state, the polycrystalline silicon film 15 in the capacitor trench CT1 and the polycrystalline silicon film 15 in another capacitor trench CT2 are electrically continuous.

As shown in FIG. 2G, a photoresist covering the capacitor region is formed on the polycrystalline silicon film 15. Forms pattern PR2. An opening is formed on the STI buried insulating film 12c remaining in the center, and also opens outside the capacitor region. The polycrystalline silicon film 15 is reactively etched using the photoresist pattern PR2 as a mask. Each capacitor storage electrode is isolated. Etchant gas for polycrystalline silicon having selectivity for silicon oxide film is, for example,

, C12ZHBrZ ○ 2. The surface of the active region not covered with the photoresist pattern PR2 is protected by the buffer oxide film 13 for etching power. After the etching of the polycrystalline silicon film 15, the photoresist mask PR2 is removed, and the buffer oxide film 13 is removed with, for example, dilute hydrofluoric acid.

FIG. 2H shows a state where the buffer oxide film 13 is also removed and a clean silicon surface is exposed. The polycrystalline silicon films 15x and 15y formed in the capacitor trench CT cover both sides and the bottom of the trench and are separated from each other. In the logic circuit region, the surface of the active region defined by STI is exposed.

As shown in FIG. 21, dry thermal oxidation is performed in, for example, 900 ° C. dry 02 to consume about 4 / m of the silicon surface and grow a thermal oxide film 16. The active area of the logic circuit area is also shown on the left side of the figure. By this thermal oxidation, a gate oxide film 16g is formed on the surface of the active region, and the exposed surface of the polycrystalline silicon film 15 is also thermally oxidized to form a silicon oxide film 16c constituting a capacitor dielectric film.

As shown in FIG. 2J, a polycrystalline silicon film 17 is deposited on the silicon oxide film 16 to a thickness of about 120 nm by CVD using SiH 4 and H 2 gas at a substrate temperature of about 600 ° C. This polycrystalline silicon film forms the gate electrode of the transistor and the counter electrode of the capacitor.

[0028] As shown in FIG. 2K, a photoresist pattern PR3 for the gate electrode of the transistor and the counter electrode of the capacitor is formed on the polycrystalline silicon film 17. The width (gate length) of the gate electrode is 50 nm, for example. The polycrystalline silicon film 17 is reactively etched using the photoresist pattern PR3 as a mask. C12 / HBr / ○ 2 is used as the etching gas. Here, the etching is performed so as to stop at the gate oxide film 16g.

Thereafter, the photoresist pattern PR3 is removed.

[0029] As shown in FIG. 2L, both sides of the gate electrode 17g (and the counter electrode 17c) of the polycrystalline silicon film The extension region 21 is formed by ion-implanting a low concentration of p-type impurity B into the n-type wall NW at an acceleration energy of 3 keV and a dose of 5 X 1014 cm_2 (hereinafter expressed as 5E14). The gate electrode 17g and the counter electrode 17c are also doped with p-type impurities.

[0030] As shown in FIG. 2M, a silicon oxide film is deposited on the semiconductor substrate to a thickness of about 10 nm CV D, and etched back by reactive etching to form the gate electrode 17g and the capacitor C on the sidewalls. Form side wall spacer SW.

As shown in FIG. 2N, using the sidewall spacer SW as a mask, p-type impurity B is ion-implanted at an acceleration energy of 10 keV and a dose of 3E15 to form a high concentration source / drain region 22. The gate electrode 17g and the counter electrode 17c are also heavily doped with p-type impurities.

As shown in FIG. 20, a silicon oxide film 23 is formed on the substrate by CVD with a thickness of about 20 nm. This oxide film serves as a mask for the silicide process. On the silicon oxide film 23, a photoresist pattern PR4 having a shape covering the region for preventing the silicidation reaction is formed. Photoresist pattern PR4 covers the access transistor. Reactive etching of the silicon oxide film 23 is performed using C4F8 / Ar / ○ 2 as an etching gas and the photoresist pattern PR4 as a mask. The silicon oxide film is removed from the counter electrode in the logic transistor region and the memory region. Thereafter, the photoresist pattern PR4 is removed. Logic transistor source Z drain region, gate electrode and capacitor counter electrode form a silicide layer to reduce resistance. Capacitor storage region can degrade retention characteristics due to silicide reaction. This is because it is preferable not to form silicide.

[0033] As shown in FIG. 2P, the sidewall spacers SW on both sides of the counter electrode 17g of the capacitor are covered with a mask and are not etched, so that they remain protruding from the counter electrode 17g of polycrystalline silicon. After depositing a Co film on the substrate surface by sputtering and performing a primary silicidation reaction at a low temperature, wash out the unreacted Co film with sulfuric acid / hydrogen peroxide solution and perform a secondary silicide reaction at 850 ° C. Thus, a low resistance silicide film is formed. A CoSi layer 26 having a thickness of 50 nm is formed on the source Z drain region of the logic transistor, the gate electrode, and the counter electrode of the capacitor. [0034] The figure also shows the n-channel transistor in the p-well PW in the logic circuit area at the left end. In an n-channel transistor, the conductivity type of the channel (well), the gate electrode 16g, the extension 23, and the source Z drain region 24 is opposite to that of the corresponding part of the p-channel transistor. In ion implantation, ions are separated by a photoresist mask and implanted in a separate process.

In this manner, a DRAM cell is formed simultaneously with the formation of the logic transistor. The steps added to form the DRAM cell include buffer oxide film formation in FIG. 2B, STI partial etching in FIGS. 2C and 2E, polycrystalline silicon deposition in FIG. 2F, and polycrystalline silicon films in FIGS. 2G and 2H ( And buffer oxide film). These processes use similar processes in the production of logic transistors and can be performed with high reliability. Since the capacitor is formed using almost all the inner surface of the recess formed in STI, the area of the capacitor can be increased.

[0036] Although the case where a silicon oxide film is used as the gate insulating film and the capacitor dielectric film has been described, a silicon oxynitride film, a silicon nitride film, a high dielectric constant insulating film, a high dielectric constant insulating film into which nitrogen is introduced A stacked layer of a silicon oxide film or the like can also be used. As explained with reference to Fig. 1A, the source region of the two access transistors can be shared, and memory capacitors can be formed on both sides. Various known MOS transistor configurations can be used.

[0037] In the above-described embodiment, partial etching of STI was performed using an etching mask having an opening including a part of the active region from STI. The capacitor's storage electrode is also in contact with the side of the active region and forms a pn junction capacitance. However, the impurity concentration in the active region is low and the pn junction capacitance is small. A pn junction can cause leakage.

[0038] FIGS. 3A and 3B show another embodiment in which a recess is formed only in the internal space of the STI to form a capacitor. FIG. 3A is a plan view showing an active region AR and an opening AP of an STI etching mask, and FIG. 3B is a cross-sectional view showing a state in which a storage electrode is formed after partial etching of STI corresponding to FIG. 2H.

[0039] As shown in FIG. 3A, the shape of the active region AR is a simple rectangle. The mask opening AR is separated for each capacitor on the STI, and it is necessary to increase the area of the recess side surface. Have a shape. Instead of the loop, a lattice shape may be used. The active area AR is separated from the outer periphery of the aperture AP.

FIG. 3B is a cross-sectional view of one capacitor. A recess on the loop is formed in the STI region, and a polycrystalline silicon film 15x is formed on the inner surface. The polycrystalline silicon film 15x between the recesses shows a removed form, but may be continuously removed as long as it is in a single capacitor. As shown in Figure 2G, the capacitors need to be separated. The polycrystalline silicon film 15 extends from the recess to the adjacent active region. It is preferable that the extension 21 enters the lower portion of the polycrystalline silicon film 15x and reaches the STI. Polycrystalline silicon film 15x is not in direct contact with n-well NW. This is advantageous when the polycrystalline silicon film 15 is doped at a high concentration.

In the present embodiment, the STI etching can be performed by etching only silicon oxide. The silicon nitride film liner 12η shown in FIG. 2A can also be used as an etch stopper. It may be possible to prevent the mobility from being lowered by the tensile stress of the silicon nitride film. The planar shape of the recess constituting the capacitor can be variously selected.

FIG. 3C is a modification of the planar shape of the recess. Recess R1 and Recess R2 are interdigitated. Although a shape with two comb teeth is shown, the number of comb teeth can be changed arbitrarily.

[0043] Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. For example, various known structures can be adopted as the structure of the logic transistor. The illustrated materials and numerical values are not restrictive. It will be apparent to those skilled in the art that various other changes, modifications, and combinations can be made.

Claims

The scope of the claims

[1] a semiconductor substrate having a logic region and a memory region;

An element isolation insulating film for filling the shallow trench;

A capacitor trench formed by removing a partial depth of the element isolation insulating film in the memory region;

A capacitor dielectric film formed on the capacitor storage electrode;

A capacitor counter electrode formed on the capacitor dielectric film and constituting a memory capacitor facing the capacitor storage electrode;

A logic transistor formed in an active region of the logic region;

2. The semiconductor device according to claim 1, wherein the access transistor, the gate electrode of the logic transistor, and the capacitor counter electrode are formed using the same polycrystalline semiconductor layer.

[3] The semiconductor device according to [1], wherein the capacitor trench force S is formed along a periphery of the shallow trench.

4. The semiconductor device according to claim 1, wherein a remaining film thickness of the element isolation insulating film under the capacitor trench is in a range of 10 nm to 2/5 of the depth of the shallow trench.

5. The semiconductor device according to claim 1, wherein the capacitor trench exposes a side surface of the adjacent active region.

[6] The adjacent active region has a wide region that has entered the element isolation region. Item 6. A semiconductor device according to Item 5.

7. The semiconductor device according to claim 6, wherein the capacitor trench has a planar shape surrounding the wide region.

8. The semiconductor device according to claim 1, wherein the capacitor trench is formed away from a side wall of the shallow wrench via a part of the element isolation insulating film.

9. The semiconductor device according to claim 8, wherein, in the planar arrangement of the capacitor trench force, the capacitor has a side that is separated from a peripheral edge of the shallow trench.

[10] The plurality of active regions of the memory region have two active regions opposed to each other across the shallow trench, and the capacitor trench is formed corresponding to each of the two active regions. 2. The semiconductor device according to claim 1, wherein the two capacitor trenches formed are separated at a portion where the element isolation insulating film is not removed.

11. The semiconductor device according to claim 10, wherein the capacitor storage electrode is separated for each memory capacitor, and the capacitor counter electrode is common to a plurality of memory capacitors.

12. The semiconductor device according to claim 10, wherein the capacitor storage electrode is formed of a polycrystalline semiconductor having a conductivity type opposite to that of the adjacent active region.

13. The semiconductor device according to claim 1, further comprising a silicide layer formed on the capacitor counter electrode.

[14] (a) A shallow trench isolation is formed in a semiconductor substrate having a logic region and a memory region, a plurality of first conductivity type active regions are formed in the memory region, and a plurality of the first regions are respectively formed in the logic region. Defining an active region of a first conductivity type and a second conductivity type that is a reverse conductivity type; and

(b) etching a part of the depth of the shallow trench isolation in the memory region to form a capacitor trench;

(c) forming a capacitor storage electrode extending from an inner surface of the capacitor trench to an adjacent active region;

(d) forming an insulating film on the surface of the active region and the capacitor storage electrode;

(e) forming an electrode layer covering the insulating film; (f) patterning the electrode layer to form a gate electrode of the transistor and a counter electrode of the capacitor;

(g) The first conductive type active region is doped with the second conductive type impurity through the patterned electrode layer, and the memory region is electrically connected to a lower surface of the storage electrode extending on the active region. Connecting, and

A method of manufacturing a semiconductor device including:

15. The method for manufacturing a semiconductor device according to claim 14, wherein the step (b) leaves the element isolation insulating film in a range of 10 nm to 2/5 of the depth of the shallow trench under the capacitor trench.

[16] In the step (a), two active regions facing each other across the shallow trench are formed in the memory region, and the step (b) corresponds to each of the two active regions, 15. The method of manufacturing a semiconductor device according to claim 14, wherein two capacitor trenches are formed that are separated at a portion where the element isolation insulating film is not removed.

[17] The step (c) force S, forming a capacitor storage electrode separated for each memory capacitor

15. The method of manufacturing a semiconductor device according to claim 14, wherein the step (f) forms a capacitor counter electrode common to a plurality of memory capacitors.

18. The method for manufacturing a semiconductor device according to claim 17, wherein the step (c) forms a capacitor storage electrode formed of a polycrystalline semiconductor having the second conductivity type.

[19] (h) forming a sidewall spacer on the side wall of the patterned electrode layer;

(i) doping the second conductivity type impurity using the sidewall spacer as a mask;

15. The method for manufacturing a semiconductor device according to claim 14, further comprising:

[20] (h) a step of forming a silicide layer on the source / drain region and gate electrode of the logic transistor and the capacitor counter electrode;

20. The method for manufacturing a semiconductor device according to claim 19, further comprising: