WO2007027186A1

WO2007027186A1 - A high brightness light emitting diode and method of making same

Info

Publication number: WO2007027186A1
Application number: PCT/US2005/032526
Authority: WO
Inventors: Richard Kulkaski; Robert William Allison, Jr.; Sergei Yur'evich Shapoval; Michael William Powell
Original assignee: M.E.C. Technology, Inc.
Priority date: 2005-08-31
Filing date: 2005-09-12
Publication date: 2007-03-08

Abstract

A semiconductor device and a method of forming the semiconductor device. The semiconductor device may include a substrate 110; an n-layer 130; a buffer 120 formed between the substrate and the n-layer; an active heterostructure 150 including a plurality of quantum wells and being proximate to the n-layer; and a p-layer 160 proximate to the active heterostructure. The buffer, n-layer, active heterostructure, and p-layer may sequentially form a mesa-shaped structure. The method may include the steps of pre-cleaning a substrate; sequentially forming an n-layer, an active layer, and a p-layer on the substrate; depositing a mirror atop the p-layer; etching a mesa profile of sequentially decreasing width for the n-layer, the active layer, the p-layer, and the mirror; and depositing side mirrors 190 along sides of the mesa profile.

Description

A HIGH BRIGHTNESS LIGHT EMITTING DIODE AND METHOD OP MAKING SAME

Cross-Reference to Related Applications

[1] This application is related to U.S. Provisional Patent Application Serial No. 60/606,165, filed on August 31, 2004, the entire disclosure of which is incorporated by reference as if set forth in its entirety herein.

Field of the Invention

[2] The present invention relates generally to illumination, and particularly to light emitting diodes exhibiting high and enhanced brightness.

Background of the Invention

[3] The use of LEDs for lighting applications has, to date, been relatively limited. LEDs used for industrial or residential lighting need to 005/032526

exhibit high brightness. Further, in order for the lighting industry to move to the use of LEDs, other advantages must be evident due to the use of LEDs rather than typical fluorescent lighting. It has been estimated that an increase in the use of LED lighting could result in an energy savings to consumers of 100 TW hours per year, and a cost savings of as much as $10 Billion per year.

[4] Typical commercial high brightness light emitting diodes (HBLEDs) generally have structures wherein a thin emitting layer is sandwiched between n- and p-GaN layers . Typically, these sandwiching layers employ Si and Mg for the n-type and p- type doping, respectively. In many cases, the emitting layers are single or multiple quantum wells of InGaN or AlInGaN alloys. Electrical contact may be made to the active layer by metal contacts. Often, a thin, partially transparent metal layer is used to spread the current for the HBLED. In many cases, TiAl may be used for the n-contact and NiAu may be used for the p-contact of the typical commercial HBLED. A buffer layer may be used for matching to a sapphire substrate of the HBLED. Such a HBLED may produce a light emission through the transparent substrate with a 90^p cone angle. Further, standard HBLEDs often are mounted in a flip chip mount, in order to allow improved access to the emitted light. Currently, typical commercial HBLEDs have achieved color rendering of approximately 80, efficacy in the range of approximately 60 to 80 lumens per Watt, and a lifetime in the range of about 4000 hours.

[5] As is known to those possessing an ordinary skill in the pertinent arts, the use of InGaN in an HBLED, such as in the commercial HBLED discussed hereinabove, may present a "red barrier" that develops due to an inability to sufficiently control the solubility ot Indium, in order to form a high intensity red diode using the nitride system. This red barrier exists as a result of the imtniscibility of Indium at stoichiometries greater than 40% and difficulties in the deposition process associated with the creation of the InGaN and AlInGaN emitting layers. Alternatively, and in frequent use in more current HBLED devices, complementary blue HBLED array systems have been developed that necessitate the use of phosphors, in part, to properly blend colored LEDs by avoiding the use of In. With these devices the red problem inherent in an InGaN RGB additive system is avoided.

[6] Because of these and other difficulties associated with the production of blue HBLEDs, the typical commercial HBLED manufacturers have begun to seek alternatives to typical commercial HBLED arrays. In fact, a switching has recently been evidenced from Indium to phosphors , in large part because indium has insufficient solubility and manufacturing characteristics to allow for necessary control of the red content in light emitted, as discussed hereinabove. The blue-phosphor white HBLED has extended the commercial use of HBLEDs, but they have been found limited to a color rendering index of 80 or less and an efficacy of from 60 to 80 lumens per Watt .

[7] Thus, a need exists for an HBLED capable of generating white light for residential and commercial purposes, wherein the light generated presents a color rendering of greater than 80, and most preferably greater than 90, an efficacy of over 100 1/w, and most preferably over 150 1/w, and a lifetime greater than or equal to about 20,000 hours.

Summary of the Invention

[8] The present invention includes a semiconductor device. The semiconductor device may include a substrate; an n-layer; a buffer formed between the substrate and the n-layer; an active heterostructure including a plurality of quantum wells and being proximate to the n-layer; and a p-layer proximate to the active heterostructure. The buffer, n-layer, active heterostructure, and p-layer may sequentially form a mesa-shaped structure .

[9] The active heterostructure may include an active layer, and at least two polarization layers that sandwich the active layer. The substrate may be formed of SiC, and may be optically transparent. Thereby, upon generation of photons from the plurality of quantum wells in said active heterostructure, photons may be emitted and pass through the substantially optically transparent substrate .

[10] The p-layer of the mesa structure may have acceptor concentrations greater than 10¹⁷. The p-layer, the n-layer, and the active heterostructure may include minimized hydrogen content, and may include thermal disorder correctives.

[11] The present invention may additionally include a method of forming a semiconductor device . The method may include the steps of pre-cleaning a substrate; sequentially forming an n-layer, an active layer, and a p-layer on the substrate; depositing a mirror atop the p-layer; etching a mesa profile of sequentially decreasing width for the n-layer, the active layer, the p-layer, and the mirror; and depositing side mirrors along sides of the mesa profile. The method may further include forming a nucleated buffer layer between the substrate and the n-layer, depositing electrical contacts, testing and grouping the semiconductor device, and mounting the semiconductor device in a matrix with other ones of the semiconductor device .

[12] The sequential forming of an n-layer, an active layer, and a p-layer on the substrate may include adding dopants such as Silicon or Magnesium to increase conductivity or otherwise modify the layer properties to enhance performance of the device. These materials may be added actively during layer formation or inactively through the use of ion or plasma ion implantation using technologies that are known to those possessing an ordinary skill in the pertinent arts .

[13] The sequential forming may include sequentially forming via a plasma enhanced cyclotron resonance deposition. The ECR deposition may occur at 800 Celsius. Further, the etching may include etching via an enhanced cyclotron resonance etch.

[14] Thereby, the present invention provides an HBLED capable of generating white light for residential and commercial purposes, wherein the light generated presents a color rendering of greater than 80, an efficacy of over 100 1/w, and a lifetime greater than or equal to about 20,000 hours. Brief Description of the Figures

[15] Understanding of the present invention will be facilitated by consideration of the following detailed description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which like numerals refer to like parts and in which:

[16] Figure 1 illustrates a block diagram of the device according to an aspect of the present invention;

[17] Figure 2 illustrates an embodiment of the device of Figure 1 wherein the negativity of the dielectric enclosure may be adjusted;

[18] Figure 3 is an illustration of an apparatus for RGB color mixing and beam shaping for the device of Figure 1; [19] Figure 4 is a block diagram of a method for making the device of Figure 1; and

[20] Figure 5 is a diagram of a plasma enhanced depositor for formation of the stack layers of device of Figure 1.

Detailed Description, of the Invention

[21] It is to be understood that the figures and descriptions of the present invention have been simplified to illustrate elements that are relevant for a clear understanding of the present invention, while eliminating, for the purpose of clarity, many other elements found in typical photonic components and methods of manufacturing the same. Those of ordinary skill in the art will recognize that other elements and/or steps are desirable and/or required in implementing the present invention. However, because such elements and steps are well known in the art, and because they do not facilitate a better understanding of the present invention, a discussion of such elements and steps is not provided herein. The disclosure herein is directed to all such variations and modifications to such elements and methods known to those skilled in the art.

[22] In order to clarify the discussion herein, the present invention will be explained with reference to certain of the several terms set forth hereinafter. Defining lamp characteristics is based, in part, on this terminology indicative of defined and measurable lamp characteristics. Lamp characteristics are parameters used for measuring and comparing light sources, and such terms descriptive of lamp characteristics include lumen output, lumen maintenance, lifetime, efficacy, efficiency, color rendering index, color temperature, and cost.

[23] Lumen output is a measure of the amount of visible light output by a light source. Lumen 005/032526

maintenance is a measure of how a lamp output changes with age or other effects . Lifetime is generally the number of hours allowed for half of a set of similar lamps to burn out, such as an average burn out time across a family of lamps. Alternatively, lifetime may be the amount of time it generally takes for the lumen output of a light source to decrease to a percentage of its initial value, such as 50% or 70%, for example. Efficacy is defined as the conversion efficiency from optical power to luminous flux. It is expressed as the ratio of luminous flux and the light source optical power. Efficiency is defined as the conversion efficiency of the optical power to the diode drive power. It is expressed as the ratio of the luminous flux to the diode drive power. Color rendering index (GRI) refers to the perceived color appearance of an object when illuminated by a lamp as compared to the same object when illuminated by a reference light source. Color temperature (CT or CCT) is a 5 032526

measure of the color of the light output from a

lamp and is often designated in ⁰K.

[24] The use of other technologies, such as technology applicable to wide-band-gap semiconductors, may allow for an improvement in these lighting characteristics. Wide-band-gap semiconductors, particularly those using GaN and SiC, are in development to provide superior microwave and high electrical strength devices, and thermal conductivity compared to more traditional semiconductors . Advances applicable to wide band-gap semiconductors can be utilized to provide significant benefits at both the device and systems level, particularly with regard to the present invention in HBLED applications .

[25] More particularly, the development of wide-band- gap semiconductors, particularly using SiC and GaN, has necessitated the development of improved thin-film device technology. In principle, these improved thin-film materials 5 032526

offer not only a higher breakdown voltage, but also an improved thermal conductivity and electron saturation velocity. Such devices also have an ability to operate at higher junction temperatures because of the low intrinsic carrier concentration associated with a wide band-gap. Further, these improved films provide better process results with regard to, for example, dopant solubility, such as In solubility.

[26] Referring now to Figure 1, there is shown a block diagram of a device 100 according to an aspect of the present invention. As may be seen in Figure 1, device 100 may include a substrate 110, a buffer layer 120, an n-contact layer 130, an active layer 150, a p-layer 160, polarization layers 140 and 145, a contact 180, with a mirror 185 on its bottom side, a side polarizing layer 190, reflective multilayer 191, and a n-type ring contact 170. According to an aspect of the present invention, device 100, and the layers 26

thereof , may take any device shape capable of formation on substrate 110, including, but not limited to, the shape of a rectangle, a hemisphere, a pyramid or a mesa of layers stacked with sequentially varying size substantially one upon, or one aside, the other. For example, substrate 110 may form the base of a mesa stack with sequential layers built substantially thereon. Substantially adjacent to substrate 110 may be n-contact layer 130 with n-contact 170, and buffer 120 may be sandwiched substantially there between. Substantially adjacent to n-contact layer 130 and distal to substrate 110 may be active layer 150, and polarization layer 140 may be sandwiched substantially there between. Substantially adjacent to active layer 150 and distal to n- contact layer 130 may be p-layer 160, and polarization layer 145 may be sandwiched substantially there between, p-contact 180 with mirror 185, may be on top of layer 160 and polarizing layer 190 and reflective multilayer. 191 may deposited on the mesa stack sides.

[27] Substrate 110 may take the form of SiC, AlN or any other suitable material for use as a semiconductor substrate known to those possessing an ordinary skill in the pertinent arts . According to an aspect of the present invention, substrate 110 may have a minimized thickness, such as a thickness of approximately 300 microns, or less if suitable heat removal properties are achieved. Specifically, substrate 110 may be made from material having, and may be designed to have, a high thermal capacity. According to an aspect of the present invention, substrate 110 may be designed to remove heat on the order of 14-20 W/cm².

[28] According to an aspect of the present invention, substrate 110 may substantially lack defects, and may preferably be a high quality material . More specifically, substrate 110 may be a low defect substrate, such as, for example, a 4H SI substrate. As may be understood by those possessing an ordinary skill in the pertinent arts, a wafer approximately 1/16 inch thick may be thinned by grinding, polishing and/or electro-etching to the desired thickness and shape to provide substrate 110.

[29] The substrate may, in an embodiment, be optically transparent or substantially optically transparent. Thereby, photons emitted from the junctions within the stack may be optically emitted via the substrate 110. The emission of photons through the substrate causes the generation of light via the present invention. As per the discussion immediately hereinabove, the thickness of substrate 110 may be further decreased to provide a decrease in ohmic and thermal resistivity while providing an increase in the transparency, to better allow for light propagation.

[30] Buffer 120, or nucleation layer 120, may be formed substantially adjacent to substrate 110. Buffer 120 may take the form of AlN or alternating stacks of Aln/AlGaN or may have dopants such as Si incorporated or any other suitable material (s) designed to minimize lattice mismatch between substrate 110 and n- layer 130. Buffer 120 may have a thickness in a broad range, such as in the range of 20 to 40 angstroms, and more specifically such as 30 angstroms, for example. Buffer 120 may be optimized to decrease the heat and to increase transparency to the light generated. Preferably, the buffer layer may be nucleated in order to improve the capability to reduce the lattice mismatch between the SiC substrate and the n-GaN layer.

[31] The n-layer 130, also referred to as the electrical conductor layer, may be composed of an n-doped layer, such as an n-doped GaN layer. The n-layer 130 may be doped using silicon, for example. This layer may have a thickness in a broad range, such as in the range of 0.3 to 3 26

microns, and more specifically such as 1000 ran, for example. As will be apparent to those skilled in the art, the n-layer conductivity is typically optimized by increasing metallic content. However, as metallic content increases, transparency decreases, and, as such, the n-layer of the present invention is typically not optimized using an increased metallic content.

[32] Active layer 150 creates quantum wells suitable for light, and more specifically photon, generation. For example, InGaN and AlInGaN may be used with InN and GaN, respectively, for quantum wells having AlN wells. In such a configuration, the In levels may be adjusted to affect the color of the light emitting diode. In such a scenario, a lower stoichiometry, that is, less In, may produce a diode with more blue colorization, while a higher stoichiometry, that is, more In may produce more red colorization. [33] The active layer may be grown using a pulsed ECR epi-growth, as is further discussed herein below. Active layer 150 may be of minimal thickness, to allow improved alloy formation. Such improved alloy formation may result in more efficient quantum wells. Additional active layers may be deposited to increase the number of quantum wells which, in turn, may increase the device emission.

[34] The p-layer 160 may be formed from a positively doped material, such as heavily doped p-GaN. The p-layer 160 may be doped with any of a variety of materials which may increase the p- layer conductivity, such as magnesium, for example. Layer 160 may be designed to have a broad range of thicknesses, such as a thickness of approximately 300 nm, for example. P-layer 160 may have acceptor concentrations greater than 10^X7, and may most preferably have acceptor concentrations of approximately equal to or greater than 10¹⁹. In order to improve the acceptor concentration, methods such as those discussed herein below with respect to Figure 3 may be employed.

[35] Polarization layers 140 and 145 may be substantially identical or may have differing characteristics depending on the particular

}^■ design of device 100. Layers 140 and 145 may, for example, be formed from Al_xGaNi__x/GaN. The constituents of the polarization layers may be manipulated to adjust the strain level in* the polarization layer, such as by changing the stoichiometry of the Al. Via this manipulability, the polarization layers provide a tunable strain adjustment that is suitable for improving the function of the active layer. The requirements of polarization layers 140 and 145 may include high light transmission and high uniformity.

[36] In another embodiment, polarization layers 140 and 145 may be arranged to form a dielectric enclosure with polarization layer 190. Such a 2005/032526

formed enclosure may surround the active layer 160 and may exert a negative influence on the two-dimensional electron gas (2DEG) thereby increasing the gas lifetime and density which may further increase the quantum well efficiency and emission lifetime.

[37] Figure 2 shows an embodiment of device 100 where the negativity of the dielectric enclosure may be adjusted to allow optimization and adjustment of the 2DEG intensity and lifetime. This adjustment may also minimize the 2DEG interactions which deplete the wall area, reduce pn junction leakage, increase the diode breakdown voltage and smooth the 2DEG radial current density thereby increasing the diode efficiency.

[38] In Figure 3 the dielectric box may be formed by the two polarization layers 140 and 145, the MESA polarization layer and side mirror 190 and 195 with the active layer 150 in the box interior. A metallic electrode 530 may be deposited on the MESA sidewalls 190, 195 and an external contact 540 may be deposited on the metallic layer . The sloped stack including the contact 540, metallic layer 530 and the sloped MESA sidewalls 190 and 195 may act as a capacitor connected to the 2DEG that may excite the active layer 150 light emission. Application of a negative dc voltage to contact 540 may charge the capacitor thereby adding an additional negative effect to the dielectric box. Such a negative effect may increase the negativity due to the strain polarization of the layers which form the dielectric box. Such a change in negativity may change the negativity effect on the active layer to thereby increase the intensity of the 2DEG. Furthermore, the applied bias voltage may be varied allowing both optimization and intensity variation of the 2DEG. In addition to increasing the diode emission intensity, the diode absorbed power may also be reduced. [39] The metallic layer 530 may be made of Ti/Al, Ti/Pd or a similar alloy. The metal layer 530 may also act as a reflective mirror replacing, or supplementing, mirror 191. The dielectric film may be Si3K4 of thickness 100 - 4000 Angstroms .

[40] The characteristics discussed hereinabove, and the constituents of each layer discussed hereinabove are, and are intended as, exemplary embodiments. Further, in certain embodiments, each layer discussed hereinabove as being resident within the stack may be designed and created substantially without, or with minimization of, the use of hydrogen. The minimization of hydrogen in the processes, formation, and structure of the present invention serves to prevent the generation of loose bonding electrons that may degrade characteristics and performance of a device in accordance with the present invention. For example, such loose hydrogen bonds may degrade US2005/032526

the light emission or diode efficiency. Additionally, each layer of the stack may, for example, be designed to minimize or correct thermal disorder.

[41] The stack discussed herein may be enhanced by the use of beam forming or micro-optics, either or both throughout the layers of the stack, or at the point of the stack from which photons are emitted. Such optics may take the form of a mirror 185 which may be formed as part of the p- contact 180 and the flat interface of p-layer 160. A multilayer sidewall film 190 may form a Bragg reflector, which may be formed of Si₃N₄ and other compatible materials such as zinc sulphide or magnesium fluoride, for example, and may form the outer boundaries of the device, particularly wherein the device takes the shape of a mesa- Further, in embodiments with or without such, side mirrors, thin films may be resident on the sides of the device, and such thin films may increase negative influence on the sides of a mesa-type device. According to an aspect of the_> present invention, the outer layers may form a Bragg reflector to thereby eliminate mesa sidewall light leakage. Eliminating such leakage may increase the amount of light leaving the substrate . The innermost nitride inner layer may have a negative influence to increase the lifetime and density of the 2-dimensional electron gas in the diode. Such an increase in negative influence positively affects carrier depletion effects in the device. Additionally, Fresnel and/or fly' s eye lenses may be used at the output of device 100. Such lenses may be aligned optically adjacent to substrate 110.

[42] For example, a mirror, or set of mirrors including rear and side mirrors, may be used to increase the intensity of the emitted light and prevent losses. As is known to those possessing an ordinary skill in the pertinent arts, a Bragg mirror is a periodical structure made up of two semiconductor or dielectric materials having

26 005/032526

different refractive indices. The thickness of layers may be chosen so that the light reflected by all the interfaces interferes negatively within a spectral range referred to as the "stop-band." In high-quality structures, reflectivity of Bragg mirrors within the stop- band exceeds 99%.

[43] Mirrors may thus be used to reduce these losses, as discussed hereinabove. For example, Bragg mirrors may be placed around the sides, or sidewalls, of device 100 and may be designed to act as a mirror and an electromagnetic reflection boundary. Such mirrors and reflectors may account for an increase in the quantum efficiency of device 100 from 15% to near 70%. Such mirrors or reflectors along the side of the device may include, for example, edge-correction capabilities, such as those discussed further herein below.

[44] According to an aspect of the present invention, the mirrors that may bound the top and sidewalls 26

of the device stack of the present invention may be formed by the ration of the layer indices of refraction, as would be evident to those possessing an ordinary skill in the pertinent arts, and also by smoothing the layer interface. Thus, optics may be used to improve the efficiency of the present device. Further, external optics may be used to direct and manipulate the light output from the substrate of device 100.

[45] Interconnections for device 100 that provide maximum efficiency in the transference of electrical stimulus to light generation are needed so that the HBLED may be driven efficiently with as much power as is practicable. As may be evident to those possessing an ordinary skill in the pertinent arts, driving a LED with increased power may cause overheating. According to an aspect of the present invention, improved interconnective contacts reduce the potential for overheating while allowing high power to be used to drive the device.

[46] A conductive transparent film may be placed on substrate 110 to make an n-contact. Such a contact may possess properties allowing for the minimization of the light loss associated with the placement of the film. For example, the shape of the film may be such that the effect on the output beam may be minimized. A film of this type would include, for example, a spider assembly. The effects of such a spider assembly may be readily manipulated by the downstream optics discussed hereinabove. As is known to those possessing an ordinary skill in the pertinent arts, spider assemblies are often used in optical systems to hold secondary mirrors in, for example, a telescope, and downstream optics are readily available to minimize the beam disturbance from such a configuration.

[47] According to an aspect of the present invention, ohmic contacts for n-type contacts may be based on TA/Al/Ni/Au. An embodiment for n-contact 170 may be an annular ring which may make ohmic contact on the outer radius of buffer layer 130. n-contact 170 may be 740 nm thick, 500 nm wide with layer thicknesses (20/20/100/600 nm) , ohmic contact for p-contact 180 may be based on Ni/Pd. p-contact 180 may be a thin disk of thickness 700 nm, diameter 300 nm with layer thicknesses (600/100 nm) . Mirror 185 may be formed on a Ta surface at the intersection of p-contact 185 and p-stack layer 180. Mirror 185 may be formed during p-contact formation resulting from a minimizing surface traps on the contact.

[48] Other features of the ohmic contacts according to the present invention include, but are not limited to, thermo-mechanical and chemical stability at temperatures up to 800 K, elimination of surface traps, prevention of minority carriers, and low contact resistance to stave off parasitic resistance. [49] A compound parabolic concentrator (CPC) may be. used to condense and homogenize the beam after the combination of single HBLEDs into an HBLED array with red-green-blue constituent parts. For example, for the provision of white light via an HBLED system in accordance with the present invention, red-green-blue (RGB) constituents are generally employed as HBLEDs .

[50] Referring now to Figure 3, there is shown an illustration of an apparatus for RGB color mixing and beam shaping for the device of Figure 1. According to an aspect of the present invention, device 200 may be used to additively RGB color mix multiple devices. As may be seen in Figure 3, device 200 may include a matrix assembly 210, a heat sink 211, printed circuit board 212, and a matrix of up to three HBLEDs in flip chip mounts 213, 214, 215 arranged as shown in Figure 3. Matrix assembly 210 may be optically matched and mounted on Compound Parabolic Concentrator input aperture 220. The CPC may include dielectric body 230 connected to input aperture 220, a shaped edge profile 240 forming the outer edge of dielectric body 230, a shaped optical edge 250 and an exit aperture 260, each aligned on the end of dielectric body 230 distal to the matrix assembly 210.

[51] According to an aspect of the present invention, device 200 may take any device shape capable of shaping of the device 100 output light beam and additively RGB color mixing multiple devices, including, but not limited to, the shape of a sphere, a hemisphere, a cone or a paraboloid of revolution. For example, the dielectric body material may have an isotropic index of refraction or a radial refractive index profile, or no dielectric material . The HBLED matrix may hold more or less HBLEDs and matrix 210 may be coupled to the CPC body with an optically shaped surface .

[52] According to an aspect of the present invention, matrix assembly 210 may have three of device 100 US2005/032526

mounted in a standard flip chip mount 213,214, 215 which may be mounted with each of device 100 emitting surface adjacent to the CPC input aperture 220. Flip chip mounts 213, 214, and 215 may connect the HBLEDs to the substrate pc board 212. In addition, flip chip mounts 213, 214, 215 may make thermal contact to PC board 212. PC board 212 may be thermally bonded to heat sink 211. Heat sink 211 may dissipate by convection or other means to ambient environment surrounding device 200 to cool the HBLEDs.

[53] According to an aspect of the present invention, flip chips 213, 214, 215 may be mounted radially as close to each neighbor as possible to thereby reduce color shadows in the RGB additive mixing within CPC body 230.

[54] Input aperture 220 may have a well that accepts matrix assembly 210. Matrix assembly 210 may be bonded to the input aperture 220 by filling the well with an optical epoxy, inserting matrix assembly 210 in to the well until pc board 212 2005/032526

touches the well edge of input aperture 220. According to an aspect of the present invention, an optical matching converter may be inserted between matrix assembly 210 and entrance aperture 220 during bonding.

[55] According to an aspect of the present invention, body 230 may be a dielectric material which may have an index of refraction of between 1.56 and 1.7 that may be transparent to light of wavelength 350 to 700 nm. Body 230 may have a compound edge profile beginning with a tilted axis paraboloid 240 that may be adjacent to edge profile 250. Paraboloid 240 may act as an angular transformer that matches the HBLED beam to the desired output beam of the complete system.

[56] A radial and/or longitudinal index of refraction may be produced in body 230. Such material modifications are well known to those experienced in the field. Such a variation may be linear or parabolic and may produce uniform RGB color mixing.

[57] The beam traversing the area within body 230 may pass into the shaped optical edge 250. This shaped optical edge may reflect back large angle rays while reducing the angle at which such rays strike exit aperture 260 which may produce a more intense light beam output. According to an aspect of the present invention, the profile of edge contour 250 may be conical, or curved such as radially or hyperbolically. The axial extent of edge profile 250 may be varied to optimize the light beam intensity and intensity distribution.

[58] Device 200 may have an input aperture of 25 mm, a body length of 39 to 55 mm and an exit aperture of 30 to 50 mm.

[59] Referring now to Figure 4, a method for fabricating a device as exemplified in Figure 1 is shown. As may be seen in Figure 4, method 300 may include process blocks for fabricating device 100. As may be seen in Figure 4 these steps may include forming the stack of device 301, implanting Mg ions through an energy filtering mask to form p-GaN 302,performing an RTP anneal to remove damage 303, depositing the metallic HBLED contact and mirror, etching device 100 to form MESA 305, deposit and delineate - n-contact 306, multi step deposition of device 100 side wall layers and mirrors 307, RTP contact anneal 308, dice individual die 309, measure die electroluminescence and separate while sorting die into RGB sets 310, mount die on RGB matrix 311, measure color and output of RGB die, integrate RGB matrix with external optics, perform final test. The process may include substrate pre-cleaning, die patterning, passification and other standard methods used by those of ordinary skill in the art.

[60] Forming stack 301 may include forming a device assembly by plasma assisted molecular beam epitaxy (PAMBE) , as is known to those possessing an ordinary skill in the pertinent arts, for growing the hetero-stack of device 100. Each cluster may contain a separate growth based on the color of device 100, such as red, green or blue, .for example. PAMBE formation of stack 301 may allow the use of lower temperatures in forming the InxGal-xN alloy active layer of device 100. PAMBE combined with atomic layer deposition may allow deposition with minimum Hydrogen and the use of atomic Nitrogen as the deposition source . Use of these techniques may allow maximum control of the active layer deposition of non-equilibrium layers which may allow the fabrication of high stoichiometry necessary to result in efficient red nitride HBLEDs, for example. Such a fabrication is pursuant to the advantages of using ECR, by an ECR sourced plasma enhanced molecular beam epitaxy unit. Such a unit may, for example, avoid the use of hydrogen by "cracking" N2 down to atomic nitrogen, N. The films deposited and etched in the present invention may be provided by such a unit in exemplary embodiments. Numerous difficulties may be remedied thereby. For example, without the use of plasma enhancement to deposit GaN, wafer processing may have to occur at about 1050 Celsius in order to provide a pressure sufficient to exceed the back pressure of N, which is approximately 760 mm. The use of an ECR process may help to overcome the high-temperature and high-pressure dependence, as well as the need for Hydrogen that could degrade device characteristics, by allowing for the use of Nitrogen instead of Hydrogen, by allowing for the use of an SiC substrate, and by providing improved film control and characteristics, such as by providing a buffer layer sufficiently thick so as to prevent layer mismatch from negatively affecting the emitting layer, and such as by providing a polarizing layer that focuses strain effects in the active layer. The ECR depositions of the present invention may be performed, for example, at 800 Celsius, which is a suitable temperature to work with InGaN.

[61] Etching the stack mesa 305, and contact surfaces 304, 306 may be performed using a low energy spread plasma etcher such as an Electron Cyclotron Resonance (ECR) Etcher. The ECR may produce a high density, low ion energy spread microwave plasma which when combined with an adjustable low frequency RF biased wafer may result in a non-vertical MESA sidewall. In addition, ECR etching may result in lower surface defects, forming low Schottky barrier contact interfaces to thereby make device 100 more power efficient.

[62] The step of covering MESA sidewalls with the Si3N4 polarizing layer and multi-layer Bragg mirror 307 may include an ECR deposition to form sequentially the layers that result in higher quality deposited films and more efficient side mirrors . [63] Forming the n-and p-contact and mirror 304, 306 may use a modified SC-I surface clean of the stack contact surfaces with a plasma surface treatment, which may minimize surface traps and interface damage to lower the contact resistance and "slump" . Subsequently, the n- and p- contact and mirror may be formed by high temperature sputtering or ion sputtering of the contact layers for device 100. After deposition each contact layer may undergo Rapid Thermal Annealing (RTP) to minimize surface defects and traps to thereby result in a high conductivity contact and a smooth p-contact to stack interface, which may form a reflective mirror, increasing the device 100 light output.

[64] Rapid Thermal Annealing 303, 308 may include a rapid thermal process to remove the effects of damage resulting from processing such as plasma and thermal radiation damage and defect annealing. By rapid thermal cycling, this radiation damage may be removed at lower average 005/032526

temperatures to avoid or minimize thermal effects to the non-equilibrium formed layers of device 100. Further, such thermal processing may diffuse the dopant ions throughout each of the n- and p- layers to result in a more efficient stack.

[65] Figure 5, shows a cross section of an ECR plasma enhanced MBE/VPE unit 400 for forming the stack of a device 100 as exemplified in Figure 1. Device 400 may be optimized for deposition of the non-equilibrium layers of device 100. As may be seen in Figure 5, only the ECR module 405 and the processing chamber 410 are shown. The remainder of unit 400 uses components and technology that are well known to those having ordinary skill in the art. Formation of non- equilibrium layers may require special chamber modifications which may help, for example, in the formation of uniform active layer crystal structures, elimination and control of Hydrogen during deposition, and in using atomic layer deposition in forming sub-layers within a layer. These modifications may minimize the growth and propagation of threading dislocations and other defects .

[66] Referring to Figure 5, it may be seen that ECR module 405 may be mounted on the major axis of processing chamber 410 perpendicular to the wafer target 413 to allow uniform plasma to impinge on target 413 and the reaction region.

[67] According to an aspect of the present invention, ECR 405 may be formed of the following components: ECR gas and the axial microwave power, with longitudinal antenna feed and ceramic window, ECR body with chemically resistant wall 407, ECR magnetic Helmholtz coils 408, plasma defining aperture 409. In this configuration the ECR module may produce, for example, nitrogen plasma at the source aperture which enters process chamber 410 striking target 413. The nitrogen beam may expand in the divergent magnetic field to uniformly cover target 413, which may be biased by an external RF power supply. Gas ring 412, which may be located above in close proximity to target 412, may provide the reactant gases for layer formation on the wafers mounted on target 413. Heater assembly 414, which may be enclosed in a boron nitride ceramic 415, may be mounted facing the underside of target 413. Target 412 with its wafers may be heated to the reaction temperature. The reaction region for layer formation may consist of gas ring 412, target 413, heater assembly 414, 415, and hemispherical heat shield 416. Heat shield 416 and cold nitrogen vanes 411 and 412 may provide isolation of the reaction region from the rest of the system. Such isolation may limit the deposition of layer material to the reaction area thereby increasing the deposition rate of the layer and providing faster and more sensitive control of the reaction parameters . The chamber walls may be heated to eliminate water vapor, and adduction reactions between the metal organic compounds such as, for example, tri-methyl Gallium and tri-methyl Indium, outside of the desired reaction area. The chamber pumping port may be placed on the chamber axis at the opposite pole of the chamber. This pumping port 417 may have an annular valve composed of two radial slotted plates that may allow adjustment of the chamber pumping speed. The use of this valve in conjunction with the precision pulsed atomic layer gas flow may control, and in conjunction with the ion source plasma density adjustment, may allow adjustment of the reaction residence time and the mean free path of the reactive components. This adjustment may allow for improved depositions .

[68] In reference to the description hereinabove it may be seen that the fabrication of more efficient stack layers for device 100 may require that the layer deposition unit have both an optimized plasma system and a properly constructed reaction region of limited extent. 5 032526

Such a reaction environment and plasma control combined with atomic layer deposition and the RF biased target may allow optimization of the deposition parameters and may result in an advance in HBLED efficiency and life.

[69] Those of ordinary skill in the art will recognize that many modifications and variations of the present invention may be implemented without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modification and variations of this invention provided they come within the scope of the appended claims and their equivalents .

Claims

What is claimed is:

1. A semiconductor device, comprising:

a substrate,-

a n-layer;

a buffer formed between said substrate anά said n-layer;

an active heterostructure including a plurality of quantum wells and having an upper side and a lower side, a right side and a left side, wherein the lower side of said active heterostructure is proximate to said n-layer; and

a p-layer proximate to the upper side of said active heterostructure;

wherein a distance from the right side to the left side is less than a first expanse across said n- layer, and greater than a second expanse across said p- layer .

2. The semiconductor device of claim 1, wherein said active heterostructure comprises:

an active layer; and

at least two polarization layers that sandwich said active layer.

3. The semiconductor device of claim 1 , wherein each layer from said substrate, said buffer layer, said n-layer, said active heterostructure, and said p-layer is successively and respectively wider than each successive respective layer.

4. The semiconductor device of claim 1, wherein said substrate comprises SiC.

5. The semiconductor device of claim 1, wherein said substrate has a thickness of approximately 500 microns .

6. The semiconductor device of claim 1, wherein said substrate has a high power density.

7. The semiconductor device of claim 1, wherein said substrate removes heat at approximately 14-20 W/cm².

8. The semiconductor device of claim 1, wherein said substrate substantially lacks defects.

9. The semiconductor device of claim 1, wherein said substrate comprises SiC and a 4 HC cut .

10. The semiconductor device of claim 1, wherein said substrate is substantially optically transparent.

11. The semiconductor device of claim 10, wherein, upon generation of photons from the plurality of quantum wells in said active heterostructure, the photons are emitted from the substantial optical transparency.

12. The semiconductor device of claim 1, wherein said buffer comprises AlN.

13. The semiconductor device of claim 1, wherein said buffer layer has a thickness in a range of 20 to 30 angstroms .

14. The semiconductor device of claim 1, wherein said buffer layer comprises a nucleated layer.

15. The semiconductor device of claim 1 , wherein said n-layer comprises an n-doped GaN layer.

16. The semiconductor device of claim 15, wherein the n-dopant comprises Si .

17. The semiconductor device of claim 1, wherein said n-layer comprises a thickness in a range of 0.3 to 3 microns .

18. The semiconductor device of claim 17, wherein the thickness comprises 300 nm.

19. The semiconductor device of claim 1, wherein said active heterostructure has a thickness of about a singe atom layer thickness .

20. The semiconductor device of claim 1, wherein said p-layer comprises heavily doped p-GaN.

21. The semiconductor device of claim 20, wherein the p-dopant comprises Mg.

22. The semiconductor device of claim 1, wherein said p-layer comprises a thickness in a range of about 300 nm.

23. The semiconductor device of claim 1, wherein said p-layer comprises acceptor concentrations greater than 10¹⁷.

24. The semiconductor device of claim 23 , wherein the acceptor concentrations are equal to or greater than

25. The semiconductor device of claim 2, wherein said polarization layers comprise substantially similar constituent characteristics.

26. The semiconductor device of claim 25, wherein said polarization layers comprise Al_xGaNi__x/GaN.

27. The semiconductor device of claim 25, wherein the constituent characteristics are tunable to adjust the strain level in the polarization layer.

28. The semiconductor device of claim 27, wherein the tuning comprises changing a stoichiometry of Al .

29. The semiconductor device of claim 27, wherein the tunability improves performance of said active heterostructure .

30. The semiconductor device of claim 27, wherein said polarization layers comprise high uniformity.

31. The semiconductor device of claim 1, wherein each of said p-layer, said n-layer, and said active heterostructure comprise minimized hydrogen content.

32. The semiconductor device of claim 1, wherein each of said p-layer, said n-layer, and said active heterostructure comprise thermal disorder correctives.

33. The semiconductor device of claim 1, further comprising optics adjacent to substrate opposite said buffer layer.

34. The semiconductor device of claim 33, wherein said optics comprise beam forming optics.

35. The semiconductor device of claim 1, further comprising optics adjacent to said p-layer opposite said active heterostructure.

36. The semiconductor device of claim 35, wherein said optics comprise a mirror.

37. The semiconductor device of claim 36, wherein the mirror comprises a Bragg mirror.

38. The semiconductor device of claim 1, further comprising at least two sidewall mirrors, wherein each of said sidewall mirrors contacts at least said n-layer, said p-layer, and said active heterostructure.

39. The semiconductor device of claim 38, wherein each of said sidewall mirrors comprises SiN.

40. The semiconductor device of claim 1, further comprising at least two sidewall thin films, wherein each of said sidewall thin films contacts at least said n-layer, said p-layer, and said active heterostructure.

41. The semiconductor device of claim 40, wherein each of said sidewall thin films increases negative influence .

42. The semiconductor device of claim 1, further comprising at least one corrective optic acting on the photons emitted from said active heterostructure, wherein said at least one corrective optic increases quantum efficiency to about 70%.

43. The semiconductor device of claim 1, further comprising at least one Presnel lens at a photon emission point along said substrate.

44. The semiconductor device of claim 43, wherein said Fresnel lens collimates light output resultant from the photons emitted.

45. The semiconductor device of claim 43, wherein said Fresnel lens comprises a positive lens having two finite conjugates.

46. The semiconductor device of claim 1, further comprising an n-contact for delivery of an electrical stimulus to said active heterostructure .

47. The semiconductor device of claim 46, wherein said n-contaσt comprises a conductive transparent film.

48. The semiconductor device of claim 46, wherein said n-contact comprises a spider assembly.

49. The semiconductor device of claim 46, wherein said n-contact comprises TA/Al/In/Au.

50. The semiconductor device of claim 1, further comprising a p-contact for delivery of an electrical stimulus to said active heterostructure .

51. The semiconductor device of claim 50, wherein said p-contact comprises Ni and Pd.

52. A method of forming a semiconductor device, comprising:

pre-cleaning a substrate;

sequentially forming an n-layer, an active layer, and a p-layer on the substrate;

depositing a mirror atop the p-layer; etching a mesa profile of sequentially decreasing width, for the n-layer, the active layer, the p-layer, and the mirror; and

depositing side mirrors along sides of the mesa profile.

53. The method of claim 51, further comprising forming a nucleated buffer layer between the substrate and the n-layer.

54. The method of claim 51, further comprising depositing electrical contacts.

55. The method of claim 51, further comprising testing and grouping the semiconductor device.

56. The method of claim 51, further mounting the semiconductor device in a matrix with other ones of the semiconductor device.

57. The method of claim 51, wherein said forming the p-layer comprises a magnesium implanting.

58. The method of claim 51, wherein said forming the n-layer comprises a silicon implanting.

59. The method of one of claims 56 or 57, wherein said implanting comprises:

heating an implanting region;

depositing a thin film on the implanting region;

implanting through the thin film to the implantation region; and removing the thin film.

60. The method of claim 51, wherein said sequentially forming comprises sequentially forming via an enhanced cyclotron resonance deposition.

61. The method of claim 59, wherein at least one of said ECR depositions occurs at 800 Celsius

62. The method of claim 51, wherein said etching comprises etching via an enhanced cyclotron resonance etch.

63. The method of claim 61, wherein said etching comprises a chlorine ECR etch.

€4. A semiconductor device, comprising: US2005/032526

a substrate ;

a n-layer;

a buffer formed between said substrate and said n-layer;

an active heterostructure including a plurality of quantum wells formed atop said n-layer;

a p-layer formed atop said active heterostructure; and

a plurality of reflective surfaces that bound said p-layer opposite said active heterostructure and each sidewall formed by a successive layering of said buffer layer, said n-layer, said active heterostructure, and said p-layer.

65. The semiconductor device of claim 63, wherein said substrate is substantially optically transparent to allow for propagation of photons generated by the quantum wells.

66. The semiconductor device of claim 63, wherein said substrate is transparent .

67. The semiconductor device of claim 65, further comprising at least one optic integral to said device for extracting increased light through said transparent substrate .

68. The semiconductor device of claim 63, further comprising a substantially enclosed negative effect box substantially surrounding said active layer to minimize depletion losses.

69. The semiconductor device of claim 67, wherein minimizing depletion losses increase the emission intensity.

70. The semiconductor device of claim 63, further comprising a n-contact.

71. The semiconductor device of claim 69, wherein the placement of said n-contact improves the internal diode field distribution as a result of the proximity/

72. A light emitting diode device with white light output, said device comprising:

a blue light emitting diode, said blue diode comprising:

a substrate;

a n-layer;

a buffer formed between said substrate and said n-layer;

an active heterostructure including a plurality of quantum wells formed atop said n-layer; and a p-layer formed atop said active heterostructure ;

a green light emitting diode, said green diode comprising:

a substrate;

a n-layer;

a buffer formed between said substrate and said n-layer;

an active heterostructure including a plurality of quantum wells formed atop said n-layer,- and

a p-layer formed atop said active heterostructure;

a red light emitting diode, said red diode comprising:

a substrate;

a n-layer; a buffer formed between said substrate and said n-layer;

an active heterostructure including a plurality" of quantum wells formed atop said n-layer; and

a p-layer formed atop said active heterostructure;

a mount for each of said red, blue, and green diodes, said mount placing the output face of each diode in close proximity to the others of said diodes; and

a plurality of optics for color mixing the output of each of said red, blue, and green diodes to produce a functional white light output from said device .

73. The light emitting diode device of claim 71, wherein said plurality of optics include a CPC.

74. The light emitting diode device of claim 72, wherein said CPC includes a refractive index gradient .

75. The light emitting diode device of claim 73, wherein said refractive index gradient is radial .

76. The light emitting diode device of claim 73, wherein said refractive index gradient is in the z-axis.

77. The light emitting diode device of claim 73, wherein said refractive index gradient is both radial and in the z-axis.

78. The light emitting diode device of claim 71, wherein said plurality of optics include edge shaping optics to force high angle light rays out of the device.