Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/70—Masking faults in memories by using spares or by reconfiguring
  • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
  • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
  • G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches

Definitions

• the present invention relates to memory circuits, and more particularly to memory circuits with row and column redundancy.
• memories may include redundant rows or columns of memory cells. These redundant components are not used if the memory's non-redundant memory cells contain no manufacturing errors. If, however, a memory cell is faulty, a redundant memory component may be substituted for one of the non-redundant memory components such that the memory component including the faulty memory cell is no longer used. For example, a redundant row of memory cells is addressed in a row redundancy scheme only if a non-redundant row includes a faulty memory cell. Should a user desire to address the faulty row, the memory's row decoder addresses a substituted row instead.
• each group of rows will be denoted as a "row-unit.” Should a memory cell be faulty in a row-unit, that row-unit is no longer used and a substitute row-unit is used instead. With regard to the row-units, it is conventional to organize memory row-units into blocks such that each block includes its own X decoder as well as a redundant row-unit. A similar group organization may be implemented for the columns. For example, Figure 1 illustrates a memory including a plurality of 8 memory blocks arranged from a block 0 to a block 7.
• Each block includes a redundant row-unit and is addressed by a corresponding X decoder and a Y driver (for illustration clarity, only the X decoders are illustrated).
• Each X decoder must then be able to identify whether a row-unit is bad. For example, a one-bit signal may be used as a flag indicating whether a row-unit in a given block is faulty. Should there be 64 row-units, a six-bit signal is sufficient to indicate the identity of the faulty row.
• Each X decoder may thus couple to a corresponding seven-bit- wide redundancy information bus to receive the flag and address signals (for illustration clarity, only X decoder 7 is shown coupled to its seven-bit- wide bus).
• each X decoder may thus identify whether a faulty row-unit exists, the X decoder must include a decoding portion to decode the contents of the bus, thereby occupying valuable die space. Moreover, the routing of the necessary buses complicates design. Finally, the demand on the input/output (I/O) resources can be considerable. For example, 56 I/O pins would need to be reserved for the row redundancy information for the memory of Figure 1 (7 bits times 8 blocks).
• a memory includes: a redundant row-unit having one or more rows of memory cells; a plurality of memory cells arranged according to rows, wherein the rows are arranged into a plurality of row-units such that each row-unit has the same number of rows, and wherein the redundant row-unit includes the same number of rows; a plurality of repair memory cells corresponding on a one-to-one basis with the plurality of row-units, each repair memory cell operable to store a repair true or false value signal; and an X decoder for addressing the rows, the X decoder adapted to respond to an address for a row-unit having a repair memory cell storing the repair true signal by addressing a unit selected from the remaining row-units and the redundant row-unit, wherein each repair memory cell is adapted to store the repair true signal in response to an assertion of a set signal and an addressing of the corresponding row-unit.
• a memory includes: a redundant column-unit having one or more columns of memory cells; a plurality of memory cells arranged according to columns, wherein the columns are arranged into a plurality of column-units such that each column-unit has the same number of columns, and wherein the redundant column-unit includes the same number of columns; a plurality of repair memory cells corresponding on a one-to-one basis with the plurality of column- units, each repair memory cell operable to store a repair true or false value signal; and a Y driver for driving the columns, the Y driver adapted to respond to an access for a column- unit having a repair memory cell storing the repair true signal by accessing a unit selected from the remaining column-units and the redundant column-unit, wherein each repair memory cell is adapted to store the repair true signal in response to an assertion of a set signal and a write operation for the corresponding column-unit.
• Fig. 1 is a block diagram of a conventional row redundancy architecture.
• Fig. 2 illustrates aspects of a row redundancy architecture according to an embodiment of the invention.
• Fig. 3. illustrates a portion of a memory including the row redundancy architecture of Fig. 2.
• Fig. 4. is a timing diagram for the control signals of Figure 2.
• Fig. 5 illustrates an alternative memory cell configuration for storing the repair state information of Figure 2.
• Fig. 6 illustrates portion of a memory include a column redundancy architecture according to an embodiment of the invention.
• a row redundancy architecture is shown that eases the I/O resource demands and die area demands discussed earlier by storing the row redundancy identification information in binary storage cells such as repair memory cell 200 represented by cross-coupled inverters 205 and 210.
• Each row-unit (not illustrated) has its own corresponding repair memory cell 200, which may comprise an SRAM cell, a non-volatile memory cell, or any other suitable memory cell.
• Repair memory cell 200 may be reset through the assertion of a reset signal 206 that drives a gate of a transistor 215.
• "assertion" of a signal indicates the signal has a binary true state.
• repair memory cell 200 stores a "repair false" binary signal upon assertion of the reset flag.
• a user may invoke a redundancy row substitution by asserting a set signal 220 while accessing the row-unit such as through a write or read operation that raises a wordline within the row-unit.
• a row-unit may include just a single row of memory cells (and hence a single word line) or may include multiple memory rows.
• each row-unit includes a plurality of rows
• the corresponding wordlines may be logically OR'ed to provide a wordline ⁇ 0:n> signal 220.
• the result of the access operation to the row-unit is that wordline signal ⁇ 0:n> 220 is asserted.
• the assertion of this signal drives a transistor 225 to conduct. While transistor 225 is conducting, the assertion of the set signal drives a transistor 230 to conduct such that a repair complement node of the repair memory cell is de-asserted, whereby the repair memory cell stores a "repair true" binary signal.
• FIG. 3 a memory 300 is illustrated that includes the row redundancy architecture discussed with regard to Figure 2. For illustration clarity, only a single block is illustrated having four wordlines arranged from a wordline 0 to a wordline 3. In this embodiment, each row-unit includes just a single wordline such that wordlines 0 through 3 may also be considered as row-units 0 through 3. It is convenient for the corresponding repair memory cells 200 to be included in the X decoder but they may be located in other areas as well. A user may assert the set and reset signals through pins 305 and 310, respectively. Suppose it is determined the row of memory cells (not illustrated) corresponding to wordline 3 includes a faulty cell.
• repair memory cells 200 store a "repair false" state (represented by logical zeroes).
• the set signal may then be asserted while an access operation such as a read operation specifying the address for wordline 3 is performed.
• Repair memory cell 200 for wordline 3 will thus store a "repair true” signal (represented by a logical one).
• the X decoder senses the assertion of the repair true signal for wordline 3 and will thus substitute one of the remaining wordlines or the redundant wordline during access operations that would otherwise access the memory row corresponding to wordline 3.
• the operation of memory 300 may be better understood with regard to the timing diagram of Figure 4.
• a user Before writing to the appropriate repair memory cells 200, a user has tested the memory and identified the faulty row(s).
• a user may first assert the reset signal.
• memory accesses are performed synchronously with a clock.
• the clock when the clock is asserted, the user may perform an access operation such as a read or write to a row-unit including a faulty memory cell.
• a first repair address is provided corresponding to a wordline within the row-unit with the faulty row-unit so that the corresponding repair memory cell stores a repair true state.
• a second repair address (if necessary) is provided at the subsequent clock pulse, and so on.
• the set signal Simultaneously with the provision of the repair addresses, the set signal is asserted as discussed with regard to Figures 2 and 3.
• a column redundancy scheme may include analogs of row- units which will be denoted herein as "column-units.” Each column-unit may include one or more bit lines that are grouped according to the memory blocks (each memory block having its own X decoder, Y driver, wordlines, and bitlines). Referring again to Figure 2, transistor 225 would then be controlled by a bitline ⁇ 0:n> signal that is formed analogously as discussed with regard to the wordline ⁇ 0:n> signal.
• each column-unit include a plurality of n bitlines
• these bitlines are logically OR-ed to form the bitline ⁇ 0:n> signal (it will be appreciated that in embodiments having both true and complement bit lines, just the logical true bit lines need be OR-ed) .
• the access operation for a column redundancy implementation should be a write operation.
• a corresponding row redundancy implementation could be made responsive to a read operation such that the set signal could be common to both the row and column redundancy schemes. In this fashion, just a single pin needs to be reserved for the set signal, there being no need for separate "row reset" and a "column reset" signals.
• the column-unit may be selected through a combination of the ' input data and the address bits corresponding to the column multiplexer.
• the same set signal may be used in a memory that incorporates both row and column redundancy. For example, the wordline ⁇ 0:n> signal could be asserted only during read operations whereas the bitline ⁇ 0:n> signal could be asserted only during write operations. In this fashion, a single set signal is shared with both the row and column redundancy schemes.
• the reset pin may be eliminated through the use of a pulse generator that pulses the reset signal on the signal edge when the set signal is asserted.
• the access operation read or write
• the access operation should be delayed sufficiently while the pulse generator pulses.
• the access operation would still be asserted, however, during the assertion of the set signal - the set signal would just be asserted slightly longer to account for the time during which the pulse generator pulses.
• memory cell 200 can be implemented using a flip-flop register 500 such as illustrated in Figure 5 that includes an asynchronous set input.
• the D input is grounded whereas the set signal is tied to the clock input.
• the set signal as well as the wordline ⁇ 0:n> signal (or bitline ⁇ 0:n> signal in a column redundancy implementation) drives an AND gate 505 tied to the asynchronous set input.
• a memory 600 includes a Y driver 605 that reads the contents of repair memory cells 200. Unlike an X decoder, a Y driver need not decode addresses in that it simply reads (or writes) to all bit lines corresponding to a given word.
• each column-unit comprises a single bit line, arranged from a bit line 0 to a bit line 3 (it will be appreciated, however, that what is denoted as a "single bit line" may actually comprise a true and complement bit line depending upon the memory architecture).
• the corresponding redundant column-unit thus comprises a single redundant bit line.
• Y driver 605 functions to substitute a unit selected from the remaining column-units and the redundant column-unit for the faulty column-unit.

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• 2006
  • 2006-08-16 WO PCT/US2006/032222 patent/WO2007022393A2/en active Application Filing
  • 2006-08-16 CN CNA2006800367705A patent/CN101317229A/zh active Pending

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