WO2007020557A1

WO2007020557A1 - Timing recovery for semi synchronous receiver

Info

Publication number: WO2007020557A1
Application number: PCT/IB2006/052717
Authority: WO
Inventors: David Modrie; Koen Vanhoof
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2005-08-19
Filing date: 2006-08-07
Publication date: 2007-02-22
Also published as: TW200723700A

Abstract

Resampling apparatus (100) has a sample rate converter (13) for receiving first samples at a first sample rate and outputting converted samples at a converted sample rate according to an output clock, and a phase locked loop (55) for deriving the output clock synchronized to transitions represented by samples at the first sample rate. By synchronizing to the first samples rather than using only feedback from the converted samples, there is less delay in responding to changes in the input. The converted samples can be fed to a bit detector. This can enable more rapid detection of data read from optical discs.

Description

Timing recovery for semi synchronous receiver

This invention relates to resampling apparatus for receivers, to systems having such apparatus, and to corresponding methods.

It is known to provide receiver circuitry for application such as optical disc players. An analog replay signal is retrieved from an optical disc. An optical head retrieves the analog replay signal by using a laser. After some analog processing the replay signal is provided to a converting means such as an Analog to Digital converter (ADC) to provide digital samples. The ADC is controlled by a clock. For example, for a synchronous receiver, a voltage controlled oscillator VCO based phase locked loop can be used, e.g. a PLL, to clock the ADC and is controlled by an error signal fed back from the digital side. The error generator generates an error signal from an output of digital processing means (DPM), an equalizer for instance. The DPM processes the output signal of the ADC. Finally the output of the DPM is fed to a detector to produce the data sequence. All the processing after the ADC is done synchronously with a data rate 1/T of the data sequence.

As receivers for digital recording and transmission are increasingly implemented digitally, the VCO based timing recovery has been replaced by a timing recovery using a sample rate converter (SRC). The first part of this receiver also consists of analog processing means and an ADC. The ADC in this receiver is controlled by a free running clock. The free running clock is usually a crystal based clock. The frequency of the clock is independent of the data rate 1/T of the data sequence. The output of the ADC is fed to a sample rate converter (SRC). The SRC can be controlled by a Numerical Controlled Oscillator (NCO). The frequency of the output signal of the NCO is dependent on the output signal of an error generator. The error generator reacts to an output of digital processing means (DPM). Again the output of the DPM is fed to a detector to generate the data sequence. The advantage of such synchronously sampled receivers is that the digital signal processing, like equalizing for instance, can be done in the symbol rate clock domain retrieved by the timing recovery. On the other hand the delay resulting from this processing contributes to the overall delay of the loop, which can lead to instabilities, especially when high bandwidths are required. This constrains considerably the digital processing used in the loop and therefore the performance can potentially be severely degraded.

Patent application WO 03100781 proposes altering the known receiver topology with an SRC as described above, while keeping the 'frequency-scaling' advantage of the synchronous receiver. It involves moving the digital processing block from its position inside the timing recovery to the asynchronous domain, i.e. between the Analog to Digital Converter ADC and the SRC. Because the processing is positioned in the asynchronous domain, its time span depends now on the over-sample ratio T/Ts, resulting in an oversampling dependent performance. Instead of a free running clock the ADC can be controlled by a preset value. The preset value controls the rate at which the ADC makes samples. The preset value is chosen such that the T/Ts ratio has a fixed value, although a few percents of deviation is possible. The timing recovery, which transfers the signals from the asynchronous Ts domain to the data-rate domain, can be optimized employing the fixed T/Ts ratio. Instead of an ADC controlled by the preset value, also an ADC controlled by a free running clock combined with a second SRC can be used, wherein the ADC outputs an intermediate received sequence. The second SRC converts the intermediate received sequence into the received sequence, where the sample rate is controlled by the preset value. The combination of the ADC with the second SRC results in the same received sequence compared to the preset value controlled ADC. US patent application 2004086067 shows recovering a clock signal without requiring a data receiver to adopt a sampling frequency that is an integer multiple of the data bit rate. An encoded digital data signal is fed to a zero-crossing detector and to a decoder. Input pulses from zero-crossing detector are provided to a synchronizer. Based on certain thresholds also provided to synchronizer, a synchronization or sync signal is provided to a clock generator. Using sampling frequency Fs as a counting reference, the clock generator regenerates the clock timing signal which is provided to the decoder to regenerate the original binary data stream.

US6801591 shows using a PLL to generate a clock locked to incoming data. A video processing unit produces an output signal. A sample rate converter is provided in an output signal path for converting the sample rate of the output signal of a video-processing unit that runs on the clock frequency locked to the incoming data. The sample rate converter can be controlled by phase information phs out of a non- integer divider coupled to the PLL. An object of the invention is to provide improved resampling apparatus for receivers, and to systems having such apparatus, and to corresponding methods. According to a first aspect, the invention provides:

An arrangement for resampling or a resampling apparatus for a receiver, the arrangement or resampling apparatus having a sample rate converter for receiving a signal represented by first samples at a first sample rate and outputting converted samples at a converted sample rate according to an output clock, and a clock recovery part for deriving the output clock, the clock recovery part operating on the signal represented by the first samples at the first sample rate. The operating on the signal represented by the first samples results in locking to the output clock. By operating on the first samples rather than using only feedback from the converted samples, there is less delay in responding to changes in the input. Thus, the synchronization/locking can take place more quickly. This is particularly useiul where a data standard specifies a short run in period for completing synchronization before reading desired data. Further, the first sample rate can be selected arbitrarily, hence making this part of the circuit simpler.

An additional feature of some embodiments is the clock recovery part having a phase locked loop.

Another such additional feature is the loop for the clock recovery and in particular the phase locked loop in the clock recovery part not having the sample rate converter in its loop.

Another such additional feature is the clock recovery part and in particular the phase locked loop having a zero crossing detector, and the clock recovery part, e.g. the phase locked loop being locked to the detected zero crossings. Another such feature is the phase locked loop having a comparator for generating an error signal by comparing the detected zero crossings with zero crossings of the output clock.

Another such feature is the clock recovery part and in particular the phase locked loop having an oscillator for generating the output clock controlled according to an integral of the error signal.

Another such additional feature is the first sample rate being higher than a bit rate, i.e. oversampling.

Another such additional feature is the converted sample rate being a bit rate of the received data. Another feature is a receiver having the resampling apparatus included therein. An additional feature of the receiver is a preliminary sample rate converter for providing the first samples.

Another such additional feature is a bit detector arranged to use the converted samples.

Another such feature is a system having such a receiver.

Another aspect provides:

Resampling apparatus for a receiver, the resampling apparatus having a sample rate converter for receiving a signal represented by first samples at a first sample rate and outputting converted samples at a converted sample rate according to an output clock, and a clock recovery part for deriving the output clock synchronized to the signal represented by the first or the converted samples, the clock recovery part having a phase locked loop arranged such that the sample rate converter is outside the loop of the phase locked loop.

By excluding the sample rate converter from the phase locked loop, the loop is shorter and so there is less delay in responding to changes in the input. Thus the synchronization can take place more quickly. This is particularly useful where a data standard specifies a short run in period for completing synchronization before reading desired data. This applies whether the PLL is synchronized by the samples before or after the sample rate conversion. Another aspect of the invention provides a corresponding method:

A method of receiving first samples at a first sample rate, having the steps of outputting converted samples at a converted sample rate according to an output clock, and the step of deriving the output clock synchronized to transitions represented by samples at the first sample rate. Any of the additional features can be combined together and combined with any of the aspects. Other advantages will be apparent to those skilled in the art, especially over other prior art. Numerous variations and modifications can be made without departing from the claims of the present invention. Therefore, it should be clearly understood that the form of the present invention is illustrative only and is not intended to limit the scope of the present invention.

How the present invention may be put into effect will now be described by way of example with reference to the appended drawings, in which: Fig. 1 shows a known arrangement, Fig. 2 shows a receiver embodiment, and Fig. 3 shows another embodiment of resampling apparatus.

The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. Any reference signs in the claims shall not be construed as limiting the scope. The drawings described are only schematic and are non- limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. Where the term "comprising" is used in the present description and claims, it does not exclude other elements or steps. Where an indefinite or definite article is used when referring to a singular noun e.g. "a" or "an", "the", this includes a plural of that noun unless something else is specifically stated. Furthermore, the terms first, second, third and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.

Moreover, the terms top, bottom, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other orientations than described or illustrated herein.

In the following reference will be made to receivers. A receiver for use in telecommunications networks typically has an analog front end, an analog to digital converter and a digital signal processing part. In the digital signal processing part the digital signal which has been modulated onto a carrier in analog form is reconstructed. The output of a receiver is typically a bit stream. To retrieve the bit stream in the digital signal processing part of the receiver from the reconstructed digital signal, a bit detector circuit is typically used, e.g. to detect in a binary system whether a bit has a "1" or a "0" value. The bit detector will generally be a block which converts the resampled input signal to the final user bits.

Figure 1: Semi-synchronous receiver architecture known from WO 03100781. In Fig. 1 shows a known arrangement including converting means 40 feeding samples to a digital processing means 12. An output of this goes to a detector 16 via SRC 13. The output of the detector is data sequence ak. The converting means 40 comprises an ADC

41 and a preliminary sample rate converter 42 operating at a sample rate which is controllable by the preset value Pv. The ADC 41 converts the analog signal Sa into an intermediate received sequence ri. After the ADC 41 the preliminary sample rate converter

42 converts the intermediate received sequence ri into the received sequence rn at a sample rate 1/Ts controlled by the preset value Pv.

The free running clock FC has a frequency independent of the data rate 1/T of the data sequence ak. The SRC 13 is controlled by control signal generating means 15. The control signal generating means 15 can for instance be a Numerical Controlled Oscillator (NCO). The frequency of the output signal of the NCO is dependent on the output signal of the error generator 14. The digital processing means 12 is positioned between the converting means 40 and the sample rate converter 13. Because the processing is positioned in the asynchronous domain, its time span depends now on the over-sample ratio T/Ts, resulting in an oversample dependent performance. Therefore, a preset value Pv is used to control the sample ratio of the converting means 40. The preset value Pv is chosen such that the T/Ts ratio has fixed value, a few percents of deviation is possible. The timing recovery, which transfers the signals from the asynchronous Ts domain to the data- rate domain, can be optimized employing the fixed T/Ts ratio. The NCO can be seen as reconstructor of the T timebase. It uses the error generator information based on the zerocrossings to reconstruct the T time base.

Figure 2 showing first system embodiment.

Figure 2 shows a first embodiment of the invention, in which the second sample rate converter has been expelled from the loop 35 that reconstructs the clock T. This contrasts with the locked loop arrangement shown in fig 1 including the NCO, by reducing the number of elements in the control loop, which thus can help reduce the delay in the loop. In other words a consequence is an increase in the bandwidth of the loop that reconstructs the clock T. Furthermore the loop that reconstructs the clock T is now completely placed in the Ts time domain and the sample rate conversion from Ts to T takes place outside this loop.

In one aspect of the present invention the loop 35 that reconstructs the clock T can be based on a phase locked loop (PLL) controlled by an error signal. The PLL can be constructed based on zerocrossing detection, though other arrangements are possible including peak or slope detection. Zero crossings (or peaks or slopes) at the Ts sample rate are available for the PLL to carry out rapid synchronization. Where Ts is higher than a bit rate T, this means that more samples are available for the loop which reconstructs the clock T and synchronization/locking can be quicker. PLLs controlling a sample rate converter (SRC), wherein the clock reconstruction loop and the SRC are decoupled can bring advantages including: faster locking, reduction of delays in the PLL, increase of margin of stability, increase in PLL bandwidth. As shown in Figure 2, an analog signal processing stage 10 feeds an ADC 41, and a preliminary SRCl 41. This feeds samples to the digital processing means 12 at sample rate Ts. As in fig 1, this feeds the SRC2, 13 which provides resampled samples to the detector 16 at sampling rate T. The detector can be any type. For example for optical storage applications, a runlength pushback is typically used to generate the databits out of the bitsynchronous sampled signal.

SRCl output is clocked by a timing signal generated by clock recovery circuit 35, based on samples at rate Ts from the SRCl, before or preferably after the digital processing means 12. In this structure the sample rate converter (SRC2), which 'resamples' the signal into the bit-synchronous domain, is put outside the timing recovery loop. Compared to Fig 1 where the timing recovery of the semi-synchronous receiver transfers the data signal from the semi-asynchronous Ts domain to the data-rate domain, with a fixed T/Ts ratio, fig 2 can be seen as having a feed forward path, for the clock recovery, and shows a simplified recovery part more clearly separated from the SRC2. For instance, for an example where Ts = -1/2 T, or a 2-times oversampled signal with respect to the datarate, then for every two samples coming into the sample rate converter, only 1 bit sample needs to be generated (in average). Thus more samples and so more zero crossings at a higher sample rate are available for the PLL to carry out rapid synchronization.

Figure 3, second embodiment relating to SRC2 and its clock recovery.

Figure 3 shows a schematic arrangement of a second embodiment of the present invention. It is a more specific implementation of the scheme shown in Fig. 2. As shown in Fig 3, a digital processing means 12 provides samples to a SRC2. The clock recovery part 35 does not have the SRC2 as part of its loop. A zero crossing detector 43 feeds a fast PLL 55 which in turn outputs a synchronized clock to SRC2. The fast PLL has a PI (proportional integral) controller 49 generating an increment for the DTO (Digitally tuned oscillator) 51. The DTO reconstructs the channel bitclock T. A Zerocrossing Generator (ZeroX Gen) 53 detects the ideal zerocrossing positions of the DTO which are fed to a Comparator 47 (Comp.) which compares the actual measured zero crossing positions with the ideal ones. The resampling apparatus 100 is intended to encompass the SRC2 and the clock recovery part.

The loop is constructed based on zerocrossing detection, though other arrangements are possible including peak or slope detection. The loop is called a fast PLL structure. This type of PLL has a minimum amount of delay, therefore allowing higher bandwidths. The PLL operates as follows: The position of the zerocrossings of the signal on Ts - time base are measured using the zerocrossing detector. These values are translated to the T domain, using a time base translation. When the fast PLL loop is "in lock', the DTO regenerates the T time base. From this DTO the ideal zerocrossings can be calculated (this is zerocrossings exactly in the middle of the sample moments). Both the measured zerocrossings and the ideal predicted zerocrossings can be compared and used to steer the DTO.

The error generator is typically driven by zerocrossing positions. The sampling is bitsynchronous when the zerocrossing are lying in the middle of the sample positions. An advantage of this structure is that the SRC2 is now also outside the timing recovery loop, allowing high bandwidths. The parts can be implemented in conventional hardware such as ASICs (application specific integrated circuits) or in firmware, or in software executed by conventional processing circuitry such as digital signal processors, or a combination of these or others.

In the Blue-Ray Disc standard (BD) it is perfectly possible to have isolated clusters on the disc or in other words clusters which don't have cluster neighbors. All clusters have a small run-in (and run-out area) in order to let control loops like the timing recovery lock onto the incoming HF signal. However this run-in area is rather small and therefore high bandwidths are required in order to not miss the first dataframe. Due to the minimum "loop length" of this PLL, higher bandwidths are possible, which can makes it feasible to read-out single written cluster on a empty BD-RE disc for instance.

The resampling apparatus can be incorporated for example in a CD or other optical disc player for instance. Typically an optical pickup unit (OPU) generates a laser beam that is projected on the surface of the information carrying optical disc. Reflections are detected and a detection means generates an analog signal Sa. The signal coming from the detection means can also be pre-processed by analog processing means before the analog signal Sa is outputted.

As well as applications in optical recording systems like

CD/DVD/BD/HDDVD/.., the same principles of operation can be used in general digital transmission systems.

As described above, the embodiments are related to bit detection and PLL. Here the second sample rate converter has been expelled from the loop that reconstructs the clock T. In other words the loop that reconstructs the clock T is completely placed in the Ts time domain and the conversion from Ts to T takes place outside the loop. In other words, a PLL clock recovery for controlling an SRC has a clock reconstruction loop decoupled from the SRC. Other variations can be envisaged within the claims.

Claims

CLAIMS:

1. An arrangement comprising a sample rate converter for receiving a signal represented by first samples at a first sample rate and outputting converted samples at a converted sample rate according to an output clock, and a clock recovery part for deriving the output clock, the clock recovery part operating upon the first samples at the first sample rate.

2. Arrangement according to claim 1 , wherein the clock recovery part comprises a phase locked loop.

3. Arrangement according to claim 1 or 2, wherein the clock recovery part does not have the sample rate converter in its loop.

4. Arrangement according to any previous claim, wherein the recovery part comprises a zero crossing detector, and the clock recovery part is locked to the detected zero crossings.

5. Arrangement according to claim 4 wherein the clock recovery part comprises a comparator for generating an error signal by comparing the detected zero crossings with zero crossings of the output clock.

6. Arrangement according to any of the claims 2 to 5, wherein the phase locked loop comprises an oscillator for generating the output clock controlled according to an integral of the error signal.

7. Arrangement according to any previous claim wherein the converted sample rate is a reconstructed bit rate of the signal.

8. A receiver having the arrangement of any of the claims 1 to 7.

9. Receiver according to claim 8 further comprising a preliminary sample rate converter for providing the first samples.

10. A method of receiving first samples at a first sample rate, comprising: - outputting converted samples at a converted sample rate according to an output clock, and, deriving the output clock synchronized to transitions represented by samples at the first sample rate.