WO2007014320A3 - Method and structure for fabricating multiple tile regions onto a plate using a controlled cleaving process - Google Patents

Method and structure for fabricating multiple tile regions onto a plate using a controlled cleaving process Download PDF

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Publication number
WO2007014320A3
WO2007014320A3 PCT/US2006/029378 US2006029378W WO2007014320A3 WO 2007014320 A3 WO2007014320 A3 WO 2007014320A3 US 2006029378 W US2006029378 W US 2006029378W WO 2007014320 A3 WO2007014320 A3 WO 2007014320A3
Authority
WO
WIPO (PCT)
Prior art keywords
substrates
substrate
plate
cleaving process
track member
Prior art date
Application number
PCT/US2006/029378
Other languages
French (fr)
Other versions
WO2007014320A2 (en
WO2007014320A9 (en
Inventor
Francois J Henley
Original Assignee
Silicon Genesis Corp
Francois J Henley
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/191,464 external-priority patent/US7674687B2/en
Application filed by Silicon Genesis Corp, Francois J Henley filed Critical Silicon Genesis Corp
Priority to JP2008524186A priority Critical patent/JP2009507363A/en
Publication of WO2007014320A2 publication Critical patent/WO2007014320A2/en
Publication of WO2007014320A9 publication Critical patent/WO2007014320A9/en
Publication of WO2007014320A3 publication Critical patent/WO2007014320A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
    • H01L21/2236—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase from or into a plasma phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H01L21/67213—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process comprising at least one ion or electron beam chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Plasma & Fusion (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Electromagnetism (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)
  • Plasma Technology (AREA)

Abstract

A method for manufacturing substrates using a continuous plasma immersion process is disclosed. A process chamber (215 having an inlet (207) and outlet (217) has a movable track member (219) contained therein. The moveable track member is used to transport the one or more substrates from the inlet, to the scanning area of chamber (215), and then to the outlet (217). The track member can be rollers, air bearings, belt members and/or a moveable beam member. The substrates are provided with a plurality of ti thereon which are subjected to the scanning implant process provided by device (213). A plurality of substrates with tiles can be sequentially processed by this method to improve throughput. An alternative to the substrates is a reusable transfer substrate member. This member has donor substrate regions which have a substrate thickness and substrate region wherein the regions do not have a definable cleave region.
PCT/US2006/029378 2005-07-27 2006-07-26 Method and structure for fabricating multiple tile regions onto a plate using a controlled cleaving process WO2007014320A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008524186A JP2009507363A (en) 2005-07-27 2006-07-26 Method and structure for forming multiple tile portions on a plate using a controlled cleavage process

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/191,464 2005-07-27
US11/191,464 US7674687B2 (en) 2005-07-27 2005-07-27 Method and structure for fabricating multiple tiled regions onto a plate using a controlled cleaving process
US83328906P 2006-07-25 2006-07-25
US60/833,289 2006-07-25

Publications (3)

Publication Number Publication Date
WO2007014320A2 WO2007014320A2 (en) 2007-02-01
WO2007014320A9 WO2007014320A9 (en) 2007-09-07
WO2007014320A3 true WO2007014320A3 (en) 2009-05-07

Family

ID=37683988

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/029378 WO2007014320A2 (en) 2005-07-27 2006-07-26 Method and structure for fabricating multiple tile regions onto a plate using a controlled cleaving process

Country Status (4)

Country Link
JP (1) JP2009507363A (en)
KR (1) KR20080042095A (en)
TW (1) TW200746277A (en)
WO (1) WO2007014320A2 (en)

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CN101281912B (en) 2007-04-03 2013-01-23 株式会社半导体能源研究所 Soi substrate and manufacturing method thereof, and semiconductor device
EP1978554A3 (en) * 2007-04-06 2011-10-12 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate comprising implantation and separation steps
EP1993127B1 (en) 2007-05-18 2013-04-24 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate
TWI437696B (en) * 2007-09-21 2014-05-11 Semiconductor Energy Lab Semiconductor device and method for manufacturing the same
JP5325404B2 (en) * 2007-09-21 2013-10-23 株式会社半導体エネルギー研究所 Method for manufacturing SOI substrate
JP5250228B2 (en) 2007-09-21 2013-07-31 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
JP5452900B2 (en) * 2007-09-21 2014-03-26 株式会社半導体エネルギー研究所 Method for manufacturing substrate with semiconductor film
JP5252867B2 (en) * 2007-09-21 2013-07-31 株式会社半導体エネルギー研究所 Manufacturing method of semiconductor substrate
JP2009094488A (en) * 2007-09-21 2009-04-30 Semiconductor Energy Lab Co Ltd Method of manufacturing substrate provided with semiconductor film
US8101501B2 (en) * 2007-10-10 2012-01-24 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
JP5506172B2 (en) * 2007-10-10 2014-05-28 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor substrate
US8236668B2 (en) 2007-10-10 2012-08-07 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
TWI493609B (en) * 2007-10-23 2015-07-21 Semiconductor Energy Lab Method for manufacturing semiconductor substrate, display panel, and display device
JP5548351B2 (en) * 2007-11-01 2014-07-16 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
US8163628B2 (en) * 2007-11-01 2012-04-24 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate
US20090139558A1 (en) * 2007-11-29 2009-06-04 Shunpei Yamazaki Photoelectric conversion device and manufacturing method thereof
US7947570B2 (en) * 2008-01-16 2011-05-24 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method and manufacturing apparatus of semiconductor substrate
JP5386193B2 (en) * 2008-02-26 2014-01-15 株式会社半導体エネルギー研究所 Method for manufacturing SOI substrate
US20090223628A1 (en) * 2008-03-07 2009-09-10 Semiconductor Energy Laboratory Co., Ltd. Manufacturing apparatus of composite substrate and manufacturing method of composite substrate with use of the manufacturing apparatus
JP5548395B2 (en) * 2008-06-25 2014-07-16 株式会社半導体エネルギー研究所 Method for manufacturing SOI substrate
EP2401768A4 (en) * 2009-02-27 2013-07-17 Alta Devices Inc Tiled substrates for deposition and epitaxial lift off processes
US8008176B2 (en) * 2009-08-11 2011-08-30 Varian Semiconductor Equipment Associates, Inc. Masked ion implant with fast-slow scan
KR101213955B1 (en) 2010-09-20 2012-12-20 에스엔유 프리시젼 주식회사 Substrate processing apparatus
WO2012060430A1 (en) 2010-11-05 2012-05-10 シャープ株式会社 Semiconductor substrate, method for manufacturing semiconductor substrate, thin-film transistor, semiconductor circuit, liquid crystal display device, electroluminescent device, wireless communication device, and light-emitting device
WO2013002227A1 (en) 2011-06-30 2013-01-03 シャープ株式会社 Method for producing semiconductor substrate, substrate for forming semiconductor substrate, multilayer substrate, semiconductor substrate, and electronic device
JP2015511989A (en) * 2011-12-23 2015-04-23 ソレクセル、インコーポレイテッド Productive semiconductor metallization and interconnect spraying
US9041147B2 (en) 2012-01-10 2015-05-26 Sharp Kabushiki Kaisha Semiconductor substrate, thin film transistor, semiconductor circuit, liquid crystal display apparatus, electroluminescent apparatus, semiconductor substrate manufacturing method, and semiconductor substrate manufacturing apparatus
US9577134B2 (en) * 2013-12-09 2017-02-21 Sunpower Corporation Solar cell emitter region fabrication using self-aligned implant and cap
CN113788441B (en) * 2021-08-25 2023-03-24 山东永昇重工有限公司 Hanging basket and assembling method thereof

Citations (3)

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US5863830A (en) * 1994-09-22 1999-01-26 Commissariat A L'energie Atomique Process for the production of a structure having a thin semiconductor film on a substrate
US20020029850A1 (en) * 1995-07-19 2002-03-14 Chung Chan System for the plasma treatment of large area substrates
US20080038908A1 (en) * 2006-07-25 2008-02-14 Silicon Genesis Corporation Method and system for continuous large-area scanning implantation process

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US20020029850A1 (en) * 1995-07-19 2002-03-14 Chung Chan System for the plasma treatment of large area substrates
US20080038908A1 (en) * 2006-07-25 2008-02-14 Silicon Genesis Corporation Method and system for continuous large-area scanning implantation process

Also Published As

Publication number Publication date
WO2007014320A2 (en) 2007-02-01
TW200746277A (en) 2007-12-16
WO2007014320A9 (en) 2007-09-07
JP2009507363A (en) 2009-02-19
KR20080042095A (en) 2008-05-14

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