WO2007013744A1 - Partage de memoire a partitions multiples a travers une pluralite de routes - Google Patents

Partage de memoire a partitions multiples a travers une pluralite de routes Download PDF

Info

Publication number
WO2007013744A1
WO2007013744A1 PCT/KR2006/002740 KR2006002740W WO2007013744A1 WO 2007013744 A1 WO2007013744 A1 WO 2007013744A1 KR 2006002740 W KR2006002740 W KR 2006002740W WO 2007013744 A1 WO2007013744 A1 WO 2007013744A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
multimedia data
control unit
storage area
processing unit
Prior art date
Application number
PCT/KR2006/002740
Other languages
English (en)
Inventor
Jong-Sik Jeong
Original Assignee
Mtekvision Co., Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mtekvision Co., Ltd filed Critical Mtekvision Co., Ltd
Publication of WO2007013744A1 publication Critical patent/WO2007013744A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems

Definitions

  • the present invention is directed to sharing of a memory (storage device), more
  • processors in an electrical/electronic device digital processing apparatus.
  • portable terminals refer to any portable terminals.
  • Portable terminals include
  • PDA personal digital assistants
  • PMP multimedia players
  • the mobile communication terminal is essentially
  • communication terminals have functions, such as camera and multimedia data playback, in addition to the basic functions, such as voice communication, short message service
  • FIG. 1 shows a block diagram of a conventional mobile communication terminal
  • the mobile communication terminal 100 having a camera
  • the high frequency processing unit 110 processes a high frequency signal
  • the analog-to-digital converter 115 converts an analog signal, outputted from
  • the high frequency processing unit 110 to a digital signal and sends to the processing unit
  • the digital-to-analog converter 120 converts a digital signal, outputted from the
  • processing unit 125 to an analog signal and sends to the high frequency processing unit
  • the processing unit 125 controls the general operation of the mobile
  • the processing unit 125 can comprise a central processing
  • the power supply 130 supplies electric power required for operating the mobile
  • the power supply 130 can be coupled to, for example, an
  • the key input 135 generates key data for, for example, setting various functions
  • the main memory 140 stores an operating system and a variety of data of the
  • the main memory 140 can be, for example, a flash
  • EEPROM Electrically Erasable Programmable Read Only Memory
  • the display 145 displays the operation status of the mobile communication
  • relevant information e.g. date and time
  • an external image e.g.
  • the camera 150 photographs an external image (a photographic subject), and the
  • image processing unit 155 processes the external image photographed by the camera 150.
  • the image processing unit 155 can perform functions such as color interpolation, gamma
  • the support memory 160 stores
  • the support memory 160 stores the external image processed by the image processing unit 155.
  • SRAM Static RAM
  • SDRAM Synchronous DRAM
  • the mobile communication terminal 100 having a camera
  • a function is equipped with a plurality of processing units (that is, a main processor and one or more application processors for performing additional functions).
  • processing units that is, a main processor and one or more application processors for performing additional functions.
  • Each processing unit is structured to be coupled with an
  • each application processor can be controlled by
  • the application processor can take different forms and quantity depending on
  • the application processor for controlling the camera function can process
  • controlling the movie file playback function can process functions such as video file (e.g.,
  • MPEG4, DIVX, H.264) encoding and decoding ; and the application processor for
  • controlling the music file playback function can process functions such as audio file
  • the portable terminal can also comprise an application processor
  • Each of these processing units has an individual memory for controlling games.
  • Each of these processing units has an individual memory for controlling games.
  • Each of these processing units has an individual memory for controlling games.
  • processor in order to expand the storage space or improve the process efficiency.
  • the conventional memory sharing structure uses a memory having a single port, delaying the time and lacking the efficiency in processing a high-resolution,
  • FIG. 2 is a coupling structure between a processor and a memory in accordance
  • one processor can comprise a plurality of processing units
  • processor 230 Each of the processors is coupled parallel to a memory 240 through one
  • processor overwork due to the amount of data.
  • memory 240 becomes inevitably longer in proportion to the number of pixels of an image
  • FIG. 3 is a block diagram showing a main processor and an application
  • processor is a multimedia processor for controlling an image sensor 330 and for
  • the main processor 310 comprises a plurality of memory
  • controllers i.e. a first memory controller 333 and a second memory controller 336.
  • the main processor 310 writes data in the supplementary memory 325
  • main processor 310 writes data or reads the stored data by
  • the multimedia processor 320 comprises an interface 342, a controller 344, a
  • multimedia processing unit 346 an image sealer 348, a priority control unit 353 and a
  • the multimedia processor 320 is coupled to the supplementary memory 325
  • AP-AM application memory
  • multimedia processor 320 can be coupled to the display 145 in order to display the
  • the interface 342 communicates information between the multimedia processor
  • the multimedia processor 320 carries out an operation corresponding to a control signal, instructing a process operation, received from the main
  • the controller 344 controls the operation of the multimedia processor 320 in
  • the operation of the multimedia processor 320 is controlled; the data needed
  • the controller 344 can
  • controller 344 controls the operation of the multimedia processor
  • controller 344 can be, for example, an MCU (microcontroller unit).
  • the multimedia processing unit 346 reads image data stored in the
  • supplementary memory 325 and compresses it to a predetermined format (e.g. JPEG or
  • the multimedia processing unit 346 reads a
  • the image sealer 348 processes data inputted from the image sensor 330 in
  • the image sealer 348 performs, for example, adjustment of the image size, changing
  • the data processed by the image sealer 348 is stored in the supplementary memory 325 through the AP-AM bus by the memory
  • the priority control unit 353 determines the priority between a request to access
  • the processors to access the supplementary memory 325.
  • the priority control unit 353 is the priority control unit 353
  • the multimedia processor 320 can access the supplementary data
  • the memory control unit 356 controls one of the processors to access the
  • priority control unit 353 when the main processor 310 and the multimedia processor 320
  • memory control unit 356 controls one of the elements to access the supplementary
  • processors and/or elements access a single memory through a single bus.
  • processor 310 has temporal limitation to use a memory of the supplementary processor
  • the main processor 310 In case of playing back an MPEG file, the main processor 310 must
  • the multimedia processor Since the size of an MPEG file is large, the MPEG file is first
  • a particular element e.g. multimedia processing unit 3466 of the
  • multimedia processor 320 reads the data and decodes the data before delivering the data
  • each element included in the multimedia processor 320 must use the AP-AM bus
  • invention to provide a method for sharing a multi-partitioned memory through a plurality
  • the present invention also aims to provide a method for sharing a
  • the present invention also aims to provide a method for sharing a memory
  • Another object of the present invention is to provide a method for sharing a
  • Another object of the present invention is to provide a method for sharing a
  • main processor can control the application processor and communicate data with the
  • an aspect of the present invention features
  • the digital processing apparatus in accordance with a preferred embodiment of the present invention can comprise: a main processor; an application processor, being
  • connection bus ; and a memory, having a plurality of ports, each of which is coupled to the
  • the application processor can comprise: a multimedia data input unit,
  • a multimedia data processing unit reading and processing the
  • a first memory control unit setting a route
  • the multimedia data processing unit and a second memory control unit, setting a route
  • the m (a natural number between 2 and n-1, including 2) storage areas of the n
  • storage areas can be exclusively used by the multimedia data input unit.
  • the multimedia data In case all of the storage space of the storage area A is used, the multimedia data
  • the input unit can send a corresponding status signal to the second memory control unit, and the second memory control unit can renew a route such that the multimedia data input
  • the application processor can further comprise: a controller, controlling the
  • an access control unit controlling the first memory control unit in order to adjust the
  • the access control unit can control the second memory control unit such that one
  • multimedia data processing unit and controller accesses one of the main processor, multimedia data processing unit and controller accesses one of the main processor, multimedia data processing unit and controller accesses one of the main processor, multimedia data processing unit and controller accesses one of the main processor, multimedia data processing unit and controller accesses one of the main processor, multimedia data processing unit and controller accesses one of the main processor, multimedia data processing unit and controller accesses one of the main processor, multimedia data processing unit and controller accesses one of the
  • the application processor can further comprise an interface, which receives
  • the input device can be an image sensor.
  • the application processor
  • the digital processing apparatus in accordance with another preferred embodiment
  • embodiment of the present invention can comprise: a memory, having a plurality of ports;
  • the memory can comprise 2 or more partitioned storage areas.
  • the processor can comprise a plurality of processing units, which writes data in
  • the processor and the memory can be embodied in the same chip.
  • a first memory control unit setting a route in accordance with a
  • Each of the first memory bus and the second memory bus can couple the application processor to the memory.
  • the above method can further comprise the step of (e) the second memory
  • control unit resetting a route in accordance with a store order of the multimedia data
  • the step (d) can comprise the steps of: an access control unit setting an access
  • processing unit accesses the first storage area through the second memory bus, in case the
  • multimedia data processing unit has the priority.
  • the memory can have a plurality of ports and be partitioned to n (a natural
  • Each port is
  • recorded medium tangibly embodies a program of instructions executable by a digital signal
  • processing apparatus to execute a method for having a memory shared by each element
  • the program is readable by the digital processing apparatus.
  • the program executes the acts of: a first memory control unit setting a route in
  • multimedia data input unit used all of the storage space of the first storage area; the first
  • bus can couple the application processor to the memory.
  • the program can further execute the act of the second memory control unit
  • FIG. 1 shows a block diagram of a conventional mobile communication terminal
  • FIG. 2 shows a coupling structure between a processor and a memory in
  • FIG. 3 shows a block diagram of a main processor and an application processor
  • FIG. 4 shows a multi-partitioned memory sharing structure in accordance with a
  • FIG. 5 shows a form of partition of a multi-partitioned memory in accordance
  • FIG. 6 shows a flowchart of the operation of an application processor in
  • the first element can be
  • processing devices or systems e.g. portable terminals and/or home digital appliances,
  • PDA portable multimedia player
  • PMP portable multimedia player
  • MP3 player digital camera, digital television, audio equipment, etc.
  • processors or a plurality of elements included in one processor needs to share a
  • the portable terminal will be described hereinafter for the convenience of description and understanding. Moreover, it shall be easily understood
  • terminal but is applicable equivalently to any terminal having a memory shared by a
  • FIG. 4 is a block diagram showing a multi-partitioned memory sharing structure
  • FIG. 5 is a form
  • multimedia processor for controlling the image sensor 330 and for processing multimedia
  • image data e.g. image data and/or voice data
  • voice data inputted from the image sensor 330.
  • the supplementary memory 430 coupled to the application processor 320 can be shared by
  • the application processor 320 in accordance with the present
  • the invention is coupled to the main processor 310 through the MP-AP bus (host interface),
  • the application processor 320 can also process multimedia data inputted from the image sensor 330 and store the data in the supplementary memory 430.
  • the multimedia data stored in the supplementary memory 430 can be processed by the
  • the application processor 320 can comprise an interface 343, a controller 344, a
  • multimedia processing unit 346 an image sealer 348, an access control unit 410, a first
  • the interface 343 communicates information between the multimedia processor
  • the multimedia processor 320 carries out an operation
  • the controller 344 controls the operation of the multimedia processor 320 in
  • controller 344 controls the operation of the multimedia processor 320, reads
  • controller 346 can be, for example, an MCU (microcontroller unit). The controller 344
  • controller 344 controls the operation of the multimedia processor
  • the controller 344 can be, for example, an MCU (microcontroller unit).
  • multimedia processing unit 346 reads image data stored in the partitioned area and
  • the multimedia processing unit 346 can also read and decode a
  • unit 346 can also store the processed data in a storage area of the supplementary memory
  • the image sealer 349 processes data inputted from the image sensor 330 in
  • the image sealer 349 can, for example, generate a softened image through size
  • sealer 349 can be stored in a particular storage area of the supplementary memory 325
  • the image sealer 348 of the present invention is merely one embodiment of an
  • multimedia data e.g. image data and/or voice data
  • multimedia processing unit 346 illustrated in FIG. 4, is merely
  • any multimedia data processing unit that processes multimedia data stored in the
  • the access control unit 410 determines the priority between a request to access
  • main processor 310 is controlled to access the supplementary memory 325. Moreover,
  • the access control unit 410 determines the priority
  • the access control unit 410 may exclude multimedia data inputted from
  • the image sealer 348 when determining the priority, that is, the multimedia data inputted
  • memory control unit 420 can control the multimedia data inputted from the image sealer
  • the first memory control unit 415 controls one of the processors to access the
  • multimedia processor 320 request an access to the supplementary memory 325 at the
  • the first memory control unit 415 controls one of the elements to
  • multimedia data e.g. image data and/or voice data
  • the supplementary memory 325 coupled to the application processor 320
  • the supplementary memory 325 has one memory core
  • any of the first storage area, second storage area or third storage area can be any of the first storage area, second storage area or third storage area.
  • the first storage area can be set to be exclusively used
  • the third storage area and the third storage area can be set as a dedicated area for storing multimedia data
  • FIG. 5 shows a case of partitions of 3, for
  • main processor 310 In case the main processor 310 and/or a particular element of the application
  • processor 320 attempts to write data in A, a storage area, the main processor 310 and/or
  • main processor 310 and/or a particular
  • main processor 310 and/or the particular element sends a reading order (i.e. address
  • OE B Output Enable
  • chip selection signal for storage area B (CS B: Chip Select _ B) and a clock (CLKJB)) for writing data to the supplementary memory 325.
  • CS B Chip Select _ B
  • CLKJB clock
  • the read order or store order can be sent to the read order or store order
  • the size of the image sensor 330 has been 640x480 pixels, it is typically
  • the present invention can solve the problem of prolonged time taken to store data resulted from this increase.
  • FIG. 6 is a flowchart showing the operation of an application processor in
  • FIG. 5 will be referenced. It will be assumed that the first storage area is a dedicated area
  • third storage areas are dedicated for the image sealer 348. As described earlier, the name
  • the image sealer in step 610, stores multimedia data
  • control unit 410 controls the route such that the multimedia data outputted from the image
  • sealer 348 can be stored in the second storage area through the second memory control
  • step 615 the image sealer 348 determines whether the multimedia data is
  • step 610 is repeated. However, if the storage space in the second storage area is completely occupied
  • step 620 is performed.
  • a status signal e.g. information that
  • the multimedia data is completely stored, information that the storage space of the storage
  • the second memory control unit 420 controls the
  • image sealer 348 to access the third storage area by making reference to the received
  • the image sealer 348 can send the status signal to the access control unit
  • step 635 the image sealer 348 stores the multimedia data, inputted real time
  • the access control unit 410 receives the image sensor 330, in the accessed third storage area.
  • Steps following step 635 may be performed only if the data that the
  • image sealer 348 is to store in the supplementary memory 325 is bigger than the second
  • the multimedia data is continuously received real time from the image
  • step 640 the image sealer 348 determines whether the multimedia data is
  • step 635 is repeated.
  • step 645 is performed.
  • the image sealer 348 terminates
  • a status signal e.g. information that the multimedia
  • the second memory control unit 420 controls the image
  • sealer 348 to access another storage area by making reference to the received status signal.
  • the image sealer 348 can send the status signal to the access control unit 410, which can
  • image sealer 348 If the image sealer 348 is designated to store multimedia data in the second and third
  • the second memory control unit 420 will make the image sealer 348
  • multimedia processing unit 346 is still accessed to the second storage area and is reading
  • the image sealer 348 may be restricted from storing data in the second
  • the image sealer 348 sends a status signal for terminating the access to the second storage area to the second memory control unit 420
  • step 625 the multimedia processing unit 346 (or the controller 344,
  • a request to access may include a read order
  • the second storage area may include a read order
  • memory control unit 415 controls the multimedia processing unit 346 to access the first
  • the multimedia processing unit 346 reads the
  • processed data can be displayed through the display 145.
  • Steps 625-630 are carried out for a separate storage area parallel to steps
  • step 645 the multimedia processing unit 346 sends to the access
  • control unit 410 and/or the first memory control unit 415 a request to access the third
  • the first memory control unit 415 controls the multimedia processing
  • the multimedia processing unit 346 to access the third storage area.
  • the multimedia processing unit 346 then reads the multimedia data stored in the third storage area and carries out necessary processes,
  • processed data can be displayed through the display 145.
  • processors having a plurality of processing units that read data written in the
  • the present invention can minimize the loss of process efficiency of an application processor and minimize the delay of time when processing a
  • the present invention can also maximize the efficiency of data storage and data
  • the present invention also can optimize the memory efficiency by allowing
  • the present invention also can control the loss of data by eliminating the delay in
  • the present invention can easily control a storage device by having an
  • interface to the storage device connect to only an element performing the function of a
  • the main processor can control the
  • the present invention can reduce the traffic in the system bus by

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Television Signal Processing For Recording (AREA)

Abstract

La présente invention a trait à un procédé et un dispositif pour le partage d'une mémoire à partitions multiples à travers une pluralité de routes. L'appareil de traitement numérique selon un mode de réalisation de la présente invention comporte: un processeur principal; un processeur d'application, contrôlé par le processeur principal et relié au processeur principal via un bus de connexion; et une mémoire, ayant une pluralité de ports, dont chacun est relié au processeur d'applications via un bus de mémoire indépendant, et étant segmenté en n (nombre naturel) zones segmentées. Grâce à la présente invention, il est possible d'accroître la vitesse de traitement d'une image de haute qualité.
PCT/KR2006/002740 2005-07-26 2006-07-12 Partage de memoire a partitions multiples a travers une pluralite de routes WO2007013744A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2005-0068065 2005-07-26
KR20050068065A KR100728650B1 (ko) 2005-07-26 2005-07-26 복수 경로를 통한 다중 분할된 메모리 공유 방법 및 장치

Publications (1)

Publication Number Publication Date
WO2007013744A1 true WO2007013744A1 (fr) 2007-02-01

Family

ID=37683599

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2006/002740 WO2007013744A1 (fr) 2005-07-26 2006-07-12 Partage de memoire a partitions multiples a travers une pluralite de routes

Country Status (2)

Country Link
KR (1) KR100728650B1 (fr)
WO (1) WO2007013744A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010041793A1 (fr) * 2008-10-07 2010-04-15 Chips & Media, Inc. Procédé et appareil de transformation d'interface d'accès à la mémoire

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100822468B1 (ko) * 2006-09-11 2008-04-16 엠텍비젼 주식회사 공유 메모리를 구비한 장치 및 코드 데이터 전송 방법
KR100855701B1 (ko) * 2007-01-26 2008-09-04 엠텍비젼 주식회사 복수의 프로세서 코어가 통합된 칩 및 데이터 처리 방법
KR101111946B1 (ko) 2009-12-17 2012-02-14 엠텍비젼 주식회사 촬상 장치, 이미지 시그널 프로세서 칩 및 칩 간의 메모리 공유 방법
KR102170879B1 (ko) 2014-04-18 2020-10-29 삼성전자주식회사 이미지 센서와 이를 포함하는 이미지 처리 시스템

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000029943A1 (fr) * 1998-11-16 2000-05-25 Telefonaktiebolaget Lm Ericsson Ordonnancement pour systeme de traitement
US6401176B1 (en) * 1997-11-14 2002-06-04 Agere Systems Guardian Corp. Multiple agent use of a multi-ported shared memory
US6463519B1 (en) * 1998-06-30 2002-10-08 Mitsubishi Denki Kabushiki Kaisha Multi-CPU unit
KR20040106778A (ko) * 2003-06-11 2004-12-18 엘지전자 주식회사 복수개의 프로세서를 갖는 이동통신 단말기의 메모리 공유장치 및 그 방법

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000044726A (ko) * 1998-12-30 2000-07-15 전주범 디지탈 처리 시스템에서의 메모리 관리 방법
EP1490764A2 (fr) * 2002-04-04 2004-12-29 Infineon Technologies AG Architecture amelioree a memoire partagee

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6401176B1 (en) * 1997-11-14 2002-06-04 Agere Systems Guardian Corp. Multiple agent use of a multi-ported shared memory
US6463519B1 (en) * 1998-06-30 2002-10-08 Mitsubishi Denki Kabushiki Kaisha Multi-CPU unit
WO2000029943A1 (fr) * 1998-11-16 2000-05-25 Telefonaktiebolaget Lm Ericsson Ordonnancement pour systeme de traitement
KR20040106778A (ko) * 2003-06-11 2004-12-18 엘지전자 주식회사 복수개의 프로세서를 갖는 이동통신 단말기의 메모리 공유장치 및 그 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010041793A1 (fr) * 2008-10-07 2010-04-15 Chips & Media, Inc. Procédé et appareil de transformation d'interface d'accès à la mémoire

Also Published As

Publication number Publication date
KR100728650B1 (ko) 2007-06-14
KR20070013620A (ko) 2007-01-31

Similar Documents

Publication Publication Date Title
US8051264B2 (en) Portable device and method for controlling shared memory in portable device
KR100855701B1 (ko) 복수의 프로세서 코어가 통합된 칩 및 데이터 처리 방법
US8135919B2 (en) Operation control of a shared memory partitioned into multiple storage areas
US20090254713A1 (en) Access control to partitioned blocks in shared memory
WO2007013744A1 (fr) Partage de memoire a partitions multiples a travers une pluralite de routes
WO2008018775A1 (fr) Dispositif ayant une mémoire partagée et procédé pour commander une mémoire partagée
KR100663380B1 (ko) 촬상 장치 및 영상 신호 생성 방법
US8145852B2 (en) Device having shared memory and method for providing access status information by shared memory
US20090254686A1 (en) Memory sharing through a plurality of routes
JP2007018222A (ja) メモリアクセス制御回路
KR100746364B1 (ko) 메모리 공유 방법 및 장치
US20080215825A1 (en) Memory Share by a Plurality of Processors
US7814282B2 (en) Memory share by a plurality of processors
WO2006109917A1 (fr) Procede et dispositif permettant d'acceder a une memoire individuelle
KR100592109B1 (ko) 공유 메모리의 분할 영역의 다중 억세스 제어 방법 및 공유메모리를 가지는 휴대형 단말기
KR100658588B1 (ko) 메모리 공유 시스템 및 그 방법
US6785795B1 (en) Data processing device for use in cooperation with a memory
US20080005417A1 (en) Method for speedy delivery of data between processors and digital processing apparatus having shared memory
KR100909025B1 (ko) 복수의 프로세서에 의한 메모리 공유 방법 및 메모리 공유구조를 가지는 휴대형 단말기
KR100658591B1 (ko) 공유 메모리를 이용한 디스플레이 제어 방법 및 장치
US6865635B1 (en) Access scheme for a collective resource using a plurality of states
KR100592108B1 (ko) 복수의 프로세서간의 신속한 데이터 전달 방법 및 공유메모리를 가지는 디지털 처리 장치
WO2007021154A1 (fr) Partage de memoire par une pluralite de processeurs
WO2007102712A1 (fr) Dispositif présentant une mémoire partagée et procédé utilisant cette mémoire partagée pour fournir des informations d'état d'accès
WO2007078072A1 (fr) Dispositif et procede destines a une interface memoire

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 06783292

Country of ref document: EP

Kind code of ref document: A1