WO2007102712A1 - Dispositif présentant une mémoire partagée et procédé utilisant cette mémoire partagée pour fournir des informations d'état d'accès - Google Patents

Dispositif présentant une mémoire partagée et procédé utilisant cette mémoire partagée pour fournir des informations d'état d'accès Download PDF

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Publication number
WO2007102712A1
WO2007102712A1 PCT/KR2007/001140 KR2007001140W WO2007102712A1 WO 2007102712 A1 WO2007102712 A1 WO 2007102712A1 KR 2007001140 W KR2007001140 W KR 2007001140W WO 2007102712 A1 WO2007102712 A1 WO 2007102712A1
Authority
WO
WIPO (PCT)
Prior art keywords
processor
processors
common area
status information
access
Prior art date
Application number
PCT/KR2007/001140
Other languages
English (en)
Inventor
Jong-Sik Jeong
Original Assignee
Mtekvision Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mtekvision Co., Ltd. filed Critical Mtekvision Co., Ltd.
Publication of WO2007102712A1 publication Critical patent/WO2007102712A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02K—DYNAMO-ELECTRIC MACHINES
    • H02K7/00—Arrangements for handling mechanical energy structurally associated with dynamo-electric machines, e.g. structural association with mechanical driving motors or auxiliary dynamo-electric machines
    • H02K7/10—Structural association with clutches, brakes, gears, pulleys or mechanical starters
    • H02K7/106—Structural association with clutches, brakes, gears, pulleys or mechanical starters with dynamo-electric brakes
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02K—DYNAMO-ELECTRIC MACHINES
    • H02K5/00—Casings; Enclosures; Supports
    • H02K5/24—Casings; Enclosures; Supports specially adapted for suppression or reduction of noise or vibrations
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02K—DYNAMO-ELECTRIC MACHINES
    • H02K2205/00—Specific aspects not provided for in the other groups of this subclass relating to casings, enclosures, supports
    • H02K2205/09—Machines characterised by drain passages or by venting, breathing or pressure compensating means

Definitions

  • the present invention relates to a digital processing apparatus, more specifically to a
  • digital processing apparatus having a shared memory that is shared by a plurality of
  • portable terminals refer to electronic
  • Portable terminals can include, for example,
  • mobile communication terminals personal digital assistants (PDA), portable music players, and portable music players, etc.
  • PDA personal digital assistants
  • portable music players portable music players
  • PMP multimedia players
  • MP3 players MP3 players
  • the mobile communication terminal is essentially a device designed to enable a
  • FIG. 1 is a block diagram illustrating a conventional mobile communication
  • the mobile communication terminal 100 having a camera
  • a main memory 140 for storing data
  • a display 145 for displaying images
  • a camera 150 for processing images
  • an image processing unit 155 for processing images
  • the high frequency processing unit 110 processes a high frequency signal, which is
  • the analog-to-digital converter 115 converts an analog signal, outputted from the
  • high frequency processing unit 110 to a digital signal and sends to the processor 125.
  • the digital-to-analog converter 120 converts a digital signal, outputted from the
  • processor 125 to an analog signal and sends to the high frequency processing unit 110.
  • the processor 125 controls the general operation of the mobile communication
  • the processor 125 can comprise a central processing unit (CPU) or a
  • the power supply 130 supplies electric power required for operating the mobile
  • the power supply 130 can include a terminal for coupling
  • the key input 135 generates key data for, for example, setting various functions or
  • the key input 135 can be embodied in the form of a key
  • the main memory 140 stores an operating system and a variety of data of the
  • the main memory 140 can be, for example, a '
  • the display 145 displays the operation status of the mobile communication terminal
  • the display 100 100 and an external image photographed by the camera 150.
  • the display 150 For example, the display
  • 145 can include an LCD panel.
  • the camera 150 photographs an external image (a photographic subject) and
  • the image processing unit 155 processes the external image inputted from the
  • the image processing unit 155 can perform functions such as color
  • camera 150 and the image processing unit 155 can be controlled by the processor 125.
  • the support memory 160 stores, for example, the external image processed by the
  • the mobile communication terminal 100 having a camera
  • processors i.e. a main processor and one or
  • mobile communication terminal 100 shown in FIG. 1 includes the processor 125 for
  • the image processing unit 155 for controlling the camera function.
  • the image processing unit 155 for controlling the camera function.
  • the processor 125 is controlled by the processor 125.
  • each processor is structured to be
  • the application processors each of which can be embodied as an independent
  • processor and is controlled by the main processor can take different forms depending on
  • the application processor for the camera function can process functions such
  • JPEG encoding and JPEG decoding As JPEG encoding and JPEG decoding, and the application processor for playing back
  • video files can process functions such as video file (e.g. MPEG4, DIVX, and H.264)
  • video file e.g. MPEG4, DIVX, and H.264
  • the application processor for playing back music files can
  • Each of these processors is individually coupled to a memory for storing the data
  • FIG. 2 is a coupling structure of a main processor, an application processor, each of
  • main processor 210 is coupled to a main memory 230 through a bus, and the application
  • processor 220 is coupled to an application memory 240 through a bus.
  • the application is coupled to an application memory 240 through a bus.
  • processor 220 is coupled to a display device 250 to have information, corresponding to
  • a bus refers to a common-purpose electric
  • a bus comprises a line for data
  • processor 220 will be referred to as an MP (Main Processor)- AP (Application
  • MP-MM Main Memory
  • processor 220 to the application memory 240 will be referred to as an AP-AM (Application Memory) bus.
  • AP-AM Application Memory
  • each of the processors 210 and 220 is independently
  • the main processor 210 reads the data stored in the main memory 210 .
  • bus i.e. a host interface
  • application processor 220 requests the application processor 220 and reads the data
  • processor 210 and the application processor 220, respectively, the main processor 210
  • the application processor 220 transmits the data stored in the application memory 240
  • processor 210 and the application processor 220, the more time each of the processors
  • 210 and 220 has to spend on the operation (i.e. memory access, data reading, and host
  • the main processor 210 reads and processes data stored
  • the application processor 220 then stores, reads and processes
  • the data (e.g. polygon data and texture data) received through the MP-AP bus in the
  • the application processor 220 is large, wasting the data communication time
  • the present invention provides a device having a shared memory and a method for
  • partitioning a storage area of the shared memory into a plurality of partitioned areas e.g. dedicated areas and a common area.
  • the present invention also provides a device having a shared memory and a method
  • the present invention also provides a device having a shared memory and a method
  • the present invention also provides a device having a shared memory and a method
  • processors can cross-access the common area.
  • the present invention also provides a device having a shared memory and a method
  • the access status information i.e. occupation status information
  • the access status information i.e. occupation status information
  • the present invention also provides a device having a shared memory and a method
  • application processor read the data by sequentially accessing the storage area in which
  • the data is written by the main processor.
  • an aspect of the present invention features a digital
  • processors share one memory, and/or a
  • memory device which is shared by a plurality of processors.
  • inventions can include processors in a quantity of "n" and a memory unit, which is
  • the processors in a quantity of "n" can include a main processor and application
  • control bus is controlled by a control signal received via the control bus.
  • the application processor can process data written in the common area by the main
  • the access status information can include at least one of read status information and
  • the memory unit can include access ports in a quantity of "n" corresponding to each
  • the storage area which is partitioned into the dedicated areas and the
  • the memory unit can generate and output the access status information by referring
  • the memory unit can generate and output the access status information by
  • processors is accessed to the common area, the processors stand by to access the
  • the area partition information which corresponds to a size or quantity of the
  • the storage area which is partitioned into dedicated areas and a common area
  • Another aspect of the present invention features a method of providing access status
  • a storage area of the memory can be partitioned into "n" dedicated areas, in which a storage area is individually allocated to each processor, and
  • the dedicated area can be exclusively occupied by a
  • processors at different unoverlapped times, "k" being a natural number greater than or
  • An independent control bus can be formed between a plurality of processors sharing
  • the plurality of processors can include a main processor and an application
  • the main processor via the control bus.
  • the access status information can include at least one of read status information and
  • the memory unit can include access ports in a quantity of "n" corresponding to each
  • the storage area which is partitioned into the dedicated areas and the
  • the memory unit can generate and output the access status information by referring
  • the memory unit can generate and output the access status information by
  • processors is accessed to the common area, the processors stand by to access the
  • the program which is readable by the
  • memory device can execute: determining whether any one processor is accessed to a
  • the memory device can be shared by a
  • the dedicated area can be exclusively occupied by a
  • processors at different unoverlapped times, "k" being a natural number greater than or
  • FIG. 1 shows a block diagram of a conventional mobile communication terminal
  • FIG. 2 shows a coupling structure of a main processor, an application processor,
  • FIG. 3 shows a coupling structure of a main processor, an application processor, a
  • FIG. 4 shows a memory unit in accordance with an embodiment of the present
  • FIG. 5 shows a memory unit in accordance with another embodiment of the present
  • FIG. 6 shows a flowchart of a process for controlling an access privilege on the
  • the first element can be any element that only to distinguish one element from the other.
  • the first element can be any element that only to distinguish one element from the other.
  • the first element can be any element that only to distinguish one element from the other.
  • any first processor e.g. a main
  • processor or a first application processor can write data, to be processed in a different, second processor (e.g. a second processor or the main processor), in a particular storage
  • the memory unit can control an access privilege such that the second
  • processor can access the storage area and read the data. Therefore, any additional
  • FIG. 3 is a block diagram showing a coupling structure of a main processor, an
  • FIG. 4 shows a memory unit in accordance with an
  • FIG. 5 shows a memory unit in accordance
  • main processor 210 and the application processor 220 share one memory unit 310.
  • processor 220 in accordance with a process command of the main processor 210.
  • main processor 210 can output, through the MP-AP bus, a control command for
  • coupled output device can vary depending on the function of the application processor
  • FIG. 3 shows one application processor 220, it shall be evident that the
  • FIG. 3 shows that only one
  • memory unit 310 is shared by a plurality of processors 210 and 220, the number of
  • shared memory units 310 can be increased or decreased depending on the need, and the
  • processors sharing the memory unit 310 can be different from one another. For example,
  • a first memory unit can be shared by the main processor and a first application
  • a second memory unit can be shared by the main processor and a second
  • the main processor 210 and the application processor 220 are identical to the main processor 210 and the application processor 220.
  • the main processor 210 is coupled to the memory unit 310 via an MP-SM (shared
  • a bus is a common-purpose electric pathway that is used to transmit
  • the main processor 210 can be a processor that controls the
  • a digital processing apparatus e.g. a portable terminal.
  • the application processor 220 which has received a process command from the main processor 210 via the MP-SM bus, access the memory unit 310 via an AP-SM bus
  • the application processor 220 can process the data written in the common area by the
  • application processor 220 can access the common area after the main processor 210
  • application processor 220 can be a processor dedicated to process MPEG4, 3-D graphic,
  • processor 220 are controlled by the main processor 210 and that the process operation
  • the back of the application processor 220 can be
  • peripheral devices other than the illustrated display device 250.
  • the memory unit 310 is shared by the coupled plurality of processors (i.e. the main
  • processor 210 and one or more application processors) and has access ports, the number
  • the memory unit 310 is shared by the main processor 210 and the
  • the memory unit 310 has 2 access
  • a first port is connected to the main processor 210, and a second port is connected to the
  • the memory unit 310 has one internal controller 410, there can be a
  • each of the processors 210 and 220 can use its own
  • the storage area of the memory unit 310 can be
  • storage areas can include dedicated areas, the number of which corresponds to the
  • the dedicated area is configured to control the number of installed processors, and at least one common area.
  • the dedicated area is configured to control the number of installed processors, and at least one common area.
  • the common area refers to an area to which all processors are
  • each processor to individually access each partitioned area (i.e. the dedicated area or the
  • the memory unit 310 can be partitioned into 2 dedicated areas (i.e. an area A 420 and an area B 430) and a common area 440, as shown in FIG. 4.
  • the memory unit 310 is, for example, an SDRAM, the usage of the storage area
  • 256Mbit SDRAM can be described as 8Mb x 8 bits x 4 banks. Two of these banks can
  • each one of the other two banks can be allocated to the area A 420, and each one of the other two banks can be allocated to
  • Each of the four banks may be allocated to the area A 420, the area B 430, a first
  • processor 220 can access the first common area and read the written data, once the main
  • processor 210 terminates the access to the first common area, and then access the
  • the method of providing access status information by the memory unit 310 will be described.
  • processor itself is accessed to the pertinent dedicated area.
  • each processor is restricted to access the common area 440 only if the other processor is
  • main processor 210 desires to write particular data (e.g. any one of the data to
  • control signals can include, for example, WE_A (Write Enable) for instructing
  • CS A Chip Select_A
  • the memory unit 310 If the main processor 210 is accessed to the common area, the memory unit 310
  • the access status information can be generated and outputted
  • the internal controller 410 which manages the access status of the common area 440.
  • the access status information can be outputted through a predetermined pin, or can be
  • write status information can be
  • the memory unit 310 is designed to write the received data in the
  • the memory unit 310 will output the high-state write status information
  • main processor 210 to access the common area 440.
  • the memory unit 310 outputs the access status information for each common area. For example, if the storage capacity is used
  • the main processor 210 terminates the
  • the memory unit 310 provides the
  • corresponding access status information (for example, to indicate that the access to the
  • first common area is terminated and that the second common area is to be accessed to
  • the application processor 220 can recognize that the first
  • the main processor 210 terminates its access to the memory unit 310, which
  • the application processor 200 that desires to read and use the data read the data (Data A) by transmitting address information (Addr A: the
  • control signals e.g. OE A (output enable) for OE A
  • CS_A chip select signal
  • the application processor 220 read and process the data written in the common area 440,
  • the main processor 210 can deliver a corresponding process instruction (e.g. address
  • the application processor 220 can use the access status
  • the common area 440 can be recognized to be accessible and
  • Rbusy_A readable if Rbusy_A, provided by the memory unit 310, is a first state (e.g. a low state).
  • Wbusy_A should be also the first state (e.g. a low state) in order for the
  • the memory unit 310 provides only the access
  • processor i.e. the processor that is not currently accessed to the common area.
  • the memory unit 310 i.e. the internal controller 410) provides the access status information, which tells for which operation (i.e. reading or
  • a processor 210 or 220 is accessed, to the common area 440. For this, it is
  • any one processor recognizes whether a common area 440 is accessible
  • processor is currently not accessed to the common area 440.
  • the internal controller 410 can output corresponding access status information (ST A_A
  • the read status information (Rbusy), corresponding to one of the processors, is in a high state.
  • the memory unit 310 can reduce the number of pins by
  • the memory unit 310 of the present invention As described with reference to FIGS. 4 and 5, the memory unit 310 of the present invention
  • invention can output the information on the status of accessing the common processor
  • the memory unit 310 i.e. the internal controller 410) has to recognize
  • the memory unit 310 can
  • processor has accessed the common area 440 can be used without restriction.
  • the size is divided into any sizes by the main processor 210 and/or the application processor 220 or that the size is configured to be
  • the data to be written is bigger than the size of the writable area.
  • memory unit 310 can be configured and managed by the main processor 210, and the
  • the address information can be
  • the memory unit 310 can be recognized by each processor during the booting process of
  • the digital processing apparatus e.g. a portable terminal.
  • FIG. 6 shows a data flow of controlling the privilege to access the common area in
  • step 610 the memory unit 310 outputs access status
  • a write status signal and a read status signal (refer to FIG. 4) or an
  • information being inputted to the main processor 210, can include the information on
  • the memory unit 310 is shared by a plurality of processors, the memory unit 310
  • the access status information (refer to
  • FIGS. 4 and 5 outputted to each processor can be identical. This is because, if the
  • common area 440 is recognized to be already accessed by a processor due to the access
  • area 440 can be accessed after the access by the other processor is terminated.
  • step 620 the main processor 210 determines whether the common area 440 is
  • the main processor 210 can recognize
  • the write status signal and the read status signal e.g. Wbusy_B or Rbusy_B of FIG.
  • an access status signal (e.g. STA B of FIG. 5).
  • step 620 if it is determined that the common area
  • the main processor 210 accesses the common area 440, in step 630, to write or read data,
  • step 640 Once the main processor 210 accesses the common area 440, the memory
  • the memory unit 310 determines, in step 650, whether the main processor 210 has
  • step 610 is repeated to generate and output updated access status information.
  • processor by simply transferring between the processors the privilege to access the
  • the present invention can increase the efficiency of memory use
  • the present invention can also minimize the duration of data transmission between
  • the processors by configuring the common area to be accessible by each of the processors.
  • the present invention can also optimize the operation speed and efficiency of each
  • the present invention can also simplify a control sequence of each of the processors
  • the present invention can also maximize the speed of data delivery by having the
  • main processor sequentially write data in the common area, which is partitioned into n

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

L'invention concerne un dispositif présentant une mémoire partagée, et un procédé utilisant cette mémoire partagée pour fournir des informations d'état d'accès. Un processus numérique de l'invention met en oeuvre 'n' processeurs et une unité de stockage. L'unité de stockage, couplée à chaque processeur par l'intermédiaire d'un bus, est partitionnée en 'n' zones spécialisées dans lesquelles une zone de stockage est attribuée individuellement à chaque processeur, et en 'm' zones communes; et produit à destination de chaque processeur des informations d'état d'accès indiquant si un processeur a accédé à la zone commune. Grâce au procédé de l'invention, la séquence de commande de chaque processeur peut être simplifiée au maximum par le fait que la mémoire partagée produit des informations d'état d'accès à la zone commune.
PCT/KR2007/001140 2006-03-08 2007-03-08 Dispositif présentant une mémoire partagée et procédé utilisant cette mémoire partagée pour fournir des informations d'état d'accès WO2007102712A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2006-0021902 2006-03-08
KR1020060021902A KR100700040B1 (ko) 2006-03-08 2006-03-08 공유 메모리를 구비한 장치 및 공유 메모리 억세스 상태정보 제공 방법

Publications (1)

Publication Number Publication Date
WO2007102712A1 true WO2007102712A1 (fr) 2007-09-13

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PCT/KR2007/001140 WO2007102712A1 (fr) 2006-03-08 2007-03-08 Dispositif présentant une mémoire partagée et procédé utilisant cette mémoire partagée pour fournir des informations d'état d'accès

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KR (1) KR100700040B1 (fr)
WO (1) WO2007102712A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5884055A (en) * 1996-11-27 1999-03-16 Emc Corporation Method and apparatus including a shared resource and multiple processors running a common control program accessing the shared resource
WO2003085524A2 (fr) * 2002-04-04 2003-10-16 Infineon Technologies Ag Architecture amelioree a memoire partagee
US6738888B2 (en) * 2000-08-21 2004-05-18 Texas Instruments Incorporated TLB with resource ID field
KR20040106778A (ko) * 2003-06-11 2004-12-18 엘지전자 주식회사 복수개의 프로세서를 갖는 이동통신 단말기의 메모리 공유장치 및 그 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5884055A (en) * 1996-11-27 1999-03-16 Emc Corporation Method and apparatus including a shared resource and multiple processors running a common control program accessing the shared resource
US6738888B2 (en) * 2000-08-21 2004-05-18 Texas Instruments Incorporated TLB with resource ID field
WO2003085524A2 (fr) * 2002-04-04 2003-10-16 Infineon Technologies Ag Architecture amelioree a memoire partagee
KR20040106778A (ko) * 2003-06-11 2004-12-18 엘지전자 주식회사 복수개의 프로세서를 갖는 이동통신 단말기의 메모리 공유장치 및 그 방법

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