WO2007008173A1 - Structure semi-conductrice destinée à des transistors ayant une excursion infraliminaire et procédés de fabrication de celle-ci - Google Patents

Structure semi-conductrice destinée à des transistors ayant une excursion infraliminaire et procédés de fabrication de celle-ci Download PDF

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Publication number
WO2007008173A1
WO2007008173A1 PCT/SG2006/000093 SG2006000093W WO2007008173A1 WO 2007008173 A1 WO2007008173 A1 WO 2007008173A1 SG 2006000093 W SG2006000093 W SG 2006000093W WO 2007008173 A1 WO2007008173 A1 WO 2007008173A1
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Prior art keywords
transistor
region
dopant
type
source
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PCT/SG2006/000093
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English (en)
Inventor
Eng Huat Toh
Yee Chia Yeo
S. Samudra Ganesh
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National University Of Singapore
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Priority to TW095124835A priority Critical patent/TW200707730A/zh
Publication of WO2007008173A1 publication Critical patent/WO2007008173A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Definitions

  • the present invention relates to the field of semiconductor devices and circuits, and more particularly, to semiconductor devices, inverters, integrated ciruit chips, and methods of manufacturing such devices, and the use of such devices in integrated circuits.
  • CMOS Complementary Metal Oxide Semiconductor
  • Reducing the supply voltage V DD helps to contain or reduce the power consumption, but if the transistor threshold voltage V 7 - is not correspondingly reduced, the gate overdrive V G - V 7 -, where V 6 is the maximum gate voltage and is equal to Vbo. becomes smaller. A smaller gate overdrive leads to reduced speed performance.
  • V 7 reduction usually accompanies transistor scaling and supply voltage reduction.
  • the reduction of V 7 - results in an increase in the transistor off-state leakage current, which leads to an increase in power consumption.
  • the subthreshold swing S for a. conventional CMOS field-effect transistor (FET) is above 60 mV per decade at room temperature, and this is related to the Ferrhi-Dirac distribution of the carrier energy.
  • planar impact ionization metal-oxide-semjconductor (I- MOS) structure that modulates the breakdown voltage and the current of a gated p-i-n structure can realize a subthreshold swing S of less than 60 mV/dscade at room temperature.
  • I- MOS metal-oxide-semjconductor
  • planar I-MOS device structure also suffers from a number of other deficiencies.
  • planar I-MOS structure requires a laterally-positioned impact ionization region (l-region) for carrier multiplication effect, and the l-region occupies an additional area.
  • additional silicon area leads to a trade-off in layout efficiency and renders the device design unattractive.
  • the prior art planar I-MOS structure employs lithography techniques to define the l-region.
  • a misalignment error in lithography directly translates to an error in the length of the l-region, which affects the electrical performance of the device. Lithographic errors could therefore affect the operational uniformity of I-MOS transistors in a integrated chip.
  • the present invention thus seeks to address the above deficiencies through novel impaction ionization metal-oxide-semiconductor (I-MOS) device structure designs and methods of manufacture.
  • I-MOS impaction ionization metal-oxide-semiconductor
  • a semiconductor structure comprising a substrate structure; a gate stack formed on said substrate structure ⁇ drain region of a first dopant type formed in the substrate structure adjacent said gate stack; a source structure formed on said substrate structure adjacent said gate stack, the source structure comprising a source region of a second dopant type and a first region of a dopant concentration below it) 18 crrf 3 disposed between the source region and the substrate structure. 6 000093
  • the substrate structure may be a bulk semiconductor or a semiconductor-on-insulator substrate.
  • the bulk semiconductor may comprise elemental or compound semiconductors selected from a group comprising silicon, germanium, carbon, gallium arsenide, indium phosphide, and indium antimonide.
  • the semiconductor-on-insulator substrate may comprise at least one semiconductor layer formed on an insulator layer, said semiconductor layer comprising any one or more of a group consisting of silicon, germanium, carbon, or compound semiconductors.
  • the semiconductor-on-insulator may comprise a plurality of semiconductor layers.
  • the semiconductor layers may comprise a silicon-germanium layer formed on a silicon layer and said silicon layer formed on a silicon oxide layer.
  • the gate stack may comprise a gate electrode formed on a gate dielectric layer.
  • the gate electrode may comprise any one or more of a group consisting of polycrystalline silicon, an elemental metal, a metal alloy, a metal nitride, a metal suicide or a metal oxide.
  • the gate dielectric layer may comprise any one or more of a group consisting of silicon dioxide, nitraded silicon dioxide (SiON), hafnium oxide (HfO 2 ), hafnium oxynitride (HfON), hafnium silicate (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La 2 O 3 ) or any dielectric with a permittivity (k) value larger than 6.
  • the source structure may comprise elemental, compound semiconductors, IH-V semiconductors, binary compound semiconductors, ternary compound semiconductors or alloy semiconductors selected from a group comprising silicon, germanium, gallium arsenide, indium arsenide, indium antimonide, indium phosphide, gallium indium arsenide, gallium indium antimonide, silicon-germanium, silcon-germanium-carbon, silicon-carbon, and germanium-carbon.
  • the first region may comprise elemental, compound semiconductors, IH-V semiconductors, binary compound semiconductors, ternary compound semiconductors or alloy semiconductors selected from a group comprising silicon, germanium, gallium arsenide, indium arsenide, indium antimonide, indium phosphide, gallium indium arsenide, gallium indium antimonide, silicon-germanium, silcon-germanium-carbon, silicon-carbon, and germanium-carbon.
  • the semiconductor structure may further comprise spacers oppositely adjacent said gate electrode.
  • the first dopant type may be n-type dopant and the second dopant type may be p-type dopant.
  • the first dopant type may be p-type and the second dopant type may be n-type dopant.
  • the source region may be formed by a combined deposition and in-situ doping.
  • the semiconductor structure may further comprise a second region of said first dopant type formed on said drain region.
  • the semiconductor structure may further comprise a conductive metal suicide material formed on said source region and said drain region.
  • the first region may be doped with a second dopant type.
  • the first region may have a thickness in the range of approximately 1 nm to approximately 100 nm.
  • the substrate structure may comprise a recessed portion, with respect to a surface of the drain region, at an interface between the first region and the substrate structure.
  • the substrate structure may comprise silicon and said first region may comprise silicon, germanium, or both.
  • a method of forming a semiconductor structure comprising the steps of providing a substrate structure; forming a gate stack on the substrate structure; forming a drain region of a first dopant type in said substrate structure adjacent said gate stack; forming a source structure on said substrate structure adjacent said gate stack, the source structure comprising a source region of a second dopant type and a first region of a dopant concentration below 10 18 cm "3 disposed between the source region and the substrate structure.
  • the method may further comprise the step of forming spacers adjacent said gate stack.
  • the step of forming said gate stack may further comprise the steps of forming a gate dielectric layer; and forming a gate electrode.
  • a hardmask may be formed on the gate electrode, the hardmask comprising a dielectric material.
  • the step of forming said source structure may comprise a selective epitaxy step.
  • the selective epitaxy step may further comprise in-situ doping.
  • the selective epitaxy step may comprise utilising any one or more of a group consisting of silane, disilane, methyl-silane, germane, and chlorine.
  • the method may further comprise the step of etching said substrate structure prior to forming said source structure.
  • the substrate structure arid the source structure may comprise any one or more of a group consisting of silicon, germanium, Garbon of compound semiconductors.
  • the method may further comprise the steps of forming a conductive material over said source region and said drain region; depositing an insulating layer above said conductive material; and forming contacts to said source region, said drain region, and said gate stack.
  • the steps of forming said drain region and said source structure may comprise an ion implantation step.
  • the first dopant type may be n-type and said second dopant type may be p-type.
  • the first dopant type may be p-typ ⁇ e and said second dopant type may be n-type.
  • an inverter comprising a first transistor comprising a gate electrode; a drain region of a first dopant type; and a source region of a first dopant type, said first transistor source region connected to a first power supply and said first transistor drain region connected to an output terminal; a second transistor comprising a substrate structure; a gate stack formed on said second transistor substrate structure; said second transistor gate stack further comprising a gate electrode; a drain region of a second dopant type formed in said second transistor substrate structure adjacent sajd second transistor gate stack; and a source structure formed on said second transistor substrate structure adjacent said second transistor gate stack, said second transistor source structure comprising a source region of a first dopant type and a first region of a dopant concentration below 10 18 cm "3 disposed between said second transistor source region and said second transistor substrate structure, said second transistor source region connected to a second power supply and said second transistor drain region connected to said output terminal; and an input terminal connected to the gate electrodes of said first transistor comprising a gate electrode; a drain region
  • the first dopant type may be p-type dopant
  • said second dopant type may be n- type dopant.
  • the first dopant type may be n-type dopant, and said second dopant type may be p- type dopant.
  • an inverter comprising a first transistor comprising a substrate structure; a gate stack formed on said first transistor substrate structure; said first transistor gate stack further comprising a gate electrode; a drain region of a first dopant type formed in said first transistor substrate structure adjacent said first transistor gate stack; and a source structure formed on said first transistor substrate structure adjacent said first transistor gate stack, said first transistor source structure comprising a source region of a second dopant type and a first region of a dopant concentration below 10 18 cm "3 disposed between said first transistor source region and said first transistor substrate structure, said first transistor source region connected to a first power supply and said first transistor drain region connected to an output terminal; a second transistor comprising a substrate structure; a gate stack formed on said second transistor substrate structure; said second transistor gate stack further comprising a gate electrode; a drain region of a second dopant type formed in said second transistor substrate structure adjacent said second transistor gate stack; and a source structure formed on said second transistor substrate structure adjacent said second transistor gate
  • the first dopant type may be p-type dopant
  • said second dopant type may be n- type dopant.
  • the first dopant type may be n-type dopant, and said second dopant type may be p- type dopant.
  • an integrated circuit chip comprising a plurality of first transistors, each first transistor comprising a first gate electrode; a first drain of a first dopant type, and a first source of a first dopant type; and a plurality of second transistors, each second transistor comprising a substrate structure; a gate stack formed on said second transistor substrate structure; said second transistor gate stack further comprising a gate electrode; a drain region of a second dopant type formed in said second transistor substrate structure adjacent said second transistor gate stack; and a source structure formed on said second transistor substrate structure adjacent said second transistor gate stack, said second transistor source structure comprising a source region of a first dopant type and a first region of a dopant concentration below 10 18 cnrf 3 disposed between said second transistor source region and said second transistor substrate structure.
  • the first dopant type may be p-type dopant
  • said second dopant type may be n- type dopant.
  • the first dopant type may be n-type dopant, and said second dopant type may be p- type dopant.
  • an integrated circuit chip comprising a plurality of first transistors, each first transistor comprising a substrate structure; a gate stack formed on said first transistor substrate structure; said first transistor gate stack further comprising a gate electrode; a drain region of a second dopant type formed in said first transistor substrate structure adjacent said first transistor gate stack; and a source structure formed on said first transistor substrate structure adjacent said first transistor gate stack, said first transistor source structure comprising a source region of a first dopant type and a first region of a dopant concentration below 10 18 cr ⁇ f 3 disposed between said first transistor source region and said first transistor substrate structure; and a plurality of second transistors, each second transistor comprising a substrate structure; a gate stack formed on said second transistor substrate structure; said second transistor gate stack further comprising a gate electrode; a drain region of a first dopant type formed in said second transistor substrate structure adjacent said second transistor gate stack; and a source structure formed on said second transistor substrate structure adjacent said second transistor gate stack, said second transistor source
  • Figure 1 shows a cross sectional view of an L-shaped Impact Ionization Metal-Oxide- Semiconductor (LI-MOS) transistor device built in accordance with one embodiment of the present invention.
  • LI-MOS Impact Ionization Metal-Oxide- Semiconductor
  • Figure 4 shows a plot of the simulated drain current I 0 (A/ ⁇ m) against gate voltage V G (V).
  • the source voltage V s of Si LI-MOS and Ge LI-MOS is at -5.25 V and -1.8 V, respectively.
  • Figure 5 shows a plot of the simulated gate current 1 G (A/ ⁇ m) against gate voltage V G (V).
  • the source voltage V s of Si LI-MOS and Ge LI-MOS is at -5.25 V and -1.8 V, respectively.
  • FIGS 6 to 11 illustrate fabrication of embodiments of L
  • Figure 12 shows a cross sectional view of an L-shaped Impact Ionization Metal-Oxide- Semiconductor (LI-MOS) transistor device built in accordance with one embodiment of the present invention.
  • LI-MOS Impact Ionization Metal-Oxide- Semiconductor
  • FIGS 13 to 14 illustrate fabrication of embodiments of Ll-MOS transistor devices built in accordance with the present invention.
  • Figure 15 shows a cross sectional view of an L-shaped Impact Ionization Metal-Oxide- Semiconductor (LI-MOS) transistor device built in accordance with one embodiment of the present invention.
  • Figure 16 shows a cross sectional view of an L-shaped Impact Ionization Metal-Oxide- Semiconduetor (U-MOS) transistor device built in accordance with one embodiment of the present invention.
  • LI-MOS L-shaped Impact Ionization Metal-Oxide- Semiconductor
  • U-MOS L-shaped Impact Ionization Metal-Oxide- Semiconduetor
  • Figure 17 shows a cross sectional view of an L-shaped Impact Ionization Metal-Oxide- Semiconductor transistor device 15 built in accordance with one embodiment of the present invention.
  • Figure 18 shows the electrical circuit symbols for a LI-MOS device built in accordance with an embodiment of the present invention.
  • Figures 19A to 19C shows basic electrical circuits comprising a LI-MOS device built in accordance with an embodiment of the present invention.
  • Figures 2OA and 2OB show inverter circuits comprising a MOS device and a LI-MOS device built in accordance with an embodiment of the present invention.
  • Figure 21 A to 21 C shows NAND logic gate circuits comprising a MOS device and a Ll- MOS device built in accordance with an embodiment of the present invention.
  • the embodiments described provide semiconductor devices and circuits, and more particularly, semiconductor devices with improved subthreshold swing, methods of manufacturing such devices, and the use of such devices in integrated circuits.
  • Figure 1 shows a cro ' ⁇ s sectional view of an. L-shaped Impact Ionization Metal-Oxide- SemiGonductor (LI-MOS) transistor device 10O fabricated in accordance with one embodiment of the present invention, which can provide a semiconductor device with improved subthreshold swing.
  • LI-MOS Impact Ionization Metal-Oxide- SemiGonductor
  • the device 100 comprises a gate stack 102 formed on a substrate structure 104.
  • the substrate structure 104 comprises a first semiconductor layer 106 formed above an insulation layer 108 on a wafer substrate 110.
  • the first semiconductor layer 106 and the second semiconductor layer 126 may have a crystalline or amorphous structure and may comprise of an elemental semiconductor or compound semiconductor.
  • Elemental semiconductors include silicon, and germanium.
  • Compound semiconductors or Hl-V semiconductors include binary compound semiconductors such as gallium arsenide, indium arsenide, indium antimonide, indium phosphide, and ternary compound semiconductors such as gallium Indium arsenide and gallium indium antimonide.
  • first semiconductor layer and the second semiconductor layer each may comprise alloy semiconductors, such as silicon-germanium (SiGe), silcon-germanium-carbon (SiGeC), silicon-carbon (SiC), and germanium-carbon (GeC).
  • alloy semiconductors such as silicon-germanium (SiGe), silcon-germanium-carbon (SiGeC), silicon-carbon (SiC), and germanium-carbon (GeC).
  • the gate stack 102 comprises a gate insulator or gate dielectric layer 112 formed on the first semiconductor layer 106, and a gate or gate electrode 114 formed above the gate dielectric layer 112. Spacers 116a and 116b are formed on opposite sides of the gate electrode 114. A second semiconductor layer 126 is formed above the substrate Structure 104 adjacent to the spacer 116a.
  • a source structure comprising a heavy doped source region 132 is formed within the second semiconductor layer 126, the second semiconductor layer 126 itself having a dopant concentration below 10 18 cm “3 .
  • the heavy doped source region 132 is disposed nearer to the surface of the second layer 126.
  • the source region 132 will be p+ doped, while for a p-channel device 100, the source region 132 will be n+ doped.
  • a drain region 122 will also be formed within the first semiconductor layer 106 extending, below the spacer 116b so that the drain region 122 is formed within the substrate structure 104.
  • the drain region 122 will be n+ doped, while for a p-channe
  • a conducting channel (not shown), spanning from the source region 132 to the drain region 122 will be formed when the device 100. is suitably biased.
  • an L-shaped impact ionization region 136 extends vertically below the source region 132, and horizontally below the spacer 116a.
  • prior art planar I-MOS structures have the impact ionization region occurring in the region 113 directly beneath the gate dielectric layer 112 as well as the intrinsic semiconductor region 106, Thus for the device 100, the impact ionization region 136 has been significantly shifted away from most of the region 113. While there is still carrier activity in the region 113, the carrier activity is not of the hot carrier activity type due to the low electric field in the region 113.
  • the formation of the L-shaped impact ionization region 136 in the present embodiment arises due to the strong electric field present in the impact ionization region 136.
  • the L-shaped impact ionization region 136 thus reduces the damaging effects impact ionization has on the gate dielectric layer 112 and further greatly reduces hot carrier degradation effects that are more present in current i-MOS structures.
  • the impact ionization region 136 can also be scaled vertically instead of horizontally thus allowing a compact design without sacrificing silicon (substrate) area. Vertical scaling of the impact ionization region will be detailed (ater with respect to Figures 7 to 12.
  • the first semiconductor layer 106 and the second semiconductor layer 126 comprises silicon.
  • the wafer substrate 110 comprises bulk silicon, while the insulation layer 108 comprises silicon dioxide.
  • the gate electrode 114 comprises polysilicon.
  • the gate dielectric layer 112 comprises silicon dioxide.
  • the spacers 116a and 116b comprises silicon nitride (SiN).
  • the gate electrode 114 comprises any other conductive gate materials like elemental metals (e.g. Ta, Ti, Hf, Ru, Mo, W, Pt, Ni, etc.), metal alloys (e.g. TaPt, TaHf, NiHf, etc.), metal nitrides like TiN, HfN, WN, MoN, and TaN, metal suicides (e.g. NiSi, CoSi, RSi, HfSi, etc.), metal oxides ⁇ e.g. RuO 2 , IrO 2 , etc.), or combinations thereof.
  • the first semiconductor layer 106 and the second semiconductor layer 126 comprise silicon germanium, silicon or germanium, carbon or compound semiconductors.
  • the gate dielectric layer 112 comprises any dielectric insulator such as hafnium oxide (HfO 2 ), hafnium oxynitride (HfON), hafnium silicate (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La 2 O 3 ) or any dielectric with a permittivity (k) value larger than 6.
  • the spacers 116a and 116b comprise silicon oxynitride (SiON), silicon dioxide (SiO 2 ), Si ⁇ N 4 , high-k materials or combinations thereof. Different combination of materials can also be used to enhance the operation of the device.
  • the source region 132 and the drain region 122 may additionally be strapped with a conductive material such as metal suicides to reduce the electrical resistance.
  • a metal suicide commonly used to reduce the resistance in source and drain regions is nickel suicide (NiSi).
  • the gate electrode 114 comprises polysilicort with a nitride hard mask on top.
  • the nitride hard mask comprises a material selected from a group comprising silicon oxide, silicon oxynitride and any dielectric material.
  • the first semiconductor layer 106 can comprise a plurality of sub-layers, the sub-layers comprising silicon, germanium, carbon, or combination thereof, or compound semiconductors.
  • the first semiconductor layer 106 may comprise two sub-layers such as a silicon-germanium sub-layer formed on a silicon sub-layer. Having two sub-layers can give the advantage of strain control and bandgap engineering at the impact ionization region 136 below the spacer 116a.
  • the second semiconductor layer 126 may also be comprised of a plurality of sub-layers comprising elemental semiconductors, compound semiconductors, or alloy semiconductors.
  • the second semiconductor layer may comprise a germanium layer formed on a silicon-germanium layer.
  • the substrate structure 104 is a bulk semiconductor or a semiconductor-on-insulator substrate.
  • Bulk semiconductor substrates comprise elemental semiconductors such as silicon, germanium, carbon, or compound semiconductors such as gallium arsenide, indium phosphide, indium antimonide, or combinations thereof.
  • approximate thicknesses for the insulation layer 112, the first semiconductor layer 106, the second semiconductor layer 126 and the gate electrode 114 are 2 ⁇ A, 6O ⁇ A, 500A and 1000 A respectively.
  • the gate electrode 114 has a width W 114 of approximately 60nm.
  • the L-shaped length L 136 of the L-shaped impact ionization region 136 is approximately 60 nm.
  • the widths W 116a and W 116b of the spacers 116a and 116b are respectively approximately 40nm each.
  • the spacer widths W 1163 and W 116b are preferably chosen to be thick enough to keep hot carriers occurring within the impact ionization region 136 from reaching the gate dielectric layer 112.
  • the spacer widths W 1163 and Wii 6b are preferably chosen to be not too thick as this will increase the resistance of the impact ionization region 136 and thereby induce a greater voltage drop across the impact ionization region 136.
  • the dimensions of the spacer widths W 1163 and W 116b depend on the technology application.
  • Spacer widths W 1163 and W 116b are preferably between approximately 2 nm and approximately 200nm, and more preferably between about 2 nm and 100 nm, and even more preferably between about 2 nm and 50 nm. It should be noted that the spacer width generally scales with technology generations.
  • the thickness of the gate dielectric or insulation layer 112 can range from about 0.4 nm to about 20 nm, more preferably from about 0.4 nm to about 5 nm, and even more preferably from about 0.4 nm to about 1.5 nm.
  • the thickness of the gate electrode may be about 10 nm to about 200 nm, and more preferably about 10 nm to 100 nm.
  • the thicknesses of the first sub-layer and the second sub-layer are each preferably between about 1 nm to about 50 nm. In another embodiment the first sub-layer and the second sub-layer are each between about 1 nm to about 100 nm.
  • Table 1 Device materials and parameters used for first simulation set
  • Figure 2 shows a schematic of band-to-band carrier generation rate contour plots 201 occurring at the impact ionization region 136 of an n-channel device 100 of Figure 1.
  • the device materials and parameters of the n-channei device 100 used are those summarized in table 1.
  • Figure 2 has been simulated using Synopsys (TCAD) tools.
  • TCAD Synopsys
  • a thin layer of liner 212 between the gate eleGtrode 114 and the spacers 116a and 116b is formed.
  • the liner 212 comprises silicon dioxide.
  • the highest band-to-band generation region referred to as the hot carrier activity region 203
  • the hot carrier activity region 203 occurs at the edge of the spacer 116a.
  • current density is highest at the corner of the liner 212 corresponding to the area below the spacer 116a.
  • the hot carrier activity region 203 does not occur in the region below the gate dielectric layer 112, little hot carriers will be injected into the gate electrode 114 and the gate dielectric layer 112, therefore reducing the effect of hot carrier degradation on the gate dielectric layer 112 and the gate electrode 114.
  • most of the hot carrier activity region 203 occurs in the vertical area adjacent to the spacer 116a and away from the gate dielectric 112.
  • Figure 3 shows a schematic of holes concentration contour plots 301 generated by ' impact ionization from hot electrons occurring at the impact ionization region 136 of an n-bha ⁇ nel device 100 of Figure 1.
  • the device materials and parameters of the n- channel device 100 used are those summarized in table 1.
  • Figure 3 has been simulated using Synopsys (TCAD) tools.
  • the lowest holes concentration is 10 16 cm “3
  • the highest holes concentration is 10 19 cm "3 .
  • Figure 4 shows a plot of the simulated drain current I 0 (A/ ⁇ m) against gate voltage V G (V).
  • the curve 401 represents the semiconductor device 100 of Figure 1 using device materials and dimensions tabulated in table 1.
  • the curve 402 represents the semiconductor device 100 of Figure 1 using device materials and dimensions tabulated in table 2.
  • the operating conditions for both curves are as follows: source voltages V 5 biased at -5.25V and -1.8V, respectively, for silicon (Table 1 ) and germanium (Table 2) LI-MOS devices; and both. drain voltages V D being grounded.
  • Both curves show that a subthreshold slope of less than 5mV/dec with a low Wl ⁇ ratio and a threshold voltage V r of 0.10V can be achieved.
  • the silicon based and the germanium based devices 100 have a subthreshold swing of 4.5 mV/decade and 0.2 mV/decade, respectively.
  • Figure 5 shows a plot of the simulated gate current I G (A/ ⁇ m) against gate voltage V G (V).
  • the gate current I G reflects the hot electrons flow as a function of gate voltage V G .
  • the curve 501 represents. the device 100 of Figure 1 using device materials and dimensions tabulated in table 1.
  • the curve 502 represents the semiconductor device 100 of Figure 1 using device materials and dimensions tabulated in table 2.
  • the operating conditions for both curves are as follows: source voltages V 5 biased at - 5.25V and -1.8V, respectively, for silicon and germanium LI-MOS devices; and both drain voltages V D being grounded.
  • the germanium based device 100 has a lower carrier injection current to the gate electrode 114 even though the germanium based device 100 has a higher impact ionization rate than the silicon based device 100.
  • the gate currents in the silicon based device 100 and the germanium based device 100 can be considered negligible as they are in the order of below 1 Q "15 A/ ⁇ m. The hot carrier reliability of the device 100 can thus be appreciated.
  • Figure 6 shows a cross sectional view of an L-shaped Impact Ionization Metal-Oxide- Semiconductor (LI-MOS) transistor device 600 built in accordance with one embodiment of the present invention.
  • LI-MOS Impact Ionization Metal-Oxide- Semiconductor
  • the device structure 600 comprising a gate stack 602 formed on a substrate structure 604
  • the substrate structure 604 is a semiconductor- on-insulator substrate comprising a first semiconductor layer 606 formed on an insulation layer 608 on a wafer substrate 610.
  • the gate stack 602 comprises a gate insulator or gate dielectric layer 612 formed on the first semiconductor layer 606, and the gate or gate electrode 614 formed above the. gate dielectric layer 612.
  • the gate electrode 614 may comprise of a hard mask at the top surface that could be retained during subsequent selective epitaxy step and ion implantation step.
  • the hardmask may comprise one or more layers of silicon dioxide, silicon oxynitride, or any dielectric material.
  • Spacers 616a and 616b are formed on opposite sides of the gate electrode 614. It will be appreciated by the person skilled in the. art that the device structure 600 can be formed using known fabrication processes to fabricate a gate stack with adjacent spacers, e.g. employing lithographic processes, etching processes, and deposition processes such as sputtering, chemical vapour deposition (CVD) 1 and epitaxial growth.
  • CVD chemical vapour deposition
  • the first semiconductor layer 606 comprises silicon.
  • the wafer substrate 610 comprises bulk silicon, while the insulation layer 608 comprises silicon dioxide.
  • the gate electrode 614 comprises polysilicon with a nitride hard mask on top.
  • the gate dielectric layer 612 comprises silicon dioxide.
  • the spacers 616a and 616b comprise silicon nitride.
  • the nitride hard mask comprises a material selected from a group comprising silicon oxide, silicon oxynitride and any dielectric material. However, it will be appreciated that different materials may be used in different embodiments.
  • the substrate structure 604 comprises a bulk semiconductor substrate.
  • the spacers 616a and 616b can comprise materials such as SiON 1 Si 3 N 4 , SiO 2 , or a high-k material.
  • an optional oxide layer 618 is deposited over the device structure 600, in the example embodiment using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD).
  • the oxide layer 618 can be used to prevent ion channeling during a subsequent ion implantation step.
  • a photo resist 620 is then deposited and patterned using lithography techniques known in the art so that it is above the first semiconductor layer 606 on one side of the gate stack 602 and extending above one of the spacers 616a and above a portion of the gate electrode 614.
  • a doping step by ion implantation, plasma immersion ion implantation or diffusion source is performed to form a drain region 622 in the first semiconductor layer 606 in areas not covered by the photo resist 620, and extending below the spacer 616b.
  • n+ dopants will be used while to obtain a p-channel device, p+ dopants will be used.
  • a mask 624 is formed.
  • the mask 624 which preferably comprises silicon oxide, covers the drain region 622, and exposes the substrate region on the opposing side of the gate stack, as shown in Figure 6C.
  • the silicon oxide mask 624 may be formed by depositing silicon oxide over the device structure, patterning a photo resist (not shown) to cover the silicon oxide over the drain region 622, etching the uncovered silicon oxide, and removing the photo resist.
  • a second semiconductor layer 626 is then epitaxially grown above the exposed surface portion of the first semiconductor layer 606. The.
  • the epitaxial growth of the second semiconductor layer 626 employs a selective epitaxy process which uses any one or more of a group of gases consisting of silane, disilane, methyl-silane, germane, and chlorine, depending on the material of the second semiconductor layer 626.
  • the gases silane, disilane, methyl-silane, or germane may be mixed with a carrier gas such as hydrogen or argon.
  • the second semiconductor layer 626 comprises silicon and germanium, however it will be appreciated that other semiconductor materials may be used in different embodiments.
  • the mask 624 is removed by a suitable etch. Jn the preferred embodiment, the etch employs HF.
  • An optional oxide layer 628 is formed using LPCVD or PECVD.
  • Photo resist 630 is then formed one side of the gate stack 602 extending above the drain region 622, the spacer 616b and above a portion of the gate electrode 614, as shown in Figure 6D.
  • a doping step by ion implantation* plasma ion implantation or diffusion source is performed to form a heavy-doped source region 632 in the second semiconductor layer 626.
  • p+ dopants will be used while to obtain a p- channel device, n+ dopants will be used.
  • Figure 6E shows the resulting structure 634 after removal by chemical resist stripping (CRS) or plasma resist stripping (PRS) of the photo resist 630 and the oxide layer 628.
  • the device structure 634 has an L-shaped impact ionization region 636 extending vertically below the source region 632, and horizontally below the spacer 616a.
  • the device structure 634 can be designed such that the hot carrier concentration in the impact ionization region 636 does not extend below the gate dielectric layer 612, thus avoiding damage to the gate dielectric that may be caused by the hot carriers.
  • the overall length or dimension of the impact ionization region 636 between the source region 632 and the drain region 622 can be readily controlled or varied during the fabrication of the device structure 634. This is because the vertical portion of the impact ionization region 636 can be very accurately controlled through the epitaxial growth of the second semiconductor layer 626 (see figure 6C) on the one hand, and control of the doping process to form the source region 632 (see Figure 6D), Also, the L-shaped impact ionization region 636 allows for a compact design without sacrificing silicon (substrate) area.
  • the fabrication process described thus far may be slightly modified while still achieving the structure 634 of Figure 6E.
  • the formation of the second semiconductor layer 626 by selective epitaxy and the doping of the source region 632 may preceed the formation of the drain region 622.
  • the device structure 634 is then subjected to annealing and a suitable Back-End-Of- Line process (BEOL) to form the finished LI-MOS transistor device.
  • BEOL Back-End-Of- Line process
  • the BEOL process includes first, a partial or full silicidatioh of the source region 632, drain region 622, and gate electrode 614.
  • a silicon nitride contact etch-stop layer is deposited, and an interlayer dielectric comprising silicon dioxide is deposited. This is followed by contact etching, and a metal such as tungsten is deposited to form the via.
  • a damascene process is then employed to form metal lines to connect various devices. Damascene processes Known in the art, such as dual damascene or single damascene processes, may be employed.
  • the starting device structure 700 is the same as the starting device structure 600 shown in Figure 6A.
  • the same numerals have been used to indicate the same layers.
  • an optional oxide layer 713 is deposited over the device structure 700, in the example embodiment using LPCVD or PECVD.
  • a photo resist 720 is then deposited and patterned using lithography techniques known in the art so that it is above the first semiconductor layer 606 on one side of the gate stack 602 and extending above one of the spacers 616a and above a portion of the gate electrode 614.
  • a doping step by ion implantation, plasma ion implantation or diffusion source is performed to form a drain region 722 in the first semiconductor layer 606 in areas not covered by the photoresist 720, and extending below the spacer 616b.
  • n+ dopants will be used while to obtain a p-channel device, p+ dopants will be used.
  • a mask 724 is formed.
  • the mask 724 which preferably comprises silicon oxide, covers the drain region 722, and exposes the substrate region on the opposing side of the gate stack, as shown in Figure 7C.
  • a second semiconductor layer 726 is then epitaxially grown above the exposed surface portion of the first semiconductor layer 606.
  • the second semiconductor layer 726 comprises silicon and germanium, however it will be appreciated that other semiconductor materials may be used in different embodiments.
  • the second semiconductor layer 726 is initially grown to a height which will later form part of the L-shaped impact ionization region underneath a source region.
  • a combined deposition and i ⁇ -situ doping step during selective epitaxy is performed to form a heavy-doped source region 732.
  • the selective epitaxy employs any one or more of a group consisting of silane, disilane, methyl-silane, germane, and chlorine, depending on the material of the second semiconductor layer 726.
  • the gases silane, disilane, methyl-silane, or germane may be mixed with a carrier gas such as hydrogen or argon.
  • the second semiconductor layer 726 continues to be grown epitaxially with in-situ doping to form the source region 732.
  • p+ dopants will be used while to obtain a p-channel device, n+ dopants will be used in the in-situ doped source region 732.
  • Figure 7E shows the resulting. structure 734 after the mask 724 is removed by a suitable etch.
  • the etch employs. HF.
  • the device structure 734 has an L-shaped impact ionization region 736 extending vertically below the source region 732, and horizontally below the spacer 616a.
  • the overall length or dimension of the impact ionization region 736 between the source region 732 and the drain region 722 can be readily controlled or varied during the fabrication of the device structure 734. This is because the vertical portion of the impact ionization region 736 can be very accurately controlled through the epitaxial growth of the second semiconductor layer 726 (see figure 7C).
  • the device structure 734 is then subjected to annealing and a suitable Back-End-Of- Line process (BEOL) to form the finished LI-MOS transistor device.
  • BEOL Back-End-Of- Line process
  • the BEOL process includes first; a partial or full silicidation of the source region 732, drain region 722, and gate electrode 614.
  • a silicon nitride contact etch-stop layer is deposited, and an interlayer dielectric comprising silicon dioxide is deposited. This is followed by contact etching, and metal like tungsten is deposited to form the via.
  • a damascene process is then employed to form metal lines to connect various devices.
  • the starting device structure 800 is the same as the starting device structure 600 shown in Figure 6A, while the same numerals have been used to indicate the same layers.
  • an optional oxide layer 813 is deposited over the device structure 800, in the example embodiment using LPCVD or PECVD.
  • a photo resist 820 is then deposited and patterned using lithography techniques known in the art so that it is above the first semiconductor layer 606 on one side of the gate stack 602 and extending above one of the spacers 616a and above a portion of the gate electrode 614.
  • a doping step by ion implantation, plasma ion implantation or diffusion source is performed to form a drain region 822 in the first semiconductor layer 606 in areas not covered by the photo resist 820, and extending below the spacer 616b.
  • n+ dopants will be used while to. obtain a p-channei device, p+ dopants will be used.
  • a mask 824 is formed.
  • the mask 824 which preferably comprises silicon oxide, covers the drain region 822, and exposes the substrate region on the opposing side of the gate stack, as shown in Figure 8C.
  • a second semiconductor layer 816 comprising material is epitaxially grown above the exposed surface portion of the first semiconductor layer 606.
  • the second semiconductor layer 816 will later form part of the L-shaped impact ionization region underneath a source region.
  • a third semiconductor layer 826 is epitaxially grown above the second semiconductor layer 606a.
  • the second semiconductor layer 816 and third semiconductor layer 826 comprise silicon, however it will be appreciated that other semiconductor materials may be used in different embodiments.
  • the mask 824 is removed by a suitable etch.
  • the etch employs HF.
  • An oxide layer 828 is deposited by PECVD.
  • Photo resist 830 is then formed on one side of the gate stack 602 extending above the drain region 822, the spacer 616b and above a portion of the gate electrode 614, as shown in Figure 8D.
  • a doping step by ion implantation, plasma ion implantation or diffusion source is performed to form a heavy-doped source region 832 in the second semiconductor layer 826.
  • p+ dopants will be used while to obtain a p- channel device, n+ dopants will be used.
  • Figure 8E shows the resulting structure 834 after removal of the photo resist 830 by chemical resist stripping (CRS) or plasma resist stripping (PRS), and the oxide layer 828 by HF dip.
  • the device structure 834 has an L-shaped impact ionization region 836 extending vertically below the source region 832, and horizontally below the spacer 616a.
  • the overall length or dimension of the impact ionisation region 836 between the source region 832 and the drain region 822 can be readily controlled or varied during the fabrication of the device structure 834.
  • the device structure 834 is then subjected to annealing and a suitable Back-End-Of- i_ine process (BEOL) to form the finished LI-MOS transistor device.
  • BEOL Back-End-Of- i_ine process
  • the BEOL process includes first, a partial or full silicidation of the source region 832, drain region 822, and gate electrode 614.
  • a silicon nitride contact etch-stop layer is deposited, and an interlayer dielectric comprising silicon dioxide is deposited. This is followed by contact etching, and metal like tungsten is deposited to form the via.
  • a damascene process is then employed to form metal lines to connect various devices.
  • the starting device structure 900 is the same as the starting device structure 600 shown in Figure 6A, while the same numerals have been used to indicate the same layers.
  • an oxide layer 913 is deposited over the device structure 900, in the example embodiment using LPGVD or PECVD.
  • a photo resist 920 is then deposited and patterned using lithography techniques known in the art so that it is above the first semiconductor layer 606 on one side of the gate stack 602 and extending above one of the spacers 616a and above a portion of the gate electrode 614.
  • a doping step by ion implantation, plasma ion implantation or diffusion source is then performed to form a drain region 922 in the first semiconductor layer 606 in areas not covered by the photoresist 920, and extending below the spacer 616b.
  • n+ dopants will be used while to obtain a p-channel device, p+ dopants will be used.
  • a mask 924 is formed.
  • the mask 924 which preferably comprises silicon oxide, covers the drain region 922, and exposes the substrate region on the opposing side of the gate stack, as shown in Figure 9C.
  • a second semiconductor layer 916 is ep ⁇ taxially grown above the exposed surface portion of the first semiconductor layer 606. The second semiconductor layer 916 will later form part of the L-shaped impact ionization region underneath a source region.
  • a combined deposition and in-situ doping step during selective epitaxy is performed to form a heavy-doped source region 932.
  • the selective epitaxy employs any one or more of a group consisting of silane, disilane, methyl-silane, germane, and chlorine, depending on the material of the second semiconductor layer 926.
  • the gases silane, disilane, methyl-silane, or germane may be mixed with a carrier gas such as hydrogen or argon.
  • a third semiconductor layer 926 is epitaxially grown with in-situ doping to form the source region 932 above the exposed second semiconductor layer 916.
  • p+ dopants will be used while to obtain a p-Ghannel device, n+ dopants will be used.
  • the second semiconductor 916 and third semiconductor layer 926 comprise silicon, however it will be appreciated that other semiconductor materials may be used in different embodiments.
  • Figure 9E shows the resulting structure 934 after removal of the mask 924 by a suitable etch.
  • the etch employs HF.
  • the device structure 934 has a ⁇ L-shaped impact ionization region 936 extending vertically below the source region 932, and horizontally below the spacer 616a.
  • the overall length or dimension of the impact ionization region 936 between the source region 932 and the drain region 922 can be readily controlled or varied during the fabrication of the device structure 934. This is because the vertical portion of the impact ionization region 936 can be very accurately controlled through the epitaxial growth of the second semiconductor layer 916 (see figure 9C).
  • the device structure 934 is then subjected to annealing and a suitable Back-End-Of- Line process (BEOL) to form the finished LI-MOS transistor device.
  • BEOL Back-End-Of- Line process
  • the BEOL process includes first, a partial or full silicidation of the source region 932, drain region 922, and gate electrode 614. Next, a silicon nitride contact etch-stop layer is deposited, and an ⁇ nterlayer dielectric which comprises silicon dioxide is deposited. This is followed by contact etching, and metat like tungsten is deposited to form the via.
  • a damascene process is then employed to form metal lines to connect various devices.
  • the starting device structure 1000 is the same as the starting device structure 600 shown in Figure 6A.
  • the same numerals have been used to indicate the same layers.
  • an optional oxide layer 1013 is deposited over the device structure 1000, in the example embodiment using LPCVD or PECVD.
  • a photo resist 1020 is then deposited and patterned using photolithogaphy techniques known in the art so that it is above the first semiconductor layer 606 on one side of the gate stack 602 and extending above one of the spacers 616a and above a portion of the gate electrode 614.
  • a doping step by ion implantation, plasma ion implantation or diffusion source is performed to form a drain region 1022 in the first semiconductor layer 606 in areas not covered by the photoresist 1020, and extending below the spacer 616b.
  • n+ dopants will be used while to obtain a p-channel device, p+ dopants will be used.
  • a mask 1024 is formed.
  • the mask 1024 which preferably comprises silicon oxide, covers the drain region 1022, and exposes the substrate region on the opposing side of the gate stack, as shown in Figure 10C.
  • the exposed portion of the first semiconductor layer 606 is etched to form a recess 1006 extending below the spacer 616a as shown in Figure IOC: The etch can be performed, for example, with a dry plasma etch process or a wet etch process or a physical sputtering process.
  • An optional surface repair step such as an annealing step, may be performed to repair any etch damage on the surface of the etched recess 1006.
  • the annealing step may employ a temperature of above 350 degrees Celsius and may be performed in a hydrogen ambient, for example.
  • a second semiconductor layer 1016 comprising material is epitaxially grown on the recess 1006 of the first semiconductor layer 1006.
  • the second semiconductor layer 1016 will later form part of the L-shaped impact ionization region underneath a source region.
  • a combined deposition and in-situ doping step during selective epitaxy is performed to form a heavy-doped source region 1032.
  • the selective epitaxy employs any one or more of a group consisting of silane, disilane, methyl-silane or germane, depending on the material of the second semiconductor layer 1026.
  • the gases silane,. disilane, methyl-silane, or germane may be mixed with a carrier gas such as hydrogen or argon.
  • a third semiconductor layer 1026 is epitaxially grown with in-situ doping to form the source region 1032 above the exposed second semiconductor layer 1016.
  • p+ dopants will be used while to obtain a p-channel device, n+ dopants will be used.
  • the second semiconductor layer 1016 and third semiconductor layer 1026 comprise silicon, however it will be appreciated that other semiconductor materials may be used in different embodiments.
  • Figure 10E shows the resulting structure 1034 after removal of the mask 1024 by a suitable etch.
  • the etch employs HF.
  • the device structure 1034 has an L-shaped impact ionization region 1036 extending vertically below the source region 1032, and horizontally below the spacer 616a.
  • the overall length or dimension of the impact ionization region 1036 between the source region 1032 and the drain region 1022 can be readily controlled or varied during the fabrication of the device structure 1034. This is because the vertical portion of the impact ionization region 1036 can be very accurately controlled through the epitaxial growth of the second semiconductor layer 1016 (see figure 10D).
  • the device structure 1034 is then subjected to annealing and a suitable Back-End-Of- Line process (BEOL) to form the finished LI-MOS transistor device.
  • BEOL Back-End-Of- Line process
  • the BEOL process includes first, a partial or full silicidation of the source region 1032, drain region 1022, and gate electrode 614. Next, a silicon nitride contact etch-stop layer is deposited, and an blinkerlayer dielectric comprising silicon dioxide is deposited. This is followed by contact etching, and metal like tungsten is deposited to form the via.
  • a damascene process is then employed to form metal lines to connect various devices.
  • the starting device structure 1100 is the same as the starting device structure 600 shown in Figure 6A, while the same numerals have been used to indicate the same layers.
  • an optional oxide layer 1113 is deposited over the device structure 1100, in the example embodiment using LPCVD or PECVD.
  • a photo resist 1120 is then deposited and patterned using photolithography techniques known in the art so that it is above the first semiconductor layer 606 on one side of the gate stack 602 and extending above one of the spacers 616a and above a portion of the gate electrode 614.
  • a doping step by ion implantation , plasma ion implantation or diffusion source is then performed to form a drain region 1122 in the first semiconductor layer 606 in areas not covered by the photoresist 1120, and extending below the spacer 616b.
  • n+ dopants will be used while to obtain a p- ⁇ channel device, p+ dopants will be used.
  • a mask 1124 is formed.
  • the mask 1124 which preferably comprises silicon oxide, covers the drain region 1122, and exposes the substrate region on the opposing side of the gate stack, as shown in Figure 11 C.
  • a second semiconductor layer 1114 is epitaxially grown above the exposed surface portion of the first semiconductor layer 606. This is followed by a condensation step to form a compound region 1118 within the first semiconductor layer 606 so that a portion of the compound region 1118 extends below a portion of the spacer 616a as shown in Figure .11 D.
  • a third semiconductor layer 11,16 is epitaxially grown above the compound region 1118 of the first semiconductor layer 606.
  • the third semiconductor layer 1116 will later form part of the L-shaped impact ionization region underneath a source region.
  • a combined deposition and in-situ doping step during selective epitaxy is performed to form a heavy-doped source region 1132.
  • the selective epitaxy employs anyone or more of a group consisting of silane, disilane, methyl-silane, germane, and chlorine, depending on the material of the second semiconductor layer 1126.
  • the gases silah ⁇ j disilane, methyl-silane, or germane may be mixed with a carrier gas such as hydrogen or argori.
  • a fourth semiconductor layer 1126 is epitaxially grown with in-situ doping to form the source region 1132 above the exposed third semiconductor layer 1116.
  • p+ dopants will be used while to obtain a p-channel device, n+ dopants will be used.
  • the second semiconductor layer 1114, the third semiconductor layer 1116 and the fourth semiconductor layer 1126 comprise silicon germanium.
  • other semiconductor materials may be used in different embodiments.
  • Figure 11 F shows the resulting structure 1134 after removal of the mask 1124 by a suitable etch.
  • the etch employs HF.
  • the device structure 1134 has an L-shaped impact ionization region 1136 extending vertically below the source region 1132, and horizontally below the spacer 616a.
  • the overall length or dimension of the impact ionization region 1136 between the source region 1132 and the drain region 1122 can be readily controlled or varied during the fabrication of the device structure 1134. This is because the vertical portion of the impact ionization region 1136 can be very accurately controlled through the epitaxial growth of the fourth semiconductor layer 1126 (see figure 11 E).
  • the device structure 1134 is then subjected to annealing and a suitable Back-End-Of- Line process (BEOL) to form the finished LI-MOS transistor device.
  • BEOL Back-End-Of- Line process
  • the BEOL process includes first, a partial or full silicldation of the source region 1132, drain region 1122, and gate electrode 614. Next, a silicon nitride contact etch-stop layer is deposited, and an interiayer dielectric which could be silicon dioxide is deposited. Thjs is followed by contact etching, and metal like tungsten is deposited to form the via.
  • a damascene process is then employed to form metal lines to connect various devices.
  • Figure 12 shows a cross sectional View of an L-shaped Impact Ionization Metal-Oxide- Semiconductor (LI-MOS) transistor device 1200 built in accordance with one embodiment of the present invention.
  • LI-MOS Impact Ionization Metal-Oxide- Semiconductor
  • the device 1200 comprises a gate stack 1202 formed on a substrate structure 1204.
  • the substrate structure 1204 comprises a first semiconductor layer 1206 formed above an insulation layer 1208 on a wafer substrate 1210.
  • the gate stack 1202 comprises a gate dielectric layer 1212 formed on the first semiconductor layer 1206, a gate electrode 1214 formed above the gate dielectric layer 1212. Spacers 1216a and 1216b are formed on opposite sides of the gate electrode 1214.
  • a second semiconductor layer 1226 is formed above the substrate structure 1204.
  • a source structure comprising a heavy doped source region 1232 is formed within the second semiconductor layer 1226, the second semiconductor layer 1226 itself having a dopant concentration below 10 18 Cm "3 , adjacent to the spacer 1216a while a drain region 1222 is formed within the second semiconductor layer 1226 adjacent to the spacer 1216b extending below the spacer 1216b so that a portion of the drain region 1222 is formed within the substrate structure 1204.
  • the source region 1232 will be p+ doped while the drain region 1222 will be n+ doped.
  • the source region 1232 will be n+ doped while the drain region 1522 will be p+ doped.
  • a conducting channel (not shown), spanning from the source region 1232 to the drain region 1222 will be formed when the device 1200 is suitably biased.
  • an L-shaped impact ionization region 1236 extends vertically below the source region 1226, and horizontally below the spacer 1216a.
  • the first semiconductor layer 1206 and the second semiconductor layer 1226 comprises silicon.
  • the wafer substrate 1210 comprises bulk silicon, while the insulation layer 1208 comprises silicon dioxide.
  • the gate electrode 1214 comprises polysilicon.
  • the gate dielectric layer comprises silicon dioxide.
  • the spacers 1216a and 1216b comprise silicon nitride.
  • the substrate structure 1204 is a bulk semiconductor substrate which may comprise elemental semiconductors such as silicon, germanium, carbon, or compound semiconductors such as gallium arsenide, indium phosphide, indium antimonide, or combinations thereof.
  • Figure 13 shows a cross sectional view of an L-shaped Impact Ionization Metal-Oxide- Semiconductor (LI-MOS) transistor device 1300 built in accordance with one embodiment of the present invention.
  • LI-MOS Impact Ionization Metal-Oxide- Semiconductor
  • the starting device structure 1300 is the same as the starting device structure 600 shown in Figure 6A.
  • the same numerals have been used to indicate the same layers.
  • a second semiconductor layer 1326 is epitaxially grown above the first semiconductor layer 606 on both sides of the gate stack 602.
  • the second semiconductor layer 1326 comprises silicon, however it will be appreciated that other semiconductor materials, such as silicon- germanium and germanium, may be used in different embodiments.
  • a photo resist 1320 is deposited and patterned using stepper track so that it is above the second semiconductor layer 606 on one side of. the gate stack 602 and extending above one of the spacers 616a and above a portion of the gate electrode 614.
  • a doping step by ion implantation, plasma ion implantation or diffusion source is performed to form a drain region 1322 extending from the second semiconductor layer 1326 and the first semiconductor layer 606 in areas not covered by the photo resist 1320 to below the spacer 616b.
  • n+ dopants will be used while to obtain a p-channel device, p+ dopants will be used.
  • a photo resist 1330 is then formed on the other side of the gate stack 602 extending above the drain region 1322* the spacer 616b and above a portion of the gate electrode 614* as shown in Figure 13D.
  • a doping step by ion implantation, plasma ion implantation or diffusion source is performed to form a heavy-doped source region 1332 in the exposed portion of the second semiconductor layer 1326.
  • p+ dopants will be used while to obtain a p-channel device, n+.dopants will be used.
  • FIG. 13E shows the resulting structure 1334 after removal of the photo resist 1330 by chemical resist stripping (GRS) or plasma resist stripping (PRS).
  • the device structure 1334 has an L-shaped impact ionization region 1336 extending vertically below the source region 1332, and horizontally below the spacer 616a.
  • the overall length or dimension of the impact ionization region 1336 between the source region 1332 and the drain region 1322 can be readily controlled or varied during the fabrication of the device structure 1334. This is because the vertical portion of the impact ionization region 1336 can be very accurately controlled through the epitaxial growth of the second semiconductor layer 1326 (see figure 13B) on the one hand, and control of the doping process to from the source region 1332 (see Figure 13D).
  • the L-shaped impact ionization region 1036 allows for a compact design without sacrificing silicon (substrate) area.
  • the device structure 1334 is then subjected to annealing and a suitable Back-End-Of- Line process (BEOL) to form the finished LI-MOS transistor deyiGe.
  • BEOL Back-End-Of- Line process
  • the BEOL process includes first, a partial or full silicidation of the source region 1332, drain region 1322, and gate electrode 614.
  • a silicon nitride contact etch-stop layer is deposited, and an interlayer dielectric comprising silicon dioxide is deposited. This is followed by contact etching, and metal like tungsten is deposited to form the via.
  • a damascene process is then employed to forrri metal lines to connect various devices. . Having a raised source region 1332 and a raised drain region 1322 in the finished Ll- MOS transistor device may facilitate subsequent circuit interconnection between other peripheral devices.
  • the starting device structure 1400 is the same as the starting device structure 600 shown in Figure.6A, while the same numerals have been used to indicate the same layers.
  • a second semiconductor layer 1416 is epitaxially grown above the exposed surface portion of the first semiconductor layer 606.
  • the second semiconductor layer 1416 will later form part of the L-shaped impact ionization region underneath a source region.
  • a third semiconductor layer 1426 is then epitaxially grown above the second semiconductor layer 1416.
  • the second semiconductor layer 1416 and the third semiconductor layer 1426 comprise silicon, however it will be appreciated that other semiconductor materials may be used in different embodiments.
  • a photo resist 1420 is deposited and patterned using, stepper track so that it is above the third semiconductor layer 1426 on one side of the gate stack 602 and extending above one of the spacers 616a and above a portion of the gate electrode 614.
  • a doping step by ion implantation, plasma ion implantation or diffusion source is performed to form a drain region 1422 extending from the third semiconductor layer 1426, the second semiconductor layer 1416 and the first semiconductor layer 606 in areas not covered by the photo resist 1420 to below the spacer 616b.
  • n+ dopants will be used while to obtain a p-channel device, p+ dopants will be used.
  • a photo resist 1430 is then formed on one side of the gate stack 602 extending above the drain region 1422, the spacer 616b and above a portion of the gate electrode 614, as shown in Figure 14D.
  • a doping step by ion implantation, plasma ion implantation or diffusion source is performed to form a heavy-doped source region 1432 in the exposed portion of the second semiconductor layer 1416.
  • p+ dopants will be used while to obtain a p-channel device, n+ dopants will be used.
  • FIG 14E shows the resulting structure 1434 after removal of the photo resist 1430 by chemical resist stripping (CRS) or plasma resist stripping (PRS).
  • the device structure 1434 has an L-shaped impact ionization region 1436 extending vertically below the source region 1432, and horizontally below the spacer 616a.
  • the overall length or dimension of the impact ionization region 1436 between the source region 1432 and the drain region 1422 can be readily controlled or varied during the fabrication of the device structure 1434. This is because the vertical portion of the impact ionization region 1436 can be very accurately controlled through the epitaxial growth of the second semiconductor layer 606a (see figure 14B) on the one hand, and control of the doping process to form the source region 1432 (see Figure 14D).
  • the L-shaped impact ionization region 1436 allows for a compact design without sacrificing silicon (substrate) area.
  • the device structure 1434 is then subjected to annealing and a suitable Back-End-Of- Line process (BEOL) to form the finished LI-MOS transistor device.
  • BEOL Back-End-Of- Line process
  • the BEOL process includes first, a partial or full silicidati ⁇ n of the source region 1432, drain region 1422, and gate electrode 614.
  • a silicon nitride contact etch-stop layer is deposited, and an interlayer dielectric comprising silicon dioxide is deposited. This is followed by contact etching, and metal like tungsten is deposited to form the via.
  • a damascene process is then employed to form metal lines to connect various devices. Having a raised source region 1432 and a raised drain region 1412 in the finished Ll- MOS transistor device may facilitate subsequent circuit interconnection between other peripheral devices.
  • Figure 15 shows a cross sectional view of an L-shaped Impact Ionization Metal-Oxide- Semioonductor (LI-MOS) transistor device 1500 built in accordance with one embodiment of the present invention.
  • LI-MOS Impact Ionization Metal-Oxide- Semioonductor
  • the device 1500 comprises a gate stack 1502 formed on a substrate structure 1504.
  • the substrate structure 1504 comprises a semiconductor layer 1506, and a bulk substrate 1510.
  • the gate stack 1502 comprises a gate dielectric layer 1512 formed on the first semiconductor layer 1506, a gate electrode 1514 formed above the gate dielectric layer 1512. Spacers 1516a and 1516b are formed on opposite sides of the gate electrode 1514.
  • a second semiconductor layer 1526 is formed above the substrate structure 1504.
  • a source structure comprising a heavy doped source region 1532 is formed within the second semiconductor layer 1526, the second semiconductor layer 1526 itself having a dopant concentration below 10 18 Cm "3 , adjacent to the spacer 1516a while a drain region 1522 is formed within the first semiconductor layer 1506 adjacent to the spacer 1516b extending below the spacer 1516b so that the drain region 122 is formed within the substrate structure 1504.
  • the source region 1532 will be p+ doped while the drain region 1522 will be n+ doped.
  • the source region 1532 will be n+ doped while the drain region 1522 will be p+ doped.
  • a conducting channel (not shown), spanning from the source region 1532 to the drain region 1522 will be formed when the device 1500 is suitably biased.
  • an L-shaped impact ionization region 1536 extends vertically below the source region 1532, and horizontally below the spacer 1516a.
  • the first semiconductor layer 1506 and the second semiconductor layer 1526 comprises silicon.
  • the wafer substrate 1510 comprises bulk silicon.
  • the gate electrode 1-5.14 comprises polystlicon.
  • the gate dielectric layer 1512 comprises silicon dioxide.
  • the spacers 1516a and 1516b comprise silicon nitride.
  • Figure 16 shows a cross sectional View of an L-shaped Impact Ionization Metal-Oxide- Semiconductor (LI-MOS) transistor device 1600 built in accordance with one embodiment of the present invention.
  • LI-MOS Impact Ionization Metal-Oxide- Semiconductor
  • the device 1600 comprises a gate stack 1602 formed on a substrate structure 1604.
  • the substrate structure 1604 comprises a first semiconductor layer 1606 formed on a wafer substrate 1610.
  • the gate stack 1602 comprises a gate dielectric layer 1612 formed on the first semiconductor layer 1606, a gate electrode 1614 formed above the gate dielectric layer 1612. Spacers 1616a arid 1616b are formed on opposite sides of the gate electrode 1614.
  • a second semiconductor layer 1626 is formed above the substrate structure 1604.
  • a source structure comprising a heavy doped source region 1632 is formed within the second semiconductor layer 1626, the second semiconductor layer 1626 itself having a dopant concentration below 10 18 Cm "3 , adjacent to the spacer 1616a while a drain region 1622 is formed within the second semiconductor layer 1626 adjacent to the spacer 1616b extending below the spacer 1616b so that a portion of the drain region 1622 is formed within the substrate structure 1604.
  • the source region 1.632 will be p+ doped while the drain region 1622 will be n+ doped.
  • the source region 1632 will be n+ doped while the drain region 1622 will be p+ doped.
  • a conducting channel (not shown), spanning from the source region 1632 to the drain region 1622 will be formed when the device 1600 is suitably biased.
  • an L-shaped impact ionization region 1636 extends vertically below the source region 1632, and horizontally below the spacer 1616a.
  • the first semiconductor layer 1604 and the second semiconductor layer 1626 comprises silicon.
  • the wafer substrate 1610 comprises bulk silicon.
  • the gate electrode 1614 comprises polysilicon.
  • the gate dielectric layer 1612 comprises silicon dioxide.
  • the spacers 1616a and 1616b comprise silicon nitride.
  • Figure 17 shows a cross sectional view of an L-shaped Impact Ionization Metal-Oxide- Semiconductor (LI-MOS) transistor device 1700 built in accordance with one embodiment of the present invention.
  • LI-MOS Impact Ionization Metal-Oxide- Semiconductor
  • the device 1700 comprises a gate stack 1702 formed on a substrate structure 1704.
  • the substrate structure 1704 comprises a first semiconductor layer 1706 formed above an insujation layer 1708 on a wafer substrate 1710.
  • the gate stack 1702 comprises a first gate insulator or a first gate dielectric layer 1712 formed on the first semiconductor layer 1706, a charge storage layer 1710 formed above the first gate dielectric layer 1712, a second gate dielectric layer 1713 formed above the charge storage layer 1710 and a gate or gate electrode 1714 formed above the second gate dielectric layer 1713.
  • Spacers 1716a and 1716b are formed on opposite sides of the gate electrode 1714.
  • a second semiconductor layer 1726 is formed above the substrate structure 1704.
  • a source structure comprising a heavy doped source region 1732 is formed within the second. semiconductor layer 1726, the second semiconductor layer 1726 itself having a dopant concentration below Iu 18 CnT 3 , adjacent to the spacer 1716a while a drain region 1722 is formed within the second semiconductor layer 1726 adjacent to the spacer 116b extending below the spacer 1716b so that a portion of the drain region 1722 is formed within the substrate structure 1704.
  • the source region 1732 will be p+ doped while the drain region 1722 will be n+ doped.
  • the source region 1732 will be n+ doped while the drain region 1722 will be p+ doped.
  • a conducting channel (not shown), spanning from the source region 1732 to the drain region 1722 will be formed when the device 1700 is suitably biased.
  • the charge storage layer 1710 retains a charge after removal of the biasing voltage applied to the device 1700, it will be Appreciated by the person skilled in the art that the device 1700 can be used in memory devices.
  • an L-shaped impact ionization region 1736 extends vertically below the source region 1726, and horizontally below the spacer 1716a.
  • the first semiconductor layer 1706 and the second semiconductor layer 1726 comprises silicon.
  • the wafer substrate 1710 comprises bulk silicon, while the insulation layer 1708 comprises silicon dioxide.
  • the gate electrode 1714 comprises polysilicon.
  • the first gate dielectric layer 1712 and the second gate dielectric layer 1713 comprise silicon dioxide.
  • the charge storage layer 1710 comprises a floating gate made of polysilicon or silicon nitride.
  • the spacers 1716a and 1716b comprise silicon nitride.
  • the charge storage layer 1710 is a layer of discrete dots or quantum dots comprising metal, semiconductor or a dielectric material. In other embodiments, the charge storage layer 1710 comprises metal dots embedded in a dielectric matrix, semiconductor dots embedded in a dielectric matrix or a first dielectric with a smaller band gap embedded in a second dielectric matrix with a larger band gap.
  • Figure 18 shows the electrical circuit symbols for a LI-MOS device built in accordance with an embodiment of the present invention. Electrical circuit symbol 1802 is used to represent an n-channel LI-MOS while electrical circuit symbol 1804 is used to represent a p-channel LI-MOS.
  • Figures 19A to 19C shows basic electrical circuits 1900 comprising a LI-MOS device built in accordance with an embodiment of the present invention.
  • first inverter electrical circuit 1902 an n-channel LI-MOS device 1802 is connected as shown to a resistor R while to form a second inverter electrical circuit 1904, a p-channel LI-MQS device 1804 is connected as shown to a resistor R.
  • a third inverter electrical circuit 1906 is formed by connecting the n-channel LI-MOS device 1802 with the p-channel LI-MOS device 1804 as shown.
  • V DD and Vss Two distinct power supply voltages V DD and Vss are respectively used for each of the inverter circuits 1902, 1904 and 1906 while each of the outputs V ⁇ ut can be connected to a load (not shown). It will be appreciated by the person skilled in the art that the inverter circuits 1902, 1904 and 1906 can be appropriately arranged to form digital logic gates such as N ⁇ ND, NOR arid XOR.
  • Figures 2OA and 2OB show inverter circuits comprising conventional CMOS devices and LI-MOS devices built in accordance with embodiments of the present invention.
  • ah n-channel LI-MOS device 1802 is connected as shown to a conventional p-channel CMOS device 2006 while to form a second inverter electrical circuit 2004, a p-channel LI-MOS device 1804 is connected as shown to a conventional n-channel CMOS device 2008.
  • Two distinct power supply voltages V DD and V ss are respectively used for each of the inverter circuits 2002 and 2004 while each of the outputs V oyA can be connected to a load (not shown).
  • Figures 21 A to 21 C shows NAND logic gate circuits 2100 comprising conventional CMOS devices and LMMOS devices built in accordance with embodiments of the present invention.
  • a first NAND logic gate circuit 2102 is formed by connecting two n-channel LI-MOS devices 1802 that are in series with two parallel connected p-channel Ll-MOS devices 1804 as shown in Figure 21 A.
  • a second NAND logic gate circuit 2104 is formed by connecting one n-cha ⁇ nel LI-MOS device 1802 and one conventional n-channel CMOS device 2108 that are in series with two parallel connected p ⁇ ;hannel Ll-MOS devices 1804 as shown in Figure 21 B.
  • a third NAND logic gate circuit 2106 is formed by connecting one n-channel LI-MOS device 1802 and one conventional n-channel CMOS device 2108 that are in series with two parallel connected conventional p-channel CMOS devices 2110 as shown in Figure 21 C.
  • V DD and V ss are respectively used for each of the NAND logic gate circuits 2102, 2104 and 2106 while each of the outputs V out can be connected to a load (not shown).

Abstract

La présente invention concerne un dispositif semi-conducteur (100) qui comprend une structure de substrat (104) ; un empilement de grilles (102) formé sur ladite structure de substrat (104) ; une région de drain (122) d'un premier type de dopant formée dans ladite structure de substrat (104) de manière adjacente audit empilement de grilles (102) ; une structure de source (126) formée sur ladite structure de substrat (104) de manière adjacente audit empilement de grilles (102), la structure de source (126) comprenant une région de source (132) d'un second type de dopant et une première région d'une concentration en dopant inférieure à 1018 cm-3 disposée entre la région de source (132) et la structure de substrat (104). Le dispositif à semi-conducteurs à oxydes métalliques à ionisation par choc (IMOS) trouve une application en tant qu'inverseur ou une intégration dans des puces à circuits intégrés.
PCT/SG2006/000093 2005-07-07 2006-04-11 Structure semi-conductrice destinée à des transistors ayant une excursion infraliminaire et procédés de fabrication de celle-ci WO2007008173A1 (fr)

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JP5440169B2 (ja) * 2007-08-10 2014-03-12 日本電気株式会社 半導体装置、及び、その製造方法
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