WO2006134683A1

WO2006134683A1 - Signal processing apparatus

Info

Publication number: WO2006134683A1
Application number: PCT/JP2005/024058
Authority: WO
Inventors: Hideyuki Saito; Takeshi Yamazaki
Original assignee: Sony Computer Entertainment Inc.
Priority date: 2005-06-17
Filing date: 2005-12-28
Publication date: 2006-12-21
Also published as: JP2006350868A

Abstract

A signal processing apparatus that can be efficiently developed. A controller (140) in a main system (110) of a signal processing apparatus (100) converts visual-aural data (136), which has been processed by a processor (120), to a first signal group of a common format that can be transferred by a transferring part (150). The transferring part (150) transfers the first signal group to a developing interface (160), which then develops the first signal group into a second signal group, which is suitable for a particular use, and then outputs the second signal group. The first signal group has a narrower bus width than the second signal group. The main system (110) and developing interface (160) are incorporated in respective discrete semiconductor integrated circuits.

Description

Specification

Signal processing device

Technical field

The present invention relates to a signal processing apparatus that performs signal processing, specifically, processing for converting data, particularly streaming data, into a signal group suitable for a predetermined application.

Background art

Conventionally, high-rate stream data has been processed by a dedicated hardware processing device having a fixed function. Since these dedicated hardware processing units depend on the type of data, an input / output interface was prepared for each type of data, and a dedicated pin was assigned to handle low-speed data.

[0003] On the other hand, high performance of a general-purpose processing device having high programmer's spirit has been advanced due to high integration of semiconductors, and such a general-purpose processing device has conventionally been processed by a dedicated hardware processing device. It became possible to handle streaming data. In addition, the generalization of processing equipment has made it possible to handle many types of data with a single equipment. In addition, with the further improvement in performance of general-purpose processing equipment, the streaming data handled is in the trend of increasing the rate of images, including higher resolution video and higher frame rate.

Disclosure of the invention

Problems to be solved by the invention

[0004] Streaming data input / output interfaces such as cameras and displays differ depending on the set specification. Sets with these I / O interfaces have often handled high-speed devices such as storage networks.

On the other hand, general-purpose processing devices such as processors are not limited to streaming data.

Process various other data.

[0005] Therefore, a main system realized by a processor and a chip set of a general-purpose processing device or a SoC (System on Chip) in which these are integrated requires many pins, and the circuit becomes complicated. General-purpose processing equipment has originally become large-scale as its performance increases. There is a tendency to increase the development scale and development cost by imitating, and moving to the main system for each set specification further accelerates the high cost of development.

Although it is nice to be able to handle many types of data with a single general-purpose processing device, the number of pins required is further increased by preparing a dedicated input / output interface for each data type. End up.

[0006] As a method for separating a general-purpose processing device and an extended portion that differs for each set specification, there is a method of mounting a streaming data processing device on the end of a general-purpose expansion interface such as PCI Express. As a result of the high speed operation, the connected device needs a large-capacity buffer to absorb jitter, the structure of the device itself becomes complicated, and the cost and power consumption increase.

[0007] The present invention has been made in view of such circumstances, and provides a signal processing device capable of reducing the development burden.

Means for solving the problem

[0008] One embodiment of the present invention relates to a signal processing device. This signal processing apparatus inputs data, converts and outputs a first signal group based on a predetermined conversion rule, and a first signal group output from the conversion and transfer section. An application-specific expansion unit that expands to a second signal group suitable for a specific application, and the conversion rule is defined in common for a plurality of applications including the specific application, and the first signal group is It is formed as a signal group having a narrower bus width than the second signal group, and the conversion transfer unit and the application specific development unit are incorporated in a separate semiconductor integrated circuit.

[0009] A signal processing device according to another aspect of the present invention includes a main processor, a main memory that holds data processed by the main processor, and data that is input from the main memory and stored in an internal buffer. After that, based on a predetermined conversion rule, these data are converted into the first signal group and output, and the conversion and transfer unit outputs the first signal group that is output, and is used for a specific application. A conversion unit for each application that expands to a second signal group that conforms, and the conversion rule is defined in common for a plurality of applications including the specific application, and the first signal group is the second signal group. It is formed as a signal group with a narrower bus width, and the conversion transfer unit and the application-specific development unit are mounted on a separate semiconductor integrated circuit mounted on a single printed circuit board. Each is built-in.

Here, the data input to the signal processing apparatus according to the aspect of the present invention may be, for example, streaming data. “Streaming data” means continuous data that requires low jitter, such as uncompressed or compressed viewing data and sensory input data used for real-time control. “Viewing data” means video data, audio data, etc. that can be perceived when played, and generally means what can be perceived visually or auditorily. Even something that can be felt by perceptions other than hearing! /.

[0011] According to such an aspect of the present invention, the conversion / transfer unit converts the first signal group into the second signal group having a narrower bus width than the first signal group. It is possible to reduce the number of signal lines between the conversion section and the application-specific conversion section, and the number of pins used by the conversion / transfer section can be reduced. Moreover, since the conversion rules of the conversion / transfer unit are general-purpose, the conversion / transfer unit can be shared for different purposes. Furthermore, since the conversion / transfer unit and the application-specific conversion unit are separate, different applications can be realized by replacing only the application-specific development unit.

[0012] It should be noted that a configuration in which constituent elements and expressions of the present invention are mutually replaced between methods, systems, and the like is also effective as an aspect of the present invention.

The invention's effect

[0013] The present invention is advantageous in the development of a signal processing device.

Brief Description of Drawings

FIG. 1 is a diagram showing an outline of an embodiment according to the present invention.

FIG. 2 is a flowchart showing an outline of processing by each configuration shown in FIG.

FIG. 3 is a block diagram showing a configuration of a signal processing device according to an embodiment of the present invention.

4 is a diagram showing a configuration example of a transfer unit in the signal processing device shown in FIG.

FIG. 5 is a diagram showing details of signals transferred by the transfer unit shown in FIG.

6 is a diagram showing a timing chart of signals transferred by the transfer unit shown in FIG.

FIG. 7 is a diagram showing examples of control commands.

FIG. 8 is a diagram showing an example of a transfer format of image data.

FIG. 9 is a block diagram showing a configuration of a deployment interface in the signal processing apparatus shown in FIG. FIG.

Explanation of symbols

[0015] 10 conversion / transfer unit, 20 transfer bus, 30 application-specific development unit, 100 signal processing device,

110 main system, 120 processor, 130 main memory, 134 control data, 136 viewing data, 140 controller, 144 sequencer, 146 nofer, 150 transfer unit, 160 deployment interface 164 deployment unit, 168 pins.

BEST MODE FOR CARRYING OUT THE INVENTION

[0016] A conventional signal processing apparatus includes an LSI (including a plurality of LSIs arranged in parallel) that acquires and outputs a baseband signal, and uses the baseband signal (for example, the type of output destination device). It is connected directly to a converter interface that converts the output according to the output. For example, in developing a signal processing device for outputting a signal to device A, an LSI that acquires and outputs a baseband signal and a baseband signal from this LSI are received and matched to the type of device A. Design the interface to be converted to match device A. For device B, the LSI that acquires and outputs the baseband signal and the transformation interface are designed to match device B. In addition, even when the specifications of the output device change, it may be necessary to redesign the acquisition output LSI and conversion interface according to the new specifications of the device. Therefore, it takes time and effort to design and remanufacture the acquisition output LSI and the interface as necessary for each type of device and for each specification. Furthermore, as mentioned above, the structure of the acquisition output LSI and the interface with a large number of pins is complicated in the background of high-speed streaming data including viewing data such as images and sounds, and high frame rate interface. Therefore, the time and effort of development is further accelerated, and the burden on the developer is increased. Therefore, problems such as higher development costs and longer development periods may occur.

[0017] The present inventor provides a base between a side that transmits streaming data, which is a baseband signal that solves the above problem, and a conversion interface that converts the streaming data in accordance with a specific application. A band signal is converted based on a conversion rule commonly defined for a plurality of uses including this specific use (hereinafter referred to as a common conversion rule). The following technology is proposed based on the basic idea that a signal processing device can be divided into a general-purpose processing part and a dedicated processing part by providing conversion means and generalizing the streaming data transmission side. . Figure 1 shows an overview of this technology.

First, a conversion transfer unit 10 corresponding to the conversion unit described above is provided. The conversion / transfer unit 10 converts the streaming data into the first signal group according to the common conversion rule.

Then, an application-specific development unit 30 that develops the first signal group into a second signal group suitable for a specific application is provided in a semiconductor integrated circuit separate from the semiconductor integrated circuit incorporating the conversion transfer unit 10. Provided by incorporating. In addition, the conversion / transfer unit 10 forms the first signal group having a narrower bus width than the second signal group. The first signal group is output to the application-specific development unit 30 via the transfer bus 20.

FIG. 2 is a flowchart showing an overview of processing by each configuration shown in FIG. As shown in the figure, the streaming data input to the conversion / transfer unit 10 is converted into the first signal group by the conversion / transfer unit 10 according to the common conversion rule (S10, S12). This first signal group is output to the application-specific development unit 30 via the transfer bus 20 (S14), and is converted into a second signal group suitable for the specific application by the application-specific development unit 30 (S16). . Then, the second signal group is output to the output destination device, and the process ends (S20).

That is, according to this configuration, the streaming data is converted into the first signal group according to the common conversion rule, and output to the application-specific development unit 30. Here, the specifications of the conversion / transfer unit 10 and the application-specific development unit 30 are fixed for one product, and the specifications of the conversion / transfer unit 10 and the application-specific development unit 30 are used when developing other products. Although it is necessary to change, the conversion and transfer unit 10 converts the streaming data according to the common conversion rule, so the specification can be easily changed.

[0021] Furthermore, when the conversion transfer unit 10 is configured to be changed by software, there is no change in the hardware portion of the conversion transfer unit 10 when developing other products. Even if the product changes, it is not necessary to change the hardware part of the conversion transfer unit 10.

In addition, since the first signal group has a narrower bus width than the second signal group, the number of pins of the conversion / transfer unit 10 and the application-specific development unit 30 can be reduced. [0022] Further, since the first signal group has a narrower bus width than the second signal group, it is possible to reduce the scale of the circuit in which the number of signal lines of the transfer bus 20 is small.

[0023] Furthermore, since the conversion transfer unit 10 and the application development unit 30 are built in separate semiconductor integrated circuits, different applications can be realized by replacing only the application development unit.

[0024] From the above, such a configuration can reduce the burden of developing a signal processing device, and is advantageous in either reducing the development cost or shortening the development period.

Hereinafter, the best mode for carrying out the present invention will be described.

FIG. 3 is a block diagram showing the configuration of the signal processing apparatus 100 according to the embodiment of the present invention. As shown in the figure, the signal processing apparatus 100 of this embodiment includes a main system 110 and a deployment interface 160, and a transfer unit 150 that transfers data is provided between the main system 110 and the deployment interface 160. ing. The main system 110 and the deployment interface 160 are built in separate semiconductor integrated circuits and mounted on a single printed circuit board.

[0026] The signal processing apparatus 100 is a specific example that realizes the configuration shown in FIG. 1. The main system 110, the transfer unit 150, and the expansion interface 160 are the conversion transfer unit 10, the transfer bus 20, and the like in FIG. Corresponds to the development section 30 by application.

[0027] It should be noted that the force shown so that the transfer unit 150 can be seen in the figure in order to facilitate force distribution. In the signal processing device 100 of this embodiment, the transfer unit 150, the transfer unit 150, the main system 110, The connection part between the transfer unit 150 and the deployment interface 160 is developed on the printed circuit board so that the signal pattern transferred by the transfer unit 150 is not visible, such as a part of the main system. Shielded by part of interface 160. By doing this, it is possible to prevent unauthorized use of the signal output from the main system 110 side or the signal transferred by the transfer unit 150, and to improve security.

The main system 110 includes a processor 120, a main memory 130, and a controller 140. The processor 120 performs the following processing.

[0029] 1. Streaming data adapted to a specific application by executing software such as a multimedia application, for example, viewing data such as image data and audio data. Obtain 136. The signal processing apparatus 100 according to the present embodiment handles real-time viewing data, and the viewing data 136 is hereinafter referred to as real-time data 136.

[0030] 2. The controller 140 is controlled to generate control data 134 for processing performed by the controller 140, and the real-time data 136 is encapsulated by the control data 134.

The main memory 130 holds control data 134 and real time data 136 obtained by the processor 120.

[0032] The controller 140 includes a sequencer 144 and a buffer 146. The controller 140 acquires control data 134 from the main memory 130 according to the control of the processor 120, and also converts the real-time data 136 into the main memory 130 based on the control data 134. read out. Here, the control data 134 created by the processor 120 is related to the process in which the controller 140 reads data from the main memory 130, such as the address and size in the main memory 130 of the real-time data 136 to be read by the controller 140. The controller 140 develops the real-time data 136 such as information specifying the control command to be transmitted to the controller 140, the timing for transmitting the real-time data 136 read from the main memory 130, and the transfer rate. Some of them are related to the processing to be output. The sequencer 144 of the controller 140 reads the real-time data 136 from the main memory 130 based on the control data 134 and stores it in the buffer 146. Then, the sequencer 144 interlaces the real-time data 136 stored in the buffer 146 with the control command specified by the control data 134 and transfers the real-time data 136 to the real-time data 136 in a format that can be transferred by the transfer unit 150. Output to the transfer unit 150 at the specified timing and transfer rate.

[0033] For convenience of explanation, the signal group sent from the controller 140 is referred to as a first signal group.

Here, since the controller 140 stores the real-time data 136 in the buffer 146, it can absorb the jitter generated in the memory interface and the internal nose. That is, the first signal group is one in which jitter is absorbed.

[0034] The first signal group output from the controller 140 is transferred to the expansion interface 160 by the transfer unit 150, and the expansion interface 160 expands the first signal group and outputs it. Output to the device. Hereinafter, the signal group obtained by the deployment interface 160 is referred to as a second signal group.

Here, the operation of the sequencer 144 of the controller 140 and the details of the first signal group will be described while describing the details of the transfer unit 150.

FIG. 4 shows a configuration example of the transfer unit 150. The transfer unit 150 includes a CLK signal line 152 (152a: CLK +, 152b: CLK) for transferring the normal phase and reverse phase clock signals CLK for synchronization, and a data bus 154 for transferring data signals. And a CTRL signal line 156 for transferring the CTRL signal and an INT signal line 158 for transferring the interrupt signal INT. Of the signals transferred by the transfer unit 150, only the INT signal is transmitted to the slave side, here the expansion interface 160 side to the master side, here the main system 110 side.

FIG. 5 is a diagram for explaining signals transferred by each bus of the transfer unit 150. Here, as an example, the data signal is 16 bits and the data bus 154 has a bus width of 16 bits, but the number of bits of the data signal may be 8 bits, for example.

[0037] CLK is a clock signal for synchronization as described above, and is supplied from, for example, an external clock generator (not shown).

The data signal is a DDR (Double Data Rate) signal that includes real-time data and control commands and changes at the rising edges of the clock signals CLK + and CLK.

[0038] The CTRL signal indicates whether the signal flowing in the data bus 154 is force real-time data that is a control command. When the CTRL signal is 1 and 0, the control command and real-time data are respectively indicated. Show.

As shown in FIG. 5, the INT signal is a high-active signal for notifying the main system 110 when a predetermined event occurs on the development interface 160 side.

Here, the first signal group described above includes a CLK signal, a data signal, and a CTRL signal, and the sequencer 144 of the controller 140 determines the real-time data → 136 based on the control data 134. Convert to a group.

FIG. 6 shows these signals when 16-bit image data is taken as an example of real-time data. The timing chart in which a number is transferred is shown. As shown in the figure, at the rising edge of the clock signal CLK, the data signal changes, and when the CTRL signal is 0, the RGB data is transmitted, and when the CTRL signal is 1, the control command is transmitted. .

[0041] The control command is determined for each image, sound, and other real-time data, and varies depending on the type of real-time data. Here, the signal processing apparatus 100 according to the present embodiment applies all the real-time data. The control commands defined in common for are explained.

[0042] FIG. 7 illustrates various commands commonly defined for real-time data.

The “No Operation” command indicates that nothing is to be done and is used to adjust the timing. In this command data, the most significant bit is 0, and the data of other bits is arbitrary.

[0043] The "Change Channel" command indicates that the data string of the number specified by "channnel" (b) in the command is output by the number of cycles specified by "size". Since the signal processing apparatus 100 of the present embodiment transfers real-time data having a plurality of channels through one 16-bit data bus 154, a number is assigned to each channel of real-time data and the number is designated. To reserve a real-time channel for transmission. That is, by switching and transmitting the data of each channel of real-time data having a plurality of channels, a “virtual channel” for transmitting real-time data of a plurality of channels with a single bus is realized.

[0044] During the cycle specified by "size" in this command, the bandwidth of the data bus 154 is reserved for the specified channel (number). In this embodiment, this command is effective only when the bandwidth is reserved for any channel. In this way, when the bandwidth is not reserved, data can be transmitted with channel 0 selected. When transmission of the data of the channel reserved by this command is completed for the designated cycle, the state in which the bandwidth is not reserved, that is, channel 0 is selected, and the state returns to the state of being reserved. The “Set upper Address” command is not shown, but sets an upper address of this register when a register for control is mounted on the expansion interface 160. For example, the “address” (a) in this command can be used to set the upper 12 bits of the register address space.

[0046] The “Write registerj command” instructs the above-mentioned “Set upper AddressJ command and“ lower 12-bit area specified by addres ssj ”to write data to the register specified by“ data ”. . The 12 bits are set here because the bus width of the data bus 154 is only 16 bits.

The “Assert Singal” command is a command for asserting the control signal designated by “singal” in the command, that is, a command for setting the value of the control signal to 1.

The “Deassert Singal” command is a command for deasserting the designated control signal by “singal” in the command, that is, a command for setting the value of the control signal to 0.

[0049] The control signal specified by "singal" in the "Assert SingalJ command" and "Deassert SingalJ command" differs depending on the type of real-time data. For example, in the case of image data, the "VSYSNC" signal, " There are examples such as “HSYNC” signal, and in the case of audio data, there is an example of “MUTE” signal as its control signal.

[0050] As described above, other commands such as providing a command for user reservation may be defined as a matter of course, as an example of a command commonly defined for real-time data. Real-time data is transmitted when the CTRL signal is deasserted, ie at its value SO.

[0051] The type of real-time data handled varies depending on the product. In any product, real-time data is converted according to a common conversion rule that converts it into the first signal group that is powerful with the CLK signal, data signal, and CTRL signal. Different transfer formats. Fig. 8 illustrates the format for transferring each type of image data. According to these formats, any bandwidth data can be transferred via the data bus 154 having a 16-bit bus width.

[0052] For example, in the case of RGB data with 9 to 16 bits, the transfer format is R → G → B. Since the bus width of the data bus 154 is 16 bits, when the number of bits of the image data is less than 16, the lower bits are truncated on the receiving side, here, the expansion interface 160 side. For example, when the number of bits of RGB data is 12, the expansion interface 160 truncates the lower 4 bits of each of the received R, G, and B signals.

[0053] On the other hand, when the image data is 8-bit RGB data, taking two pixels (R1G1B1 and R2 G2B2) as an example, the transfer format is changed from "R1G1" → "B1" → "R2G2" → "B2 " Of course, when this transfer format is used, the lower 8 bits of B are truncated, so the transfer width of “R1G1” → “B1R2” → “G2B2” is used to make the bus width of the data bus 154 more effective. May be used to improve transfer efficiency

[0054] For example, when the image data is YCrCb (Y: Cr: Cb = 4: 2: 2) data of 9 bits or more and 16 bits or less, it can be transferred as “Y” → “CrCb”. . When transferring CrCb, the lower 8 bits and upper 8 bits of data bus 154 may be assigned to Cr and Cb, respectively. As in the case of RGB data, if the number of bits is less than 16 bits, the corresponding lower bits should be truncated on the expansion interface 160 side.

On the other hand, when the image data is 8-bit YCrCb data, one pixel can be transferred at a time, as in “YCrCb”.

[0056] The format of the "Assert Singal" command and the "Deassert SingalJ" command when transferring image data can be as follows, for example:

bitO: VSYNC

bitl: HSYNC

bit2: CSYNC

bit3: VBLANK

bit4: HBLANK

bit5: FLDO (Field Out Singal)

bit6—12: reserved In the present embodiment, the sequencer 144 in the controller 140 on the main system 110 side synchronizes the audio data with the image data, and then outputs it to the transfer unit 150. Since jitter generated after the transfer unit 150 is very small, it is not necessary to use a signal for synchronization control when transferring audio data.

Also, when transferring audio data, for example, 8-bit left and right channel data may be transferred all at once, but in this embodiment, audio data is transferred channel by channel. For example, for audio data of 8 bits and 2 channels, a number (virtual channel) is assigned to each channel and transferred. In this way, for example, it is possible to multiplex multi-channel audio data having more than two channels and output from the array speaker.

Also, the transfer format of the “Assert Singal” command and “Deassert S ingal” when transferring audio data can be “bit 0: mute ゝ bit 1-15: Reserved”; ^

The sequencer 144 of the controller 140 converts any type of real-time data into a first signal group that can be transferred by the same transfer unit 150 and outputs the first signal group to the transfer unit 150 in this way. Since the controller 140 is provided with a buffer 146 for temporarily storing the viewing data 136, the sequencer 144 executes the above-described “No Operation” command when a signal timing shift, so-called jitter, occurs. It is possible to adjust the timing by transmitting dummy data and absorb jitter.

The expansion interface 160 expands the signal transmitted via the transfer unit 150 into a second signal group suitable for the application and outputs the second signal group to the output destination device.

FIG. 9 is a block diagram showing the configuration of the deployment interface 160. The expansion interface 160 outputs the first signal group transmitted via the transfer unit 150 to the second signal group, and the expansion unit 164 and each signal included in the second signal group. Pins 16 and 8 are provided. In the illustrated example, the expansion interface 160 expands the first signal group into the image signals Y, Cr, Cb, and the audio signals L (left) and R (right) by the expansion unit 164, and the corresponding pins 168a. (Y), 168b (Cr), 168c (Cb), 168d (L), 168e (R) These pins 168 are provided according to the output destination device. By connecting to the corresponding pins in, each signal can be output to the device as the output destination.

[0063] Thus, according to the signal processing device 100 of the present embodiment, the main system 110 converts the viewing data 136 into 16-bit data, and interlaces with the control command to obtain the first signal group. . This first signal group is output to the expansion interface 160 via the transfer unit 150, and the expansion interface 160 expands the received first signal group into a format suitable for the output destination device and outputs it. Since the main system 110 and the deployment interface 160 are connected by a transfer unit 150 having a general format, the main system 110 and the deployment interface 160 can be designed and developed separately.

[0064] In addition, since the first signal group has already absorbed jitter and is suitable for a specific application, for example, the output destination device, the deployment interface ₁₆₀ is realized by a small amount of buffer and a simple conversion circuit. can do.

Also, if there is a change in the device type of the output destination, it is necessary to change the hardware such as the output pin of the deployment interface according to the output destination device. Force Controller 140 in the main system 110 Since the operation of the sequencer 144 can be changed by software, it is easy to change the specifications of the entire signal processing apparatus.

[0065] Although one embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and various modifications, increases / decreases, and improvements in details can be made without departing from the spirit of the present invention. I can bark.

[0066] For example, in order to easily distribute the gist of the present invention, the sequencer 144 of the controller 140, the transfer unit 150, and the deployment interface are compared with the signal processing device 100 of the embodiment shown in FIG. A plurality of 1S physical channels may be provided in which only one set (physical channel) consisting of 160 expansion units 164 is provided. In this way, wideband image data can be transferred separately for each image data processing unit, for example, for each pixel, and transfer of a frame rate or frame rate can be realized. Here, as an example, the processing unit of the image data is a pixel, and the force is such that each pixel is sequentially transferred through a separate physical channel. The processing unit of the image data is a line or a frame, and a plurality of lines or frames are arranged in parallel. Forward You may make it do. Furthermore, the image area represented by the image data may be divided into blocks, the processing unit of the image data may be a block, and a plurality of blocks may be transferred in parallel.

[0067] Of course, a signal processing apparatus provided with a plurality of physical channels can not only be effective in transferring wideband data at a high frame rate, but may be applied to various applications. As an example, the main system transfers block image data to be displayed in different areas on the display screen of one image playback device in parallel, and the expansion interface receives the received data of each block image as an image. By outputting to a playback device and displaying it in the corresponding area, multi-screen display by an image playback device such as a monitor or a television set can be realized.

[0068] Furthermore, by adjusting the number of physical channels for transferring each block image, the update frequency of different block images on one display surface can be made different. For example, assuming that the display screen of a game fighting on the stage is composed of the stage area and a description of the game or a simple background area, the image of the stage area has a high update frequency, whereas Images in such areas do not require high update frequency. In this case, for example, image data of the area such as the background may be transferred using one physical channel, and image data of the stage area may be transferred using two or more physical channels.

[0069] Further, the main system divides the image area represented by the image data into blocks, and transfers a plurality of blocks in parallel. The development interface receives the received data of each block in different image reproduction apparatuses. It is also possible to divide and display one image data on a plurality of image playback devices.

Further, in the signal processing apparatus 100 of the embodiment shown in FIG. 3, the main system 110 and the expansion interface 160 have only transmission / reception channels for viewing data transmitted from the main system 110 to the expansion interface 160. However, it is possible to further provide a transmission / reception channel for viewing data transmitted to the main system. In this way, it is possible to perform bi-directional transfer in which viewing data of device power connected to the development interface can also be transferred to the main system by the development interface. A system can be realized.

In addition, in the signal processing apparatus 100 shown in FIG. 3, in order to enhance security, the transfer unit 150 and other parts and the transfer unit 150 are not so seen that the pattern of the signal transferred by the transfer unit 150 is not visible. The connection part is shielded by parts on the same printed circuit board, but if it is intended to be used in an environment where security is not particularly considered, the transfer part etc. may not be shielded.

[0072] Further, in order to further enhance security, the main system 110 may encrypt and output the signal group to be output, that is, the first signal group.

Further, in the signal processing apparatus 100 shown in FIG. 3, the main system 110 and the deployment interface 160 are mounted on the same printed circuit board, and are connected by a transfer unit 150 having a signal line force such as a data node 154. However, the main system 110 and the deployment interface 160 may be mounted on separate printed circuit boards, and both may be connected by connectors. When connected with a connector, the security is lower than that of the signal processing apparatus 100 shown in FIG. 3, but the deployment interface can be replaced more easily. Of course, in this case, security may be enhanced by encrypting a signal group output from the main system side.

[0074] Of course, the specific control commands and the transfer formats of image data and audio data are not limited to those listed above! /.

In addition, the signal processing device according to the present invention is particularly effective in processing streaming data that requires low jitter, but the processing target of the signal processing device of the present invention is not limited to streaming data. Any kind of data may be used.

Industrial applicability

The present invention can be used for a signal processing device that converts data, particularly streaming data, into a signal group suitable for a predetermined application.

Claims

The scope of the claims

[1] A conversion transfer unit that inputs data, converts the data into a first signal group based on a predetermined conversion rule, and outputs the first signal group,

Conversion and transfer unit force The first signal group that is output is input, and the application-specific development unit that develops the second signal group suitable for a specific application.

The conversion rule is defined in common for a plurality of uses including the specific use, and the first signal group is formed as a signal group having a narrower bus width than the second signal group, And,

A signal processing apparatus, wherein the conversion transfer unit and the application specific development unit are incorporated in a separate semiconductor integrated circuit.

[2] The signal processing device according to claim 1, wherein the data is streaming data.

[3] The signal processing device according to claim 1 or 2, wherein the conversion transfer unit includes a built-in buffer, and once the data is input to the built-in buffer, the conversion processing to the first signal group is performed. A signal processing apparatus.

4. The signal processing apparatus according to claim 1, wherein the separate semiconductor integrated circuit is mounted on a single printed circuit board.

[5] The signal processing device according to any one of claims 1 to 4, wherein the signal processing device includes a plurality of conversion / transfer units and application-specific development units.

6. The signal processing device according to claim 5, wherein the plurality of application-specific development units included in the plurality of sets share processing for the same application.

[7] The signal processing device according to claim 6, wherein the plurality of conversion transfer units included in the plurality of sets divide the image data into predetermined processing units and output the divided data in parallel, and develop the plurality of uses according to the plurality of uses. The unit receives each processing unit and converts it into a second signal group, respectively.

8. The signal processing apparatus according to claim 7, wherein the processing unit corresponds to a display unit for image data.

[9] With the main processor, A main memory for storing data processed by the main processor;

After the data is input from the main memory and stored in the built-in buffer, the data is converted into the first signal group based on the predetermined conversion rule, and the conversion / transfer unit outputs the data. The first signal group is input and expanded to a second signal group suitable for a specific application,

A signal processing apparatus, wherein the conversion transfer unit and the application-specific development unit are respectively built in separate semiconductor integrated circuits mounted on a single printed circuit board.