WO2006128810A2

WO2006128810A2 - Method for communication or redundant data during address transmission on a multiplexed address/data bus

Info

Publication number: WO2006128810A2
Application number: PCT/EP2006/062540
Authority: WO
Inventors: Andreas Kneer; Axel Aue
Original assignee: Robert Bosch Gmbh
Priority date: 2005-06-01
Filing date: 2006-05-23
Publication date: 2006-12-07
Also published as: EP1891535A2; KR20080013973A; DE102005024988A1; WO2006128810A3; CN101189593A

Abstract

The invention relates to a method for communication between at least two subscribers (2, 3) of a communication system via a plurality of data lines (D0 - D31) of a data bus, some of these data lines being used as address lines (A0 - A23) of an address bus and data and addresses being transmitted in multiplex transmission. In order to facilitate a simple and inexpensive protection of the transmission path between the subscribers (2, 3), redundant data are transmitted via at least one of the data lines (D24 - D31) that is not used as the address line (A0 - A23) at the same time the address is transmitted via the address line (A0 - A23). Checksums (so-called check bits) are preferably transmitted as the redundant data. The inventive method is preferably used for communication between a microprocessor (3) and an external memory module (2).

Description

Method for communication between at least two users of a communication system

The present invention relates to a method for communication between at least two users of a communication system via a plurality of data lines of a data bus, some of which are used as address lines of an address bus, wherein data and addresses are multiplexed.

The invention also relates to a bus system for communication between at least two users of a communication system, wherein the bus system comprises a plurality of data lines of a data bus, some of which can be used as address lines of an address bus, wherein the transmission of data via the data lines and addresses via the address lines in the multiplex ,

Finally, the present invention also relates to a memory module associated with a microprocessor which is connected to the microprocessor via a plurality of data lines of a data bus, some of which can be used as address lines of an address bus, data and addresses being multiplexed. State of the art In known bus systems, communicate via the microprocessors with associated external memory, no protection of the transmission path is provided. If a fault or an error occurs during transmission, this will not be detected. On the one hand, an address transferred from the microprocessor to the memory can be misunderstood. On the other hand, data can be transferred incorrectly from the memory to the microprocessor. In both cases, the consequence is that in the

Microprocessor incorrect or incorrect data and there may lead to errors during processing. If, according to the prior art, disturbances are to be detected, the data transmitted between the memory and the microprocessor must be transmitted at least partially redundantly. However, additional bus lines are then required, causing significant additional costs and problems with implementation and integration with existing systems.

Using the example of a 32-bit bus system, a known communication between a microprocessor and an external memory will be explained. In such a bus system, 32-bit data and, for example, 24-bit addresses are multiplexed on the same bus lines. It is irrelevant whether the data is transferred between memory and microprocessor in burst or asynchronously. Memory access according to the known method proceeds as follows:

The processor applies a 24-bit address of a desired memory cell to the bus system and activates a Chip Select (CS) signal and an Address Latch Enable (ALE) signal. Shortly thereafter, the processor disables the ALE signal and the memory device remembers the ALE signal transmitted address and retrieves the data from the corresponding memory cell. In a data transfer in the burst, data is fetched from the corresponding memory cell and from subsequent memory cells. Then the processor switches via an Output Enable (OE) signal

Output driver of the memory module and reads the applied data.

Based on this prior art, the present invention, the object of a

Possibility to transmit redundant data without having to provide additional bus lines between the participants of the communication system.

To solve this problem is based on the

Communication method of the aforementioned type proposed that redundant data are transmitted simultaneously with the transmission of the address via the address lines via at least one of the data lines not used as an address line.

Advantages of the invention

Because the data bus in modern processors requires more lines (for example, 32 lines) than for the

Transmission of the addresses are necessary (for example, 24 lines), some bus lines are unused during the addressing phase. These unused bus lines are used according to the invention during the addressing phase for transmitting the redundant data, preferably in the form of data bits. The redundant information can be used to secure the transmission path between the participants of the communication system. In this way it is possible to provide with minimal effort, especially without additional bus lines too need to secure the transmission path between microprocessor and memory. As a result, transmission errors can be detected and appropriate measures taken. These measures may be, for example, to mark the transmitted data as faulty and to issue a corresponding notice to the user. A repetition of the data transmission is conceivable.

Advantageous embodiments of the invention are described in the subclaims. According to the embodiment according to claim 3, checksums (so-called check bits) are transmitted as redundant data. Preferably, a cross sum is formed over the data to be transmitted and, depending on whether the cross sum represents an even or an odd number, a "1" or a "0" is transmitted as a check bit.

As a further solution of the object of the present invention is proposed starting from the bus system of the type mentioned above, that the bus system comprises means for transmitting redundant data simultaneously with the transmission of the address via the address lines, wherein the means for transmitting the redundant data at least one of do not use data lines not used as address lines.

As yet another solution of the object of the present invention is proposed starting from the memory module of the type mentioned that the memory module has means for transmitting redundant data simultaneously with the transmission of addresses from the microprocessor to the memory module via the address lines, wherein the means for transmitting the use redundant data at least one of not used as an address line data lines. drawings

In the figures, preferred embodiments of the present invention are shown and explained in more detail in the following description of the figures. Show it:

1 shows a bus system according to the invention between a

Microprocessor and a memory module for implementing the method according to the invention according to a preferred embodiment;

Figure 2 shows an interconnection of certain signals in

Memory module for implementing the method according to the invention;

Figure 3 is a timing diagram of a plurality of signals in the

Realization of the present invention; and

Figure 4 is a timing diagram of several signals in the

Realization of a conventional, known from the prior art communication between the memory module and microprocessor.

Description of the embodiments

Basis of the present invention is a bus system, as shown for example in Figure 1 and is designated in its entirety by the reference numeral 1. The bus system 1 is arranged between a memory module 2 and a processor 3 (central processing unit (CPU)) of a microprocessor module 4. The memory module 2 includes, for example, a flash memory. In the exemplary embodiment illustrated, the bus system 1 comprises 32 bus lines BLO - BL31, which are connected to the Transmission of data from the memory module 2 to the microprocessor 3 are all used as data lines DO - D31 a data bus. For addressing one or more desired memory cells of the memory module 2 by the microprocessor 3, some of the bus lines BLO - BL31 are used as address lines AO - A23 of an address bus. In the bus system 1, the 32-bit data and the 24-bit addresses are multiplexed on the same bus lines BL0 - BL31. In addition, the bus system 1 has control lines, of which in FIG

Lines for Address Latch Enable (ALE), Output Enable (OE), Write Enable (WE) and Chip Select (CS) signals are shown.

A multiplexed memory access according to a known method proceeds as follows:

The microprocessor 3 applies the address (AO - A23) of the desired memory cell to the bus 1 and activates the CS and ALE signals (see Figure 4, ALE = LOW). Thereafter, the microprocessor 3 deactivates the ALE signal

(ALE = HIGH). The memory module 2 remembers the address and fetches the data from the or the corresponding memory cells. The microprocessor 3 switches on the OE signal output driver of the memory module 2 (OE = LOW) and reads the data. The corresponding chronological sequence of the signals is shown in FIG.

Since only 24-bit addresses are transmitted, but 32 data lines are available on the bus 1, according to the present invention, the remaining 8 data lines CO - C7 in the addressing phase for the transmission of redundant data, for example in the form of a checksum (a so-called check bits ), be used. As in the standard access (see Figure 3), the processor 3 sets the 24-bit address (AO - A23) and activates the ALE signal and the CS signal. In addition, the OE signal is also activated (compare FIG. 4, OE = LOW). Based on the fact that the ALE signal is LOW (activated), the memory module 2 according to the invention recognizes that, on the one hand, an address AO - A23 is present and the other output driver (driver) of the memory module 2 may be activated for the redundant data. Of the

Memory module 2 then places the redundant data on the bus lines BL24 - BL31 or on the corresponding unused data lines D24 - D31 during the addressing phase. By deactivating the ALE signal (ALE = HIGH), the microprocessor 3 takes over the redundant data (check bits), the memory module 2 adopts the address and switches over to the data output. The corresponding time sequence of the signals is shown in FIG.

Since the addresses are transmitted from the microprocessor 3 in the direction of memory module 2 and the data from the memory module 2 in the direction of microprocessor 3, in the memory module 2, the line for the OE signal of the individual driver (driver) of the memory module 2 with the line for the ALE Signal are logically linked. The required interconnection in the memory module 2 is shown in FIG. In FIG. 2, "Latch" denotes an address register, where the address applied by the microprocessor 3 is buffered.

Since the address phase is prior to the data transfer, the redundant data is in the

Addressing phase actually not available yet. The memory module 2 does not yet know what data it to the Microprocessor 3 should deliver. Therefore, the redundant data of the previous data transfer cycle (bus cycle) are always transmitted in the addressing phase. This means that the transmission of the redundant data lags behind the actual data transfer by one bus cycle. However, this is easily tolerated in most systems.

It is conceivable to provide in the memory module 2 an intermediate memory, a so-called cache memory, in which the data to be transmitted to the microprocessor 3 are first temporarily stored for a bus cycle before they are transmitted. However, the redundant data can be transmitted from the buffer and the microprocessor 3 in the addressing phase of the memory module 2 to the microprocessor 3 before the data transfer. This means that in the addressing phase of a specific bus cycle, the address of the desired memory cell for the subsequent bus cycle is transmitted from the microprocessor 3 to the memory module 2. At the same time, the transmission of the redundant data to the data stored in the buffer memory data of the previous bus cycle to the microprocessor 3. Only in the subsequent bus cycle then stored in the buffer data is transmitted to the microprocessor 3. According to this embodiment of the invention are at the time of receiving the data from the memory module 2 at the microprocessor 3 already before the redundant data, so that their error-free transmission can be checked immediately.

The generation of the redundant data, in particular the checksum (the so-called check bits) in the memory module 2 and the evaluation in the microprocessor 3 can after itself known methods are performed. For asynchronous data transfer between the memory module

2 and the microprocessor 3, it is sufficient if only one check bit is transmitted as redundant data, which contains information on whether the checksum over the data to be transmitted is an even or an odd number. This means that in the case of an asynchronous data transmission, a single data line which is not used as an address line is already sufficient in order to be able to implement the method according to the invention.

Of course, it is also possible to transmit additional redundant data, wherein the redundant data can then comprise more than 1 bit and thus also require more than one data line for the transmission of redundant data.

In a data transmission in the burst mode, the address of a first memory cell is transmitted to the memory module 2 by the processor 3. Starting from this first memory cell, data of this memory cell and several subsequent memory cells are sent to the microprocessor

3 transferred. This means that no address phases are provided between the successive data transmission phases, or only one address phase is provided for several data transmission phases. Nevertheless, even with a data transmission in the burst mode, the present invention can be used, for example, by determining check bits for the data to be transmitted in the individual data transmission phases and then checking the check bits in the following

Addressing phase are transmitted to the microprocessor 3 via the unused data lines.

For example, in the above-described embodiment, 8 unused data lines CO-C7 are available during the addressing phase, a check bit for the data transmitted during a data transmission phase can be transmitted via each of these 8 data lines CO - C7. Thus check bits for up to eight data packets of eight consecutive data transmission phases can be transmitted in a single address phase.

Claims

claims

Method for communication between at least two subscribers (2, 3) of a communication system via a plurality of data lines (DO - D31) of a data bus, some of which are used as address lines (AO - A23) of an address bus, wherein data and addresses are multiplexed , characterized in that redundant data are transmitted simultaneously with the transmission of the address via the address lines (AO - A23) via at least one of the data lines (D24 - D31) not used as address line.

2. The method according to claim 1, characterized in that the redundant data are assigned to the previously in a previous bus cycle via the data lines (DO - D31) transmitted data.

3. The method according to claim 1 or 2, characterized in that are transmitted as redundant data checksums.

4. The method according to any one of claims 1-4, characterized in that the method for communication between a microprocessor (3) and an external memory (2) is executed.

5. Bus system (1) for communication between at least two subscribers (2, 3) of a communication system, wherein the bus system (1) comprises a plurality of data lines (DO - D31) of a data bus, some of which can be used as address lines (AO - A23) of an address bus are, with the

Transmission of data via the data lines (DO - D31) and addresses via the address lines (AO - A23) in the multiplex, characterized in that the bus system (1) comprises means for transmitting redundant data simultaneously with the transmission of the address via the

Address lines (AO - A23), wherein the means for transmitting the redundant data use at least one of the non-used as an address line data lines (D24 - D31).

6. bus system (1) according to claim 5, characterized in that the bus system (1) comprises means for carrying out the method according to one of claims 2-4.

7. A memory module (2) associated with a microprocessor (3) which is connected to the microprocessor (3) via a plurality of data lines (DO-D31) of a data bus, some of which being usable as address lines (AO-A23) of an address bus, wherein Data and addresses are transmitted in the multiplex, characterized in that the memory module (2) comprises means for transmitting redundant data simultaneously with the transmission of the address from the microprocessor (3) to the memory module (2) via the address lines (AO - A23), wherein the Means for transmitting the redundant data use at least one of the non-used as an address line data lines (D24 - D31).

8. Memory module (2) according to claim 7, characterized in that the means as a switch for switching the at least one not as address lines (AO - A23) used data line (D24 - D31) between data transmission and the transmission of the redundant data are formed.