WO2006128810A3 - Method for communication or redundant data during address transmission on a multiplexed address/data bus - Google Patents

Method for communication or redundant data during address transmission on a multiplexed address/data bus Download PDF

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Publication number
WO2006128810A3
WO2006128810A3 PCT/EP2006/062540 EP2006062540W WO2006128810A3 WO 2006128810 A3 WO2006128810 A3 WO 2006128810A3 EP 2006062540 W EP2006062540 W EP 2006062540W WO 2006128810 A3 WO2006128810 A3 WO 2006128810A3
Authority
WO
WIPO (PCT)
Prior art keywords
address
communication
data
redundant data
transmitted
Prior art date
Application number
PCT/EP2006/062540
Other languages
German (de)
French (fr)
Other versions
WO2006128810A2 (en
Inventor
Andreas Kneer
Axel Aue
Original Assignee
Bosch Gmbh Robert
Andreas Kneer
Axel Aue
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bosch Gmbh Robert, Andreas Kneer, Axel Aue filed Critical Bosch Gmbh Robert
Priority to EP06763233A priority Critical patent/EP1891535A2/en
Publication of WO2006128810A2 publication Critical patent/WO2006128810A2/en
Publication of WO2006128810A3 publication Critical patent/WO2006128810A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

The invention relates to a method for communication between at least two subscribers (2, 3) of a communication system via a plurality of data lines (D0 - D31) of a data bus, some of these data lines being used as address lines (A0 - A23) of an address bus and data and addresses being transmitted in multiplex transmission. In order to facilitate a simple and inexpensive protection of the transmission path between the subscribers (2, 3), redundant data are transmitted via at least one of the data lines (D24 - D31) that is not used as the address line (A0 - A23) at the same time the address is transmitted via the address line (A0 - A23). Checksums (so-called check bits) are preferably transmitted as the redundant data. The inventive method is preferably used for communication between a microprocessor (3) and an external memory module (2).
PCT/EP2006/062540 2005-06-01 2006-05-23 Method for communication or redundant data during address transmission on a multiplexed address/data bus WO2006128810A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP06763233A EP1891535A2 (en) 2005-06-01 2006-05-23 Method for communication between at least two subscribers of a communication system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102005024988.4 2005-06-01
DE102005024988A DE102005024988A1 (en) 2005-06-01 2005-06-01 Method for communication between at least two users of a communication system

Publications (2)

Publication Number Publication Date
WO2006128810A2 WO2006128810A2 (en) 2006-12-07
WO2006128810A3 true WO2006128810A3 (en) 2007-03-08

Family

ID=37057311

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2006/062540 WO2006128810A2 (en) 2005-06-01 2006-05-23 Method for communication or redundant data during address transmission on a multiplexed address/data bus

Country Status (5)

Country Link
EP (1) EP1891535A2 (en)
KR (1) KR20080013973A (en)
CN (1) CN101189593A (en)
DE (1) DE102005024988A1 (en)
WO (1) WO2006128810A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8656082B2 (en) * 2008-08-05 2014-02-18 Micron Technology, Inc. Flexible and expandable memory architectures
DE102008064761B3 (en) * 2008-09-30 2013-06-13 Infineon Technologies Ag Method for asynchronously transmitting control signals from transmitter to receiver, involves logically combining control signals with each other at receiver end, where logic combination result is transmitted to transmitter end
DE102008049662B4 (en) 2008-09-30 2012-07-12 Infineon Technologies Ag Method and device for checking asynchronous transmission of control signals
US20160188519A1 (en) * 2014-12-27 2016-06-30 Intel Corporation Method, apparatus, system for embedded stream lanes in a high-performance interconnect

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1988009012A1 (en) * 1987-05-14 1988-11-17 Digital Equipment Corporation Automatic sizing memory system
EP0905631A2 (en) * 1997-09-26 1999-03-31 Hewlett-Packard Company Microprocessor with multiplexed and non-multiplexed address/data busses
US20030101309A1 (en) * 2001-11-06 2003-05-29 Kuan-Chou Chen Memory access interface for a micro-controller system with address/data multiplexing bus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1988009012A1 (en) * 1987-05-14 1988-11-17 Digital Equipment Corporation Automatic sizing memory system
EP0905631A2 (en) * 1997-09-26 1999-03-31 Hewlett-Packard Company Microprocessor with multiplexed and non-multiplexed address/data busses
US20030101309A1 (en) * 2001-11-06 2003-05-29 Kuan-Chou Chen Memory access interface for a micro-controller system with address/data multiplexing bus

Also Published As

Publication number Publication date
KR20080013973A (en) 2008-02-13
CN101189593A (en) 2008-05-28
WO2006128810A2 (en) 2006-12-07
EP1891535A2 (en) 2008-02-27
DE102005024988A1 (en) 2006-12-07

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