WO2006057963A3 - Memory transaction burst operation and memory components supporting temporally multiplexed error correction coding - Google Patents

Memory transaction burst operation and memory components supporting temporally multiplexed error correction coding Download PDF

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Publication number
WO2006057963A3
WO2006057963A3 PCT/US2005/042153 US2005042153W WO2006057963A3 WO 2006057963 A3 WO2006057963 A3 WO 2006057963A3 US 2005042153 W US2005042153 W US 2005042153W WO 2006057963 A3 WO2006057963 A3 WO 2006057963A3
Authority
WO
WIPO (PCT)
Prior art keywords
ecc
data
memory
temporally multiplexed
addressable
Prior art date
Application number
PCT/US2005/042153
Other languages
French (fr)
Other versions
WO2006057963A2 (en
Inventor
Pete Vogt
Original Assignee
Intel Corp
Pete Vogt
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp, Pete Vogt filed Critical Intel Corp
Priority to CN2005800336312A priority Critical patent/CN101036131B/en
Priority to JP2007543351A priority patent/JP4777358B2/en
Priority to DE112005002390T priority patent/DE112005002390T5/en
Publication of WO2006057963A2 publication Critical patent/WO2006057963A2/en
Publication of WO2006057963A3 publication Critical patent/WO2006057963A3/en
Priority to GB0706172A priority patent/GB2433624B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0879—Burst mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/287—Multiplexed DMA
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1027—Static column decode serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled bit line addresses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Dram (AREA)
  • Detection And Correction Of Errors (AREA)
  • Memory System (AREA)

Abstract

Methods and apparatus for use with memory systems and memory modules are included among the embodiments. In exemplary systems, error-correction coding (ECC) data is temporally multiplexed with user data on the same data bus lines in a burst mode transfer, such that separate chips and data lines are not required to support ECC. The memory devices on the modules each contain additional indirectly addressable ECC segments associated with addressable segments of the device. The temporally multiplexed ECC data is read from and written to the indirectly addressable segment associated with the addressable data transmitted in the burst mode transfer. In some embodiments, two types of burst modes are supported, one which includes ECC data and one which does not.This allows one type of memory module to support both ECC and non-ECC systems, and in some cases to use ECC for some data and not for other data in the same system. Other embodiments are described and claimed.
PCT/US2005/042153 2004-11-22 2005-11-17 Memory transaction burst operation and memory components supporting temporally multiplexed error correction coding WO2006057963A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN2005800336312A CN101036131B (en) 2004-11-22 2005-11-17 Memory transaction burst operation and memory components supporting temporally multiplexed error correction coding
JP2007543351A JP4777358B2 (en) 2004-11-22 2005-11-17 Memory transaction burst operation and memory components supporting time multiplexed error correction coding
DE112005002390T DE112005002390T5 (en) 2004-11-22 2005-11-17 Burst operation for the memory transaction and memory components supporting intermittent error correction coding
GB0706172A GB2433624B (en) 2004-11-22 2007-03-29 Memory transaction burst operation and memory components supporting temporally multiplexed error correction coding

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/995,850 US7464241B2 (en) 2004-11-22 2004-11-22 Memory transaction burst operation and memory components supporting temporally multiplexed error correction coding
US10/995,850 2004-11-22

Publications (2)

Publication Number Publication Date
WO2006057963A2 WO2006057963A2 (en) 2006-06-01
WO2006057963A3 true WO2006057963A3 (en) 2006-07-20

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/042153 WO2006057963A2 (en) 2004-11-22 2005-11-17 Memory transaction burst operation and memory components supporting temporally multiplexed error correction coding

Country Status (8)

Country Link
US (1) US7464241B2 (en)
JP (2) JP4777358B2 (en)
KR (1) KR100884096B1 (en)
CN (1) CN101036131B (en)
DE (1) DE112005002390T5 (en)
GB (1) GB2433624B (en)
TW (1) TWI304591B (en)
WO (1) WO2006057963A2 (en)

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Also Published As

Publication number Publication date
JP5399442B2 (en) 2014-01-29
KR100884096B1 (en) 2009-02-19
JP2011243206A (en) 2011-12-01
KR20070051930A (en) 2007-05-18
GB2433624B (en) 2008-10-15
US20060123320A1 (en) 2006-06-08
CN101036131A (en) 2007-09-12
TWI304591B (en) 2008-12-21
TW200627469A (en) 2006-08-01
CN101036131B (en) 2011-01-26
JP4777358B2 (en) 2011-09-21
US7464241B2 (en) 2008-12-09
DE112005002390T5 (en) 2007-10-11
GB2433624A (en) 2007-06-27
WO2006057963A2 (en) 2006-06-01
GB0706172D0 (en) 2007-05-09
JP2008521160A (en) 2008-06-19

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