DE10311428A1 - Memory error checking device, especially for RAM or ROM memory chips, can be user-configured to carry out different combinations of checking and correction to suit user preferences - Google Patents

Abstract

Device for detection and correction of errors in a data read out from a storage device, said device being capable of being configured. For example, it can be configured to carry out error detection or not, to detect errors and not to correct them or to detect errors and correct them, but to carry out only one error correction stage.

Description

Detection and / or device Correction of errors in data read from a memory device Data The present invention relates to a device according to the preamble of claim 1, i.e. a device for detection and / or Correction of errors in data read from a memory device Data.

With advancing technology development, more precisely said due to the ever smaller structures in storage devices or other integrated circuits or circuit parts the likelihood of errors in from a storage device read data to one extent to that at least in the case of security-relevant applications to the detection and / or the correction of such errors can no longer be dispensed with.

Devices and methods for detection and / or Correction of errors in data read from a memory device Data has been known for a long time.

The error detection can, for example, under So-called parity bits are used. Each will Time when data is written into the storage device a parity bit is generated for this data and in the same storage device or another storage device. Will the in data stored in the storage device at a later time the parity bit assigned to this data is also read out read out and checked whether the The data read out can be the data required for the generation of the read out parity bits. If this is the case, then assumed that the read data contain no error. Otherwise it will assumed that the read data contain an error, but this error is generally not localizable and correctable.

Error correction is possible if instead of parity bits an error correction code or ECC data is generated and evaluated become. Doing so every time data is stored in the storage device are written, ECC data is generated from this data and in the same storage device or another storage device. Will the in data stored in the storage device is then read out at a later point in time, the ECC data assigned to this data is also read out in this way and checked if the Data read out can be the data required for the generation of the read ECC data. If this is the case, then assumed that the read data contain no error. Otherwise it will assumed that the read data contain an error, this error under Use of the read ECC data can be localized and corrected is.

• – von Fehlererkennung gesprochen wird, wenn durch die zugrundeliegende Überprüfung "nur" erkannt werden kann, daß Fehler vorhanden sind, die vorhandenen Fehler aber nicht korrigiert werden können,
• – von Fehlerkorrektur gesprochen wird, wenn durch die zugrundeliegende Überprüfung vorhandene Fehler korrigiert werden können, und
• – auch dann von Fehlerkorrektur gesprochen wird, wenn durch die zugrundeliegende Überprüfung bestimmte Fehler nur erkannt, aber bestimmte Fehler auch korrigiert werden können.

To avoid misunderstandings, it should be noted that above and below

• - the term "error detection" is used if the underlying check can "only" detect that errors are present but the existing errors cannot be corrected,
• - One speaks of error correction if existing errors can be corrected by the underlying check, and
• - Error correction is also spoken of if certain errors can only be recognized by the underlying check but certain errors can also be corrected.

Both an error detection and first quite an error correction require measures that lead to the registered letter of data in the storage device and the reading of data require more time from the memory device than it would without error detection and / or error correction would be the case. This leads to a with an error detection and / or error correction system a lower clock frequency and / or with a larger number of Wait States must work as it would be possible without error detection and / or error correction. This is particularly important for systems in which there is no error detection and / or error correction is required, a disadvantage.

In order to meet all possible needs, it is necessary that storage facilities and building blocks containing storage devices in various Variants are offered, namely in a variant with error detection and / or error correction, and in a variant without error detection and / or error correction. However, this requires a great deal of effort on the part of the manufacturer.

The present invention lies therefore the task of the device according to the preamble of the claim 1 in such a way that they can be used both in systems in which an error detection and / or error correction is imperative, as well as in systems can be used in which a maximum working speed the highest priority Has.

This object is achieved by the solved in claim 1 device.

The device according to the invention stands out in that they is configurable by the user.

• – eine Vorrichtung, die in der Lage ist, eine Fehlererkennung durchzuführen, so zu konfigurieren, daß sie keine Fehlererkennung durchführt, und/oder
• – eine Vorrichtung, die in der Lage ist, eine Fehlerkorrektur durchzuführen, so zu konfigurieren, daß sie keine Fehlerkorrektur durchführt, und/oder
• – eine Vorrichtung, die in der Lage ist, sowohl eine Fehlererkennung als auch eine Fehlerkorrektur durchzuführen, so zu konfigurieren, daß sie nur eine Fehlererkennung durchführt, und/oder
• – eine Vorrichtung, die in der Lage ist, sowohl eine Fehlererkennung als auch eine Fehlerkorrektur durchzuführen, so zu konfigurieren, daß sie nur eine Fehlerkorrektur durchführt, und/oder
• – eine Vorrichtung, die in der Lage ist, verschiedene Arten von Fehlererkennung durchzuführen, so zu konfigurieren, daß sie eine ganz bestimmte Art von Fehlererkennung durchführt, und/oder
• – eine Vorrichtung, die in der Lage ist, verschiedene Arten von Fehlerkorrektur durchzuführen, so zu konfigurieren, daß sie eine ganz bestimmte Art von Fehlerkorrektur durchführt.

This makes it possible, for example, but not exclusively,

• To configure a device which is capable of performing an error detection so that it does not carry out an error detection, and / or
• - a device that is capable of a failure perform correction, configure so that it does not correct errors, and / or
• - to configure a device which is able to carry out both an error detection and an error correction so that it only carries out an error detection, and / or
• To configure a device which is able to carry out both an error detection and an error correction so that it only carries out an error correction, and / or
• To configure a device capable of carrying out different types of fault detection in such a way that it carries out a specific type of fault detection, and / or
• - Configure a device capable of performing different types of error correction to perform a specific type of error correction.

This allows a device for Detection and / or correction of errors in from a memory device read data optimally to the needs of the user and the Operating conditions adapted become.

The invention is described below of embodiments with reference to the figure explained.

The figure shows a block diagram the device presented here for detection and / or correction errors in data read from a memory device.

The device described below for Detection and / or correction of errors in from a memory device The data read out is part of a in the example considered program-controlled unit, for example a microprocessor, a microcontroller or a signal processor; the storage device is an internal memory of the program-controlled unit.

The device described for Detection and / or correction of errors in from a memory device read data could but also be part of any other circuit, for example Part of a memory chip.

The storage device is in the example considered by a fleeting one Memory, for example formed by a RAM. It could be but also a non-volatile one Act storage such as a flash memory. The stake the described device for the detection and / or correction of Errors in data read from a memory device can prove to be advantageous even with a ROM.

The arrangement shown in the figure contains the Device for detection and / or correction described below errors in data read from a memory device, as well as the storage device.

The storage device is with the Reference numeral MEM1 denotes and is hereinafter referred to as the first storage device designated.

The arrangement shown in the figure in addition to the first memory device MEM1, a second memory device MEM2 for storing for error detection and / or error correction required Data, a device EC1 for generating the for error detection and / or error correction required Data, a device EC2 for evaluating the error detection and / or error correction required Data, an error correction device EC3, and a control register ECCTRL to control devices EC1 and EC2 for generation and evaluation of the for error detection and / or error correction required Data and the error correction device EC3.

In the memory device MEM1 writing data will be over this a write data bus WBUS supplied. Data read out from the memory device MEM1 are transmitted via a first Read data bus RBUS1 output from this, if necessary by the error correction device EC3 corrected and over forwarded a second read data bus RBUS2 to the device, which requested the data. The buses mentioned have been considered Example, a width of 16 bits each, but can also be any number be wider or narrower.

• – eine Fehlererkennung, genauer gesagt eine Erkennung von Fehlern in aus der ersten Speichereinrichtung MEM1 ausgelesenen Daten erfolgen soll, oder
• – eine Fehlerkorrektur, genauer gesagt eine Korrektur von Fehlern in aus der ersten Speichereinrichtung MEM1 ausgelesenen Daten erfolgen soll, oder
• – weder eine Fehlererkennung noch eine Fehlerkorrektur erfolgen soll.

In the example under consideration, the control register ECCTRL contains two control bits which are designated by the reference symbols ECC_EN and C_EN. As will be described in more detail later, the control bits C_EN and ECC_EN in the example considered determine whether

• An error detection, more precisely a detection of errors in data read out from the first memory device MEM1, or
• An error correction, more precisely a correction of errors in data read out from the first memory device MEM1, or
• - Neither an error detection nor an error correction should take place.

If the control bit C_EN has the value 1, it means that either an error detection or an error correction is to take place, wherein it depends on the value of the control bit ECC_EN whether an error detection or an error correction is made. Otherwise, i.e. if that Control bit C_EN has the value 0, this means that neither an error detection an error correction should be made; the value of the control bit In this case, ECC_EN is meaningless.

If the control bit C_EN has the value 1, and the control bit ECC_EN has the value 1, this means that a Error correction should take place. Otherwise, i.e. if the control bit ECC_EN has the value 0, this means that an error is detected should.

Of course, any other can Assignment between the values of the control bits and their meaning be provided.

The control register ECCTRL, and therefore also the control bits C_EN and ECC_EN can by be described to the users of the arrangement. The content of the tax register ECCTRL can preferably at any time, in particular also during the normal operation of the arrangement can be changed. It can prove to be advantageous if the control register ECCTRL by a nonvolatile Memory is formed.

The device EC1 already mentioned above is used to generate the for error detection and / or error correction required Data and contains a parity bit generator PGEN, an ECC data generator ECCGEN, a first multiplexer MUX1, and a second multiplexer MUX2.

The parity bit generator is PGEN connected and generated on the input side to the write data bus WBUS per data word, which in the example considered comprises 16 bits, but also any longer or longer shorter can be a parity bit used for error detection and gives this to the first multiplexer MUX1.

The ECC data generator ECCGEN is also connected and generated on the input side to the write data bus WBUS for each ECC data used for error correction and outputs it to the first multiplexer MUX1.

• – wenn das später ausgelesene Datenwort nur einen Fehler enthält, kann dieser erkannt und korrigiert werden,
• – wenn das später ausgelesene Datenwort zwei Fehler enthält, können diese erkannt, aber nicht mehr lokalisiert und korrigiert werden,
• – und wenn ein Datenwort drei Fehler enthält, ist weder eine Erkennung noch eine Korrektur dieser Fehler gewährleistet bzw. möglich.

In the example under consideration, the ECC data are formed by a so-called SEC-DED code. SEC-DED means single error correction - double error detection and enables 1 error to be corrected or 2 errors to be recognized when the data word on which the ECC data is based is subsequently read out. that is,

• - if the data word read out later contains only one error, this can be recognized and corrected,
• - if the data word read out later contains two errors, these can be recognized, but can no longer be localized and corrected,
• - And if a data word contains three errors, neither detection nor correction of these errors is guaranteed or possible.

Of course, the ECC data generator ECCGEN also generates ECC data using any other codes are generated.

The parity bit generator PGEN and the ECC data generator ECCGEN work in parallel, i.e. produce the data they generate at the same time, the generation of ECC data generally take more time is called the generation of the parity bit.

The first multiplexer MUX1 gets the output signals of the parity bit generator as input signals PGEN and the ECC data generator ECCGEN fed and is controlled by the control bit ECC_EN. The MUX1 multiplexer switches the data output by the ECC data generator ECCGEN if the control bit ECC_EN has the value 1, and switches the from the parity bit generator PGEN output data if the control bit ECC_EN has the value 0.

The output from the first multiplexer MUX1 Data is fed to the second multiplexer MUX2.

The second multiplexer MUX2 points still a second input connection, with this second Input connection permanently the value 0 is created.

The second multiplexer MUX2 controlled by the control bit C_EN. He switches the him from first Multiplexer MUX1 fed Data through if the control bit C_EN has the value 1, and he switches the data "0" through when the Control bit C_EN has the value 0.

The from the second multiplexer MUX2 Output data are in the second memory device MEM2 written.

In the second storage device MEM2 are either those generated by the parity bit generator PGEN Data, or the data generated by the ECC data generator ECCGEN, or written zeros. It depends it exclusively from the control bits C_EN and ECC_EN, which data in the second Storage device MEM2 are written. If the control bit C_EN has the value 0, zeros are stored in the second memory device Written MEM2; if the control bit C_EN has the value 1, and the control bit ECC_EN the value 0, are those of the parity bit generator PGEN generated data written in the second memory device MEM2; if the control bit C_EN is 1 and the control bit ECC_EN the value 1, are generated by the ECC data generator ECCGEN Data written in the second memory device MEM2.

The in the second memory device MEM2 saved data will be later used to error in from the first memory device MEM1 be able to recognize and / or correct read data.

When data stored in the first memory device MEM1 is read out, the associated data from the second memory device MEM2 are automatically output from the second memory device MEM2 essentially simultaneously with the output of this data. Both data, ie both the data output from the first storage device MEM1 and the data output from the second storage device MEM2 are supplied to the above-mentioned device EC2, which then checks whether the data output from the first storage device MEM1 is the data, that of generating the from the second storage device device MEM2 based on the data output.

The device EC2 and contains an ECC data evaluation device ECCCHK, a parity bit evaluation device PCHK, a first AND gate AND1, a second AND gate AND2, an OR gate OR, and one Multiplexer MUX3.

• 1) daß die aus der ersten Speichereinrichtung MEM1 ausgegebenen Daten fehlerfrei sind, d.h. genau die zuvor in die erste Speichereinrichtung MEM1 geschriebenen Daten sind, oder
• 2) daß die aus der ersten Speichereinrichtung MEM1 ausgegebenen Daten einen Fehler enthalten, oder
• 3) daß die aus der ersten Speichereinrichtung MEM1 ausgegebenen Daten zwei Fehler enthalten.

Both the data output from the first storage device MEM1 and the data output from the second storage device MEM2 are fed to the ECC data evaluation device ECCCHK. The ECC data evaluation device ECCCHK assumes that the data output from the second memory device MEM2 are the ECC data belonging to the data output from the first memory device MEM1, and checks whether the data output from the first memory device MEM1 Data can be the data on which the generation of the (ECC) data output from the second memory device MEM2 is based. Here, the ECC data evaluation device ECCCHK can come to three different results, namely

• 1) that the data output from the first memory device MEM1 are error-free, ie are exactly the data previously written into the first memory device MEM1, or
• 2) that the data output from the first memory device MEM1 contain an error, or
• 3) that the data output from the first memory device MEM1 contain two errors.

The ECC data evaluation device ECCCHK generated in dependence an output signal DE (double error) and a large number of output signals SE (single error). The number of output signals SE corresponds the number of bits that come from the first storage device Data words output MEM1 include. In the example considered generates the ECC data evaluation device ECCCHK thus an output signal DE and 16 output signals SE. In the figure is for better clarity only one output signal SE shown.

The output signal DE signals the ECC data evaluation device ECCCHK whether from the first storage device Data output from MEM1 contain two errors or not. DE = 1 means that the ECC data evaluation device ECCCHK determined during the check carried out by it has that data output from the first memory device MEM1 two Errors included. DE = 0 means that this is not the case.

The signals through the output signals SE ECC data evaluation device ECCCHK whether from the first storage device Data output from MEM1 contain 1 error or not, and which one Bit of the data output from the first memory device MEM1 is faulty. Each of the several output signals SE is an output signal SE a specific bit from the first memory device MEM1 assigned data assigned. By an output signal SE that has the value 0, it is signaled that the assigned bit is off data output to the first memory device MEM1 without errors is; by an output signal SE, which has the value 1 signals that the assigned bit of the data output from the first memory device MEM1 is faulty and must be inverted for correction.

With the evaluation result mentioned above 1) the ECC data evaluation device ECCCHK have both the output signals SE and the output signal DE to 0; in the evaluation result 2) one of the output signals SE to 1 and all other output signals to 0; in the evaluation result 3) all output signals SE have the Value 0 and the output signal DE the value 1.

Of those from the ECC data evaluation facility Output signals generated by ECCCHK become the output signals SE supplied to the error correction device EC3, and the output signal DE the first AND gate AND1.

The parity bit evaluation device already mentioned above PCHK become - like that ECC data evaluation device ECCCHK - both those from the first Memory device MEM1 output data as well as the data from the second Memory device MEM2 supplied data output. The Parity bit evaluation device PCHK assumes that the the second memory device MEM2 output data the parity bits that are output from the first memory device MEM1 Data belongs and checks whether the data output from the first memory device MEM1 could be, that were used to generate the supposed parity bits.

The parity bit evaluation device PCHK generates a representative of the result of the check Output. This output signal has the value 1 if the data output from the first storage device MEM1 is the data could be, which were used to generate the supposed parity bits, that is, when the data output from the first memory device MEM1 Data is believed to be free of errors. The output signal has the value 0 if this is not the case, that is to say from the first memory device MEM1 output data contain errors.

The output signal of the parity bit evaluation device PCHK is fed to the second AND gate AND2.

The parity bit evaluation device PCHK and the ECC data evaluation device ECCCHK work in parallel, ie evaluate the data output from the second memory device MEM2 simultaneously. Since the data output from the second memory device MEM2 are only either parity bits or ECC data, only either the evaluation result of the parity bit evaluation device PCHK or the evaluation result of the ECC data evaluation device ECCCHK can be correct. Regardless of this, the evaluation of the data by the ECC data evaluation device ECCCHK will generally take more time than the evaluation of the data by the parity bit evaluation device PCHK.

The inverted control bit becomes the AND gate AND2 ECC_EN supplied as a second input signal. The AND gate AND2 undergoes those fed to him AND link signals and gives the result of this combination to the OR gate OR out.

The first AND gate mentioned above AND1 also has two input ports. This is at the first input connection Output signal DE of the ECC data evaluation device ECCCHK applied, and the control bit ECC_EN to the second input connection. The AND gate AND1 ANDs the signals fed to it and returns the result of this link to the OR gate OR.

The OR gate OR subjects the Output signals from the AND gates AND1 and AND2 of an OR operation and sends the result of this link to the multiplexer MUX3 out.

The multiplexer MUX3 has one further input connection. This is another input port permanently set to the value 0. The multiplexer MUX3 is through controls the control bit C_EN and switches the output signal of the OR gate OR through, if the control bit C_EN has the value 1 and switches through the zero data, if the control bit C_EN has the value 0.

The output signal of the multiplexer MUX3 is used as an error signal ERR. With this error signal ERR is displayed whether the data from the first memory device MEM1 output data contain one or more non-correctable errors or not. ERR = 1 indicates that the data from the first storage device MEM1 output data one or more uncorrectable errors contain; ERR = 0 indicates that the data from the first memory device MEM1 output data no such error, either at all no error or "only" a correctable Errors included.

The error signal is ERR either the output signal DE of the ECC data evaluation device ECCCHK, or the output signal of the parity bit evaluation device PCHK, or has a permanent value of 0.

• – weist dauerhaft den Wert 0 auf, wenn das Steuerbit C_EN den Wert 0 aufweist,
• – ist das Ausgangssignal DE der ECC-Daten-Auswertungseinrichtung ECCCHK, wenn das Steuerbit C_EN den Wert 1 aufweist und gleichzeitig auch das Steuerbit ECC_EN den Wert 1 aufweist, und
• – ist das Ausgangssignal Parity-Bit-Auswertungseinrichtung PCHK, wenn das Steuerbit C_EN den Wert 1 aufweist und gleichzeitig das Steuerbit ECC_EN den Wert 0 aufweist.

The error signal ERR

• Has the value 0 permanently if the control bit C_EN has the value 0,
• - is the output signal DE of the ECC data evaluation device ECCCHK if the control bit C_EN has the value 1 and at the same time the control bit ECC_EN has the value 1, and
• - The output signal is a parity bit evaluation device PCHK if the control bit C_EN has the value 1 and at the same time the control bit ECC_EN has the value 0.

The from the first memory device MEM1 Output data are already if necessary by the above mentioned Error correction device EC3 corrected. A need exists if the control bits C_EN and ECC_EN have the value 1, and the ECC data evaluation device ECCCHK in the output from the first memory device MEM1 Data has found a correctable error.

The error correction device EC3 contains pro Bit of the data output from the first memory device MEM1 an AND gate AND3 and a multiplexer MUX4. More specifically is each bit of the output from the first memory device MEM1 Data has its own AND gate AND3 and its own multiplexer MUX4 assigned. In the figure, the components mentioned are for better clarity for the sake of simplicity only.

The MUX4 multiplexer has two input connections, where at the one input terminal a bit from the first Output memory MEM1 data is applied, and to the other input connection of the inverse value of this bit.

The MUX4 multiplexer is Output signal of the AND gate AND3 controlled. If the output signal of the AND gate AND3 has the value 0, switches the multiplexer MUX4 that from the first memory device MEM1 output bits by and when the output of the AND gate AND3 has the value 1, the multiplexer MUX4 switches the inverse Bit through. By switching the inverse bit, a Change, more specifically a correction of the from the first storage device Bits output MEM1.

The AND gate AND3 has three input terminals. At the first input port the control bit C_EN is applied, the control bit to the second input connection ECC_EN, and to the third input terminal the output signal SE, which that fed to the multiplexer MUX 4 Bit of the data output from the first memory device MEM1 assigned.

The AND gate AND3 undergoes the fed to him AND link signals and gives the result of this link to the control port of the multiplexer MUX4 off.

The output signal of the AND gate AND3 has the value 1 only if the control bits C_EN and ECC_EN have the value 1, and if by the output signal supplied to the AND gate SE is signaled to the ECC data evaluation device ECCCHK, that this assigned bit of the output from the first memory device MEM1 Data is incorrect and can be corrected by inverting.

As from the above explanations can be seen, the user of the arrangement can the arrangement by configure the control bits C_EN and ECC_EN as required. He can by set the control bit C_EN whether there is any error detection and / or error correction should take place, and it can - if C_EN has the value 1 - by set the control bit ECC_EN whether "only" one error detection using parity bits or but an error correction using ECC data can be carried out immediately should.

• – am schnellsten erfolgen kann, wenn weder eine Fehlererkennung noch eine Fehlerkorrektur (C-EN=0) erfolgt,
• – am längsten dauert, wenn eine Fehlerkorrektur (C_EN=1, ECC_EN=1) erfolgt, und
• – langsamer als im erstgenannten Fall, aber schneller als im zweitgenannten Fall erfolgt, wenn "nur" eine Fehlererkennung (C_EN=1, ECC_EN=0) erfolgt.

It should be obvious and requires no further explanation that both the writing of data into the first memory device MEM1 and the reading out of data from the first memory device MEM1

• - can be done most quickly if there is neither error detection nor error correction (C-EN = 0),
• - takes the longest if an error correction (C_EN = 1, ECC_EN = 1) takes place, and
• - Slower than in the former case, but faster than in the latter case if "only" an error detection (C_EN = 1, ECC_EN = 0) takes place.

Consequently, the user of the arrangement can the setting of the control bits C_EN and ECC_EN also influence the maximum working speed of the arrangement or the arrangement containing system. More specifically, for example possible, the clock frequency with which the arrangement or that containing the arrangement System works, and / or the number of wait states depending from the settings of the control bits C_EN and ECC_EN. The setting adapted to the values of the control bits C_EN and ECC_EN the clock frequency, the number of wait states, etc. can be determined by the User, but also automatically through the system containing the arrangement respectively.

After all, the user has it in hand, the system containing the arrangement with a special high working speed, or with particularly high data security, or to operate with a compromise solution in between. It is also possible, adapt the operation of the system to the respective environmental conditions.

The arrangement described can be modified in many ways.

For example, it is possible to use the To interpret the arrangement so that it can only be switched between two operating modes, for example between a first operating mode in which an error detection is carried out and a second mode of operation in which an error correction carried out or between a first operating mode in which neither Error detection still an error correction is carried out and a second operating mode in which an error detection is carried out.

On the other hand, it would also be possible to To interpret the arrangement so that it can be switched between more than three operating modes.

Regardless of the number of operating modes, between which the arrangement can be switched could be provided be that the different operating modes different types of error detection and / or include different types of error correction.

It is also possible to use the multiplexer MUX2 to renounce and instead "only" ensure that the Data stored in the second memory device MEM2 only then be evaluated if it is certain that these are properly generated Data. Proper data for example not before if the arrangement is operated with such a high clock frequency will that no correct parity bits or ECC data can be generated.

It could also be on the multiplexer MUX3 can be dispensed with and instead only ensured that the signal ERR, which is then the output signal of the OR gate OR, not is evaluated if there is no error detection and / or error correction carried out has been.

It could also be provided that the ECC data also those required for error detection Contain parity bits, and that then, if only one fault detection is to be carried out, only that Part of the ECC data containing parity bits is evaluated.

It could also be provided that not all of the data stored in the first memory device MEM1 are treated equally, that is to say, for example, that neither error detection nor error correction is carried out for certain data, error detection for certain other data, and error correction for still other data. The point in time of the changeover of the operating mode can be specified by the user, for example by causing the control bits C_EN and / or ECC_EN to be changed by means of corresponding commands in a program. The different treatment could also be automatic, for example depending on the Address of the data take place within the first memory device MEM1, the user preferably being able to set which addresses or address areas are to be treated and how.

Furthermore, it is possible to to dispense with the second memory device MEM2 if no error detection and no error correction is carried out. This is particularly so of interest if the second storage device is a storage device is that outside of the chip containing the rest of the arrangement is provided.

Regardless of everything, it can prove to be advantageous if when writing data into the first memory device MEM1 information associated with the data is also saved, from which when reading the data from the first Memory device can determine whether for error detection and / or the error correction required Data available stand. Then could the evaluation device EC2 independently decides whether and possibly what type of error detection or error correction should be done.

It is also possible to stop the Operating mode not over carry out a control register, but via fixed wiring, which is no change the operating mode allows more.

Instead of setting the operating mode via a control register could also be provided the mode setting by creating corresponding signals to certain input and / or output connections of the to carry out the arrangement containing the module.

The mode setting could also by burning fuses contained in the device.

The arrangement described proves yourself independently of the details of practical implementation as advantageous. It enables it, the device containing the arrangement for both applications use where a high working speed has the highest priority, as well for applications to use, in which the error detection and / or error correction the highest priority Has.

ANDX

AND gate

C_En

control bit

DE

output by ECCCHK

ECCCHK

ECC data evaluation means

ECC_EN

control bit

ECCTRL

control register

ECCGEN

ECC data generator

EC1

contraption for generating error detection

and or Error correction required data

EC2

contraption for evaluating for error detection

and or Error correction required data

EC3

Error corrector

ERR

error signal

MEM1

first memory device

MEM2

second memory device

muxx

multiplexer

OR

OR gate

PCHK

Parity bit evaluation device

PGEN

Parity bit generator

RBUS1

first read data bus

RBUS2

second read data bus

SE

output by ECCCHK

wBUS

write data

Claims (20)

Device for detecting and / or correcting errors in data read from a memory device, characterized in that the device is configurable. Device according to claim 1, characterized in that the Device is able to carry out an error detection, and that the device is so configurable that it does not detect errors. Device according to claim 1, characterized in that the Device is able to perform an error correction, and that the Device is configurable so that it does not correct errors performs. Device according to claim 1, characterized in that the Device is capable of both error detection as well carry out an error correction, and that the Device is configurable so that it only performs an error detection. Device according to claim 1, characterized in that the device is able to carry out both an error detection and an error correction, and that the device it is configurable that it only carries out an error correction. Device according to claim 1, characterized in that the Device is capable of different types of error detection perform, and that through the configuration is adjustable, what type of error detection perform the device should. Device according to claim 1, characterized in that the Device is capable of various types of error correction perform, and that through the configuration is adjustable, what kind of error correction perform the device should. Device according to claim 1, characterized in that the Device during the operation of the device is reconfigurable. Device according to claim 1, characterized in that the Configuration by setting and / or resetting control register bits he follows. Device according to claim 1, characterized in that the Configuration by applying certain voltages to certain inputs and / or output ports of the device containing the device. Device according to claim 1, characterized in that the Configuration by blowing through fuses. Device according to claim 1, characterized in that the Configuration by means of a corresponding hard wiring of the device he follows. Device according to claim 1, characterized in that the device is configurable by the user of the device. Device according to claim 1, characterized in that itself if necessary, the device can be reconfigured at your own initiative. Device according to claim 14, characterized in that itself the device depends configured from the address at which the data is stored in the storage device are to be saved or are saved, Device according to claim 1, characterized in that the Device for writing data into the storage device also stores information associated with the data from which when reading the data from the memory device can determine whether for error detection and / or the error correction needed Data available stand. Apparatus according to claim 15, characterized in that the Device for writing data into the storage device also stores information associated with the data from which when reading the data from the memory device can determine which Type of data is the data that is used for error detection and / or an error correction is available. Device according to claim 1, characterized in that the Device or the system containing it the working speed of the system adapts to the configuration of the device. Device according to claim 1, characterized in that the Device or the system containing it depending from the configuration of the device the number of wait states established. Device according to claim 1, characterized in that the Device or the system containing it depending sets the clock frequency from the configuration of the device, with which the device or the system containing it works.