DE3442823C2 - - Google Patents

Description

The invention relates to a method and an arrangement for control the transfer of data according to the preamble of claim 1.

Such methods are e.g. B. from computing Surveys, Vol. 14, No. 3, September 1982, pages 473 to 530, especially page 501, left column above or but from IBM Technical Disclosure Bulletin, Vol. 25, No. 11 B, April 1983, pages 6177/6178 for after the known "copy-back" principle working cache memory.

The use of several, each changing one subunit control bits marking within a data block should ensure that the changed Subunits, e.g. B. corresponding to that of a normal Memory command captured data width, usually so Double words instead of the entire data block in the RAM are transferred. That is particularly of Advantage if the data volume per block is very large and hence the amount of data exchanged from the cache to memory can be significantly reduced, especially if the number of subunits changed in relation to the total number of subunits of a block is relatively small.  

On the other hand, the "copy-back" process is required a higher level of security for the data in the cache memory, there is no copy of the changed data in the cache memory the same data is in memory. Data in "copy-back" processing Cache memories are therefore usually replaced by a error correcting code protected - see the first cited reference, page 501, section 6 -, to ensure sufficient functionality.

The effort involved in securing against memory errors depends on this and for the correction to a considerable extent depending on how susceptible to failure the related memory chips, mostly in the form of RAM, and are therefore in addition to single errors, double errors or even triple errors to recognize and correct a sufficient functional reliability of the buffer memory ensure. So z. B. for blocks with A total of 128 additional 32 bytes of eight bits each Check bits for correcting individual errors at the byte level required, which requires 50% more storage, which significantly increases additional sources of error open up and because of the greater connection distances result in longer terms.

Would you now regardless of the point of view, the scope of data transfer between the buffer memory and the main memory to keep it as small as possible, generally in connection with the control bits indicating a change only transfer the subunits where If a change has taken place, control units that have not been changed first strain and the functionality of the data processing system do not interfere as valid copies  of these subunits are present in the working memory anyway are. In particular, would not be correctable and thus errors that lead to the program being terminated in the case of unchanged Subunits remain without effect, so that Availability and thus the performance of the Data processing system would be increased.

On the other hand, the transfer of data units requires a block one by one with individual Control commands significantly more effort than the Transfer of an entire block with only one Control command, especially at time, so the advantage the lower load on the memory transmission path at least in part by reducing performance the data processing system again will be annulled.

It is therefore an object of the invention, starting from the the methods and arrangements mentioned at the outset to design that the average Performance of the data processing system is increased.

This object is achieved according to the invention by the characterizing Features of claim 1 solved.

Based on the formation of the subunits of a data block initially regardless of the transmission width on the transmission line system alone under the Viewpoint that smaller subunits, e.g. B. in the form of bytes, with individual error monitoring options, the likelihood of functional impairment by reducing memory errors and that memory errors can have less of an impact the more limited the area of impact,  especially if only parts of a block are changed is from the point of view that Memory errors mostly occur sporadically in the predominantly the block transfer mechanism maintained so that especially in small blocks with 32 bytes, for example, the transfer to the main memory with the least possible effort and with only a relatively small load on the memory transmission path in a shorter time on average can be executed. Only in the event of an error possibly deviated from the block transfer control and based on the control bits a selection of the transmitting units.

This also increases the probability that incorrect data not changed with uncorrectable Errors are eliminated without doing the same Measure availability due to the lack of a corresponding one Error correction option is restricted. The Fault tolerance increases with only a little additional Change bit overhead.

Overall, this leads to a less effort average increase in performance as a result of the possibility of correction compared to the specified one improved availability and as a result of shorter transmission times on average.

Solution variants for the process flow arise from claims 2 to 5, in particular the training of the invention according to claim 5 with reading and Interim storage of the data block to be saved as Unit and, in the event of a fault, immediate transfer to  a single command control gives the possibility that the cleared buffer memory area immediately again occupied and priority storage cycles for others Storage requests can be inserted.

In addition, another training sees according to the Claims 6 and 7 of the invention that that also incorrect changed data is stored in the working memory can be without a memory error message is triggered by this. A program is canceled then only required if on this incorrect data must be accessed in the working memory. Often but these are only interim results, which is no longer required in the later program flow be, so that unnecessary program cancellations be avoided.

Corresponding arrangements for the implementation of the individual Methods result from claims 8 to 12.

Details of the invention are described below in the embodiment shown in the drawing explained in more detail. In detail shows

Fig. 1 is a block diagram of a cache memory with an extended according to the invention control means,

Fig. 2 is a block diagram of the additional means according to the invention with several embodiments,

Fig. 3 is a flowchart for explaining the operation of the extended control device according to a variant of the invention and

Fig. 4 shows another flow chart for explaining another process variants of the invention.

The block diagram of FIG. 1 shows the essential parts of a cache memory C-SP with the transmission line systems to the main memory ASP and to the processor unit CPU of a data processing system.

The cache memory C-SP is divided into three parts, namely a part AD-SP for the addresses TAG , a part ST-SP for the control bits and a part DAT-SP for the actual data, each of which lies on one line Parts of all three memory parts each form an entry which can be selected with the address AD 1 via the read / write control S / L-ST .

The memory part DAT-SP has, for example, a width of n double words DW 1 to DWn , which together form a block, z. B. each double word DW consists of two single words, each with two bytes of eight data bits each. For example, each byte is secured with a parity bit. The transmission width on the line systems corresponds to z. B. a double word DW , so that for the transmission of a block n double words are to be transmitted one after the other, which are passed through the memory-internal selection control SAW one after the other depending on the setting address AD _DW-E into the correct memory areas and from this with the multiplexer MUX 2 one after another depending the setting address AD _DW-A . The further multiplexer MUX-E is used in a manner known per se to select the data transmission paths for input by the processor unit CPU or by the working memory ASP .

Each of the assumed four bytes of a double word in the memory section DAT-SP , which form the subunits to be monitored, is a control bit W in the memory section ST-SP . . . assigned, which indicates a change in the associated byte when set. For blocks of eight double words each corresponding to 32 bytes, this is a total of 32 bits, namely W 1 to W 32 . In addition, at least one validity bit V , which indicates the validity of the associated entry, and a security symbol SI are provided in the usual manner for securing the control bit information. Likewise, the addresses TAG in the memory section AD-SP are secured by a security symbol SI .

On the formation of the security signs and the derivation of the control bits as well as the general mode of operation of the memory controller SP-ST in connection with the device H / M for checking whether a desired entry is present and with the test device PPE for monitoring the reads selected by the multiplexer MUX 2 Data units on freedom from errors are not discussed in more detail in this context, since this is not important for understanding the invention. Details on this are e.g. B. known from the aforementioned article from Computing Surveys with the references given therein.

However, what is new according to the invention is the addition of the memory controller SP-ST to the additional control device W-ST , which controls bits W 1 to W 32 read from the memory section ST-SP in connection with the error signals supplied by the test device PPE for the individual bytes evaluates the data units DW 1 to DWn read from the memory part DAT-SP and, depending on this, controls the transmission of the individual data units of an entry in the cache memory C-SP when it is swapped out into the main memory ASP .

Details of this control device W-ST in cooperation with the general memory controller SP-ST are shown in FIG. 2.

The control bit lines for the control bits W 1 to W 32 of a read entry in the upper left part of the figure are combined according to the four bytes for each data unit DW in groups G 1 to G 8 and are represented by the OR elements OR 1 and the subsequent OR Link OR 2 monitored for the presence of a change in the associated data bytes. If none of the bits W 1 to W 32 is set and there is consequently no change, then if the associated entry in the cache memory C-SP is to be cleared, no swapping out into the working memory ASP is necessary. It is sufficient if the associated validity bit V in the memory section ST-SP is set to zero with the signal S.INV and then the new data are transferred from the working memory to the associated entry.

If, on the other hand, one of the bits W 1 to W 32 is set, the data of the entry must first be swapped out into the working memory ASP , which is identified by the signal SWAP and thus leads to the initiation of a block transmission cycle. For this purpose, a counter CNT-A , controlled by clock pulses T , supplies one after the other and in coordination with the transmission cycle for each data unit DW in a manner known per se. . . the setting address AD _DW-A for the multiplexer MUX 2 . At the same time, this setting address controls a further multiplexer MUX within the control device W-ST , each of which simultaneously to the selected data units DW . . . of a block the associated control bit group G. . . selected and switched through to the output. With the four control bits selected in each case, e.g. B. W 1 to W 4 , which are simultaneously from the associated data unit, for. B. DW 1 , checking test device PPE supplied error signals PERR 0 to 3 linked.

This link can be carried out in different ways according to the possible different solution variants. The basic equipment includes the AND gates U 01 to U 31 , the AND gates U 02 to U 32 and the OR gate OR 3 .

The AND gates U 01 to U 31 each monitor whether an error-free changed data byte is present as a subunit and deliver the control signal BYTE.SEL . . ., which enables the corresponding data byte to be written into the working memory with signal "1" and prevents the transfer to the working memory with signal "0". The AND gates U 02 to U 32 monitor the presence of a modified, defective subunit, which leads through the OR gate OR 3 to the error signal (W PERR) , which can then influence the further control process in different ways, which will be explained in more detail later is explained.

In the simplest solution variant , the additional OR gate OR 4 drawn in dashed lines to the right of the multiplexer MUX is required, which monitors the error signals PERR 0 to 3 , whether an error has been reported, and with PERR _DW a blocking signal W.INH for the rest of an ongoing block cycle triggers e.g. B. by setting the flip-flop KS , which is reset at the end of the cycle.

The blocking signal W.INH is forwarded to the main memory ASP in a manner known per se and prevents the takeover of the data units delivered simultaneously for the rest of the current block cycle.

The derivation of the locking signal W.INH can also be made dependent on the fact that the error does not affect a changed byte. For this purpose, the output of the OR gate OR 4 is linked to the inverted output of the OR gate OR 3 by the AND gate U 1 , the output of which is then connected to the set input S of the multivibrator KS . This is particularly advantageous if, in the event of incorrectly changed subunits of the data block, an early transfer to an error handling routine FBR with an abort of the current block cycle is to be carried out.

As long as no error PERR . . . is displayed, the blocking signals BYTE.SEL . . . = 0 normally not activated, so that all subunits, whether changed or not changed, are transferred to the main memory ASP until an error is detected. The blocking suppression is not shown. It could be effected in a simple manner by applying a constant signal "1" to all blocking signal lines.

A PERR error now occurs during a running block cycle . . . then, in the one solution variant, the block cycle initially continues until the end. However, since the locking signal W.INH is switched on, no more data units are transferred to the working memory from the faulty data unit. At the end of the expiring block cycle, which is recognized by the signal BE , of the counter CNT-A , the system switches over to individual command control, and only the data units DW affected by changed subunits become. . . transferred to the working memory. All affected data units of the block, including those already transferred, are transferred.

This is controlled by a PRIO priority network, which is connected to the outputs of the OR gates OR 1 and is shown in broken lines, since it is not necessary with other solution variants.

This priority network PRIO , controlled by pulses at input f, determines groups G in a cyclical sequence. . . of control bits W. . ., which indicate a change. The determined group addresses are successively transferred to the counter CNT-A for adjustment by corresponding control pulses at the input ü , so that the multiplexer MUX switches through the selected group and at the same time the multiplexer MUX 2 selects the associated data unit. During the single command control , a possibly occurring locking signal W.INH has no effect. Rather, the control signals BYTE.SEL . . . the transfer to the working memory is controlled, whereby defective, unchanged subunits are disregarded and defective, modified subunits for the error signal (W PERR) at the output of the OR gate OR 3 and thus, as already explained, possibly for terminating the transmission with transfer to an error handling routine FBR to lead.

In a further variant, the current block transmission cycle is aborted when an error occurs and without delay in a single command control in connection with the BYTE.SEL control signals. . . transferred. As with the variant explained above, all changed subunits, including those that have already been transmitted, can be transmitted.

Due to the immediate termination of the block cycle but also the possibility of transferring with the data units not transmitted to continue.

In this case, the counter CNT-A with its address marking supplies the starting point for the priority network PRIO , the address marking being adopted with the signal ü . The changeover is then carried out again with signal f in accordance with the individual transmission cycles, until signal en indicates that all changed subunits have been outsourced.

However, as already mentioned, the PRIO priority network can be dispensed with if you generally only provide one block cycle and the BYTE.SEL . . . can take effect from the start. Then only the changed subunits are recorded. However, the prerequisite is that no locking signal W.INH is then generated.

This solution variant costs the least time and effort when incorrectly changed data is also swapped out to the ASP memory. In this case, the error signal (W PERR) leads to a signal SPERR used several times. On the one hand, in conjunction with the additional AND gates U 03 to U 33 and the OR gates OR 01 to OR 31, it ensures that the faulty changed bytes for the transfer by the working memory with the generation of the BYTE.SEL signals. . . = 1 are marked, and on the other hand it causes the working memory ASP to accept the defective bytes in spite of the error found during its own error check and to mark them as invalid, e.g. B. saved by an incorrect security symbol without reporting a memory error. Faulty, modified subunits can only have an effect if these subunits have to be accessed again in the further course of the program.

Fig. 3 and Fig. 4 show respective flow diagrams for the individual process variants described. Fig. 3 of an error whose sequence is shown in the lower right part, while the left part of the flowchart refers to the initially introduced in any case, block cycle bezeiht thereby to the variants with block cycle control, and subsequent transition to a single command control upon occurrence.

The transfer to the individual command control takes place only in the event of an error, either at the end of a block cycle if the blocking signal W.INH is set or immediately, as indicated by the dash-dotted connecting line, after an error occurs with the block cycle initiated being aborted. The outsourcing of data units with individual command control either begins, as shown, with the first changed data unit for which W _DW = 1, or, as already explained, with the data unit leading to the termination of the block cycle on the basis of the counter position taken by the counter CNT-A to determine the starting point for the PRIO priority network.

Errors that occur in the case of changed subunits lead, as indicated by dashed lines, either to an abort with a transfer to an error handling routine FBR or, if the type of program makes it seem sensible, to a swap to the main memory with the corresponding accompanying signal SPERR .

The flow chart of FIG. 4 relates to the method variant with a block cycle running once, the byte selection signals BYTE.SEL . . . are effective from the outset, so that in each of the successive write cycles only the changed bytes are written into the main memory.

In the variants described so far, the cache memory C-SP is blocked until the swapping of a block is complete, since the individual data units are transferred directly from the cache memory without intermediate storage. However, one could additionally provide a buffer for the entire entry and first check the security characters of all data units in order to decide depending on whether the swapping should take place as part of a block cycle or immediately by means of individual command control. During the test period and also during the individual command control, the entire entry area in the cache memory could already be occupied again or other memory requests could be taken into account without further notice.

The backup of the data is in the described embodiment with a single parity bit per byte been carried out, which is no correction in the event of an error allows. Nevertheless, not every mistake affects the Availability as a result of the chosen size of the subunits the risk is reduced that errors in unchanged data units refer to changed data units can impact. Despite the lack of possibility The functionality can thus be corrected  due to the greater fault tolerance increase.

If the memory error probability is greater with the Need to correct z. B. of individual errors applies The same for non-correctable double errors.

The implementation of the method is not bound to circuit parts in hard-wired logic in accordance with the exemplary embodiment in FIG. 2. The individual process steps are easily from a programmable logic controller, z. B. a microprocessor, executable.

Of course, instead of the bytes selected as subunits, two or even four bytes can each form a subunit to which a control bit W is assigned. The size of the subunits to be selected depends primarily on the type of data and the frequency with which it is changed, as well as on the level of security aimed at for a given probability of error in the memory modules used; it can be determined by appropriate simulation.

Claims (12)

1.Procedure for controlling the transfer of data stored in buffer memories, in particular cache memories, from data processing systems into the main memory, data in the main memory stored in the form of blocks only being changed in the buffer memory and changed data being transferred to the main memory only when the The associated memory area is required for a block in the buffer memory for other data, the blocks of the data consist of independent subunits and are assigned to each subunit in control bits which indicate the change in the respective subunit, and at least the transfer of the data from the working memory to the buffer memory in each case It is possible to frame an entire block by means of a single control command and, in the opposite direction, also in the context of individual subunits with individual control commands depending on the control bits, data units corresponding to the width of the transmission line system n are transmitted one after the other,
characterized in that when a data block with at least one modified sub-unit is swapped out of the buffer memory (C-SP) into the main memory (ASP) , whereby regardless of the size of the respective data block and the size of the data units (e.g. Double words DW, each with four bytes) are subdivided into subunits (e.g. in the form of bytes) with individual error monitoring options, to which an individual control bit (e.g. W 1 ) for marking a change is assigned Flawlessness of all sub-units of the block, the transmission takes place within the entire block with only one control command and that if there are at least one defective sub-unit within the block to be swapped out, the control bits (e.g. W 1 to W 32 ) are used to control the transmission of the data units changed subunits and unchanged defective subunits from the exercise in memory (ASP) can be excluded. 2. The method according to claim 1, characterized in that each swapping of a data block is initiated with a block transfer cycle, that with the first faulty data unit read from the buffer memory within the block transfer cycle (for example DW 5 ), the takeover of these and all in the block transfer cycle Subsequent data units (e.g. DW 6 to DW 8 ) are blocked by an accompanying signal (W.INH) and that at least all data units that have not yet been adopted and have changed subunits are subsequently transmitted with individual command control, subunits to be excluded from the memory transfer, if necessary, within one Data unit can be marked by separate control signals (BYTRE.SEL.... = 0). 3. The method according to claim 2, characterized in that the reading of a faulty data unit (z. B. DW 5 ), the current block transmission cycle is immediately interrupted and switched to single command control, only the data units not yet transferred in the block cycle are taken into account. 4. The method according to claim 1, characterized in that each swapping of a data block is carried out in the context of a block transmission cycle and that all unchanged subunits of the individual data units are marked by separate control signals (e.g. BYTE.SEL 1 = 0) during the ongoing block transmission cycle that prevent takeover by the main memory (ASP) . 5. The method according to claim 2 or 4, characterized in that at the beginning of each swap of a data block, the associated block is first read as a whole from the buffer memory (C-SP) and buffered for error checking (with PEE) and that a block transfer cycle is ignored the control signals marking the unchanged subunits (e.g. BYTE.SEL 1 = 0) are only initiated if all subunits of the data block are error-free. 6. The method according to any one of claims 1 to 5, characterized in that also recognized as incorrect and marked as modified subunits in the working memory (ASP) and marked in this as invalid and that the memory error message normally triggered by the working memory (ASP) is suppressed. 7. The method according to claim 6, characterized in that the transfer of defective data units into the main memory (ASP) and the suppression of the memory error message is controlled by a separate accompanying signal (SPERR) . 8. Arrangement for performing the method according to one of claims 1 to 7, consisting of a working memory (ASP) upstream of a data processing system, working according to the "copy-back" method cache memory (C-SP) , from devices (z PPE) for securing and / or correcting the data stored in the cache memory (C-SP) in the form of blocks against memory errors and from a transmission line system with controller for exchanging data units forming the data blocks (e.g. DW 1 to DWn) between the main memory (ASP) and the cache memory (C-SP) either on the basis of a single control command as part of a block cycle or on the basis of individual control commands for the individual data units (e.g. DW 1 ), characterized by a separate control device ( W-ST) for monitoring both the control bits assigned to the individual subunits of a data unit for the purpose of identifying a change that has occurred (for example W 1 to W 32 ) and also that of the safety devices (PPE) delivered error signals (z. PERR 0 to 3 ) and for generating control signals (e.g. SWAP or S.INH or BYTE.SEL... ) Depending on the monitored control bits (W ... ) And the error signals (PERR... ) to control the swapping of a marked data block (with SWAP) into the main memory (ASP) and to block the transfer of subunits of the data block to be swapped out (e.g. with W.INH or BYTE.SEL... = 0). 9. Arrangement according to claim 8, characterized by devices (OR 1 and OR 2 ) for determining that subunits of the data block to be outsourced are changed, and for generating corresponding control signals (z. B. S.INV and SWAP) , by devices (MUX) for Selection of the group (e.g. G 1 ) of control bits (e.g. W 1 to W 4 ) and belonging to the data unit (e.g. DW 1 ) read and selected from the cache memory (C-SP) by means (U 01 to U 31 ) for determining error-free changed sub-units and for generating the accompanying signals (BYTE.SEL... = 1) that control the transfer by the main memory (ASP ). 10. The arrangement according to claim 9, characterized by means (OR 4 ) for checking the respective error signals (PERR 0 to 3 ) for the presence of an error and for generating a blocking signal (W.INH) to prevent the transfer of simultaneously transmitted data units in the RAM (ASP) . 11. Arrangement according to claim 9 or 10 characterized by means (PRI 0 , CNT-A) for determining the data units of a block affected by a change depending on the individual control bit groups (z. B. G 1 to G 8 ) of the control bits (W 1 to W 32 ) in a gap-free sequence and for the appropriate setting of the selection devices (MUX, MUX 2 ) for the provision of the associated control bit group (e.g. G 1 ) and the associated data unit (e.g. DW 1 ) for controlling the Transmission. 12. Arrangement according to one of claims 9 to 11, marked by devices (U 02 to U 32 , OR 3 ) for deriving an accompanying signal (SPERR) in the presence of faulty modified subunits to force the takeover of the associated data unit by the working memory (ASP) and by means (U 03 to U 33 , OR 01 to OR 31 ) for modifying the individual accompanying signals preventing the takeover (BYTE.SEL.... = 0) for accompanying signals enabling the subunits into the takeover (BYTE.SEL... = 1 ) when the global accompanying signal (SPERR) occurs to force the takeover of a faulty data unit by the working memory.