WO2006126756A1 - Puce de dispositif passif integre et procede de fabrication correspondant - Google Patents

Puce de dispositif passif integre et procede de fabrication correspondant Download PDF

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Publication number
WO2006126756A1
WO2006126756A1 PCT/KR2005/002507 KR2005002507W WO2006126756A1 WO 2006126756 A1 WO2006126756 A1 WO 2006126756A1 KR 2005002507 W KR2005002507 W KR 2005002507W WO 2006126756 A1 WO2006126756 A1 WO 2006126756A1
Authority
WO
WIPO (PCT)
Prior art keywords
passive device
substrate
device chip
integrated
conductive layer
Prior art date
Application number
PCT/KR2005/002507
Other languages
English (en)
Inventor
Young-Se Kwon
Chae-Hyun Wang
Myoung-Jun Cho
Original Assignee
Telephus Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telephus Inc. filed Critical Telephus Inc.
Publication of WO2006126756A1 publication Critical patent/WO2006126756A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
    • H01L27/016—Thin-film circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5228—Resistive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Definitions

  • the present invention relates to an integrated passive device chip and a method of manufacturing the same and, more particularly, to an inexpensive ceramic integrated passive device chip constructed by forming a thin film layer on an inexpensive alumina ceramic substrate having a good substrate-characteristic and directly forming a passive device with a semiconductor production process to increase integration degree and easily construct circuit and a method of manufacturing the same.
  • Background Art
  • the passive devices are important elements for all electronic products.
  • the passive devices include a resistor, a capacitor, an inductor, a filter, a transformer, and the like.
  • PCB printed circuit board
  • passive devices occupies about 80% in weight of circuits of the electronic apparatus. Therefore, the integration of the passive devices greatly influences prices, sizes, and reliabilities of the electronic apparatuses.
  • an integrated passive device is constructed by oxidizing some portion of a silicon (Si) substrate to form a silicon oxide (SiO ) layer and integrating a passive device on the silicon oxide layer.
  • the silicon oxide layer (an oxide layer) is thin (about 10 D)
  • the silicon oxide layer must be formed to have a thickness of about 25 D. In order to obtain a sufficient thickness of the oxide layer, too much produces time is taken, so that cost increases.
  • the present invention is contrived to solve the above-mentioned problems, and an object of the present invention is to provide an integrated passive device chip capable of conveniently performing a mounting process by forming a thin film layer on an alumina ceramic substrate, directly forming passive devices using a semiconductor process to increase integration degree, and implementing electrical connection using via holes.
  • Another object of the present invention is to provide an integrated passive device chip capable of easily implementing mass production by forming via holes with cut grooves and conductive layers formed thereon in an initial substrate made of an alumina ceramic and forming passive devices.
  • an integrated passive device chip comprising: a substrate made of an alumina ceramic with a plurality of via holes formed thereon in a predetermined pattern; a conductive layer made of a conductive material coated on inner portions and upper and lower surfaces of the via holes formed on the substrate; and a passive device formed on one surface of the substrate and connected to the conductive layer.
  • the integrated passive device chip may further comprise thin film layer formed by coating a dielectric material to increase an adhesive force and flatness between the substrate and the passive device.
  • a method of manufacturing an integrated passive device chip comprising steps of: forming an initial substrate with an alumina ceramic, wherein a plurality of via holes are formed in a predetermine pattern; forming a conductive layer by coating a conductive material on an inner portion and upper and lower surfaces of each via hole or each via groove of the initial substrate; forming a thin film layer by coating a dielectric material on one surface of the initial substrate to improve an adhesive force and flatness of passive devices; forming the passive devices to be connected to the conductive layer in a predetermined pattern on each region by arraying the passive devices in a predetermined interval on the initial substrate; and performing a mechanical cutting process to divide chips where the passive devices are integrated.
  • FlG. 1 is a perspective view showing an integrated passive device chip according to a first embodiment of the present invention
  • FlG. 2 is a cross sectional view taken along line A-A;
  • FlG. 3 is a cross sectional view showing an integrated passive device chip according to a second embodiment of the present invention (corresponding to FlG. 2);
  • FlG. 4 is a cross sectional view showing an integrated passive device chip according to a third embodiment of the present invention (corresponding to FlG. 2);
  • FlG. 5 is a perspective view showing an integrated passive device chip according to a fourth embodiment of the present invention;
  • FlG. 6 is a perspective view showing an integrated passive device chip according to a fifth embodiment of the present invention;
  • [19] FlG. 6 is a perspective view showing an integrated passive device chip according to a sixth embodiment of the present invention; [20] FlG.
  • FIG. 8 is a process view showing a method of manufacturing an integrated passive device chip according to an embodiment of the present invention.
  • FlG. 9 is a perspective view showing an initial substrate for explaining a formation state of a via groove in a method of manufacturing an integrated passive device chip according to an embodiment of the present invention.
  • an integrated passive device chip according to a first embodiment comprises: a substrate 10 made of an alumina ceramic with a plurality of via holes 12 formed thereon in a predetermined pattern; a conductive layer
  • the passive device 20 is constructed by arraying a resistor, a capacitor, an inductor, a filter, a transformer, and a combination thereof in serial and/or in parallel.
  • the passive device 20 may be formed to have a function of a bandpass filter (BPF), a diplexer, a duplexer, a coupler, a phase shifter, or a balun.
  • BPF bandpass filter
  • the passive device 20 includes circuits and lines constructed to performing the aforementioned functions.
  • the passive device 20 can be formed by using a lithography process or the like, which is widely used in semiconductor production process.
  • the substrate 10 is made of alumina (Al 0 ) ceramic and formed by using a powder molding process, a sintering process, a firing process, and the like.
  • the substrate is made of the alumina ceramic, the material cost greatly decrease in comparison to a case of using a silicon (Si) substrate or a gallium arsenide (GaAs) substrate.
  • via holes 12 are simultaneously formed in the substrate 10.
  • the conductive layer 30 is formed on the inner surfaces and upper and lower surfaces of the via holes 12 by using a conductive material such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), and tungsten (W).
  • a conductive material such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), and tungsten (W).
  • the passive device 20 can be easily electrically connected to a printed circuit substrate through the conductive layer 30 by simply assembling and mounting the passive device 20 on the printed circuit substrate. The assembling and mounting processes can be conveniently and simply performed.
  • an insulating layer 50 may be formed by coating a low dielectric material on the passive device 20 with a larger area than that of the passive device 20 in order to insulate and protect the passive device 20.
  • the insulating layer 50 is formed by using polyimide, benzocyclobutene (BCB), or the like.
  • the insulating layer 50 may be constructed with a single layer or two or more layers.
  • the insulating layer 50 has a function of protecting the passive device 20 as well as a function of insulating the passive device 20.
  • a thin film layer 40 is further formed by coating a dielectric material in order to increase an adhesive force and flatness between the substrate 10 and the passive device 20.
  • the thin film layer 40 is formed with a thickness of several tens D or less.
  • the thin film layer 40 is too thick, too much time is taken to form the thin film layer 40 by using a deposition process, a spin coating process, or the like. Therefore, it is preferable that the thin film layer 40 is formed with less than a thickness which can be easily formed by using the deposition process, the spin coating process, or the like.
  • the thin film layer 40 is formed by using as high dielectric material such as polyimide, BCB, SiO , Si N , and SiO in order to obtain electrical insulation.
  • the substrate 10 is made of the alumina ceramic
  • a surface roughness of the substrate 10 greatly increases. Therefore, in a case where the passive 20 is directly formed thereon, it is difficult to manufacture the passive device 20, or there may be decrease in the adhesive force.
  • the flatness surface roughness
  • the flatness can be improved, so that it is possible to easily manufacture the passive device and increase the adhesive.
  • the second embodiment has the same construction as that of the first embodiment, and thus, description thereon will be omitted.
  • a conductive layer 33 is formed by coating a conductive material on the upper and lower surfaces on the via hole 12 for connection to circuits.
  • the conductive layer 31 may be integrally formed by filling a paste conductive material in the via hole using a screen printing process or the like, and then, by performing a simultaneous sintering process when the substrate 10 made of the alumina ceramic is subject to the sintering process.
  • the conductive layer 31 may be formed by filling the conductive material in the via hole 12 using a plating process.
  • the third embodiment has the same construction as those of the first and second embodiments, and thus, description thereon will be omitted.
  • connection port 38 electrically connected to the passive device 20 is partially formed, and an active device (external active device) such as an IC chip 60 or other passive devices (external passive devices) manufactured as a chip or a module are mounted on the connection port 38.
  • an active device such as an IC chip 60 or other passive devices (external passive devices) manufactured as a chip or a module are mounted on the connection port 38.
  • these components are integrally constructed.
  • the active device (external active device) or other passive devices (external passive devices) may be connected to the connection port 38 by using a flip chip bonding process or a wire bonding process.
  • connection port 38 may be formed on the substrate 10 or the thin film layer 40.
  • connection port 38 is electrically connected to the passive device 20 with lines integrally formed, so that the external active device or the passive device formed on the connection port 38 can be electrically connected to the passive device 20 formed on the substrate 10 to perform a predetermined function.
  • connection port 38 is formed together with the passive device 20.
  • the integrated passive device chip according to the present invention can be applied to a substrate used to manufacture a module, and various functions can be implemented.
  • the present invention may be constructed by only the passive devices or by combination of the active devices, a specific purpose chip performing a specific function can be freely designed and implemented if necessary.
  • the fourth embodiment has the same construction as those of the first to third embodiments, and thus, description thereon will be omitted.
  • the via hole 12 instead of the via hole 12, one or more via grooves 13 are formed on both side surfaces.
  • the conductive layer 30 is also formed to used for electrical connection of circuits.
  • a plurality of via holes 12 and via grooves 13 are formed, and conductive layers 30 are formed on the via holes 12 and the via grooves 13.
  • an initial substrate 2 is made of an alumina ceramic. In the initial substrate
  • cut grooves 4 are formed in a predetermined interval in the horizontal and vertical directions, and a plurality of via holes 12 are formed in regions partitioned by the cut grooves 4 (PlO).
  • cut holes 6 are formed at intersections of horizontal and vertical grooves 4 on the initial substrate 2 in order to easily divide chips.
  • the cut holes 6 has a shape of an approximate rectangle in order to easily perfume a chamfering process, so that it is possible to preventing the divided chip from having sharp edges.
  • the via holes 12 are formed on the cut grooves 4 as shown in FlG. 9.
  • the conductive layer 30 is formed by coating a conductive material on an inner portion and upper and lower surfaces of each via hole 12 in the initial substrate 2 (P20).
  • the conductive material used to form the conductive layer 30 is a metal having a good conductivity such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), and tungsten (W).
  • a thin film layer 40 is formed by coating a dielectric material such as polyimide and BCB on one surface of the initial substrate 2 where the passive device 20 is to be formed in order to increase the adhesive force and flatness of the passive device 20 (P30).
  • the thin film layer 40 is formed with a thickness of several tens D or less by using a deposition process or a spin coating process.
  • the thin film layer 40 is formed.
  • the present invention is not limited thereto.
  • the conductive layer 30 may be formed.
  • the thin film layer 40 may not be formed. In this case, as shown in FlG. 2, the passive device 20 is directly formed on the substrate 10.
  • the passive device 20 is formed to be connected to the conductive layer 30 in a predetermined pattern on regions partitioned by the cut grooves 4 of the initial substrate 2 (P40).
  • the passive device 20 may be constructed in a pattern formed by arraying a resistor, a capacitor, an inductor, a transmission line, and the like in serial or in parallel.
  • the passive device 20 may be a bandpass filter (BPF), a diplexer, a duplexer, a coupler, a phase shifter, or a balun constructed by arraying a resistor, a capacitor, an inductor, a transmission line, and the like in serial and/or in parallel.
  • BPF bandpass filter
  • connection ports 38 may be formed to mount and connect active devices or other passive devices.
  • the initial substrate 2 is cut along the cut grooves 4 to divide chips where the passive devices 20 are integrated, so that the integrated passive device chip according to the present invention is completed.
  • the initial substrate 2 can be easily cut by exerting a slight moment to the cut grooves 4 to divide the chips.
  • a large number of the integrated passive device chips can be simultaneously manufactured.
  • a process for forming an insulating layer 50 may be added to protect the passive device 20.
  • the cutting process may be performed after the insulating layer 50 is formed.
  • the insulating layer 50 may be formed.
  • the cut grooves 4 and the cut holes 6 are formed on the initial substrate 2 in order to easily cut the initial substrate 2.
  • the present invention is not limited thereto.
  • the cut grooves 4 and the cut holes 6 are not formed, and after the passive device 20 and the insulating layer 50 are formed, a mechanical dicing process may be performed.
  • an integrated passive device chip may be manufactured by: forming an initial substrate 2 made of an alumina ceramic, where a plurality of via holes 12 are formed in a predetermined pattern; forming a conductive layer 30 by coating a conductive material on an inner portion and upper and lower surfaces of each via hole 12; forming a thin film layer by coating a dielectric material such as polyimide and BCD on one surface of the initial substrate 2 (where the passive devices 20 are to be formed) in order to improve an adhesive force and flatness of the passive devices 20; by arraying the passive devices 20 in a predetermined interval to be connected to the conductive layer 30 in a predetermined pattern in each region; forming an insulating layer 50 to protect and insulate the passive devices 20; and performing a mechanical cutting process to divide chips where the passive devices 20 are integrated.
  • alumina substrate is relatively inexpensive and has good applicability and substrate-characteristics in comparison to a silicon substrate and a gallium arsenide substrate, it is possible to obtain a low-cost competitive product.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

La présente invention concerne une puce de dispositif passif intégré. Ladite puce comprend : un substrat constitué d'une céramique d'alumine perforée d'une pluralité de trous de raccordement disposés selon un motif prédéfini ; une couche conductrice formée par un matériau conducteur revêtant les parties internes et les surfaces supérieures et inférieures des trous de raccordement du substrat ; un dispositif passif formé sur l'une des surfaces du substrat et relié à la couche conductrice ; une couche mince créée par le revêtement d'un matériau diélectrique, visant à accroître l'adhérence et la planéité entre le substrat et le dispositif passif. En conséquence, la présente invention permet de produire en série des puces de dispositif passif intégré et en facilite le processus d'assemblage.
PCT/KR2005/002507 2005-05-26 2005-08-01 Puce de dispositif passif integre et procede de fabrication correspondant WO2006126756A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020050044376A KR100772460B1 (ko) 2005-05-26 2005-05-26 집적 수동소자 칩 및 그 제조방법
KR10-2005-0044376 2005-05-26

Publications (1)

Publication Number Publication Date
WO2006126756A1 true WO2006126756A1 (fr) 2006-11-30

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PCT/KR2005/002507 WO2006126756A1 (fr) 2005-05-26 2005-08-01 Puce de dispositif passif integre et procede de fabrication correspondant

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WO (1) WO2006126756A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009052683A1 (fr) * 2007-10-25 2009-04-30 Hong Kong Applied Science And Technology Research Institute Co., Ltd. Boîtier de circuit électronique

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980014335A (ko) * 1996-08-09 1998-05-25 윤덕용 산화막 다공성 실리콘 기판을 이용한 초고주파 소자
US5796165A (en) * 1996-03-19 1998-08-18 Matsushita Electronics Corporation High-frequency integrated circuit device having a multilayer structure
KR20010036731A (ko) * 1999-10-11 2001-05-07 구자홍 마이크로 수동소자의 제조 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5796165A (en) * 1996-03-19 1998-08-18 Matsushita Electronics Corporation High-frequency integrated circuit device having a multilayer structure
KR19980014335A (ko) * 1996-08-09 1998-05-25 윤덕용 산화막 다공성 실리콘 기판을 이용한 초고주파 소자
KR20010036731A (ko) * 1999-10-11 2001-05-07 구자홍 마이크로 수동소자의 제조 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009052683A1 (fr) * 2007-10-25 2009-04-30 Hong Kong Applied Science And Technology Research Institute Co., Ltd. Boîtier de circuit électronique

Also Published As

Publication number Publication date
KR20060124834A (ko) 2006-12-06
KR100772460B1 (ko) 2007-11-01

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