WO2006124182A1 - Method for fabricating soi device - Google Patents

Method for fabricating soi device Download PDF

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Publication number
WO2006124182A1
WO2006124182A1 PCT/US2006/014626 US2006014626W WO2006124182A1 WO 2006124182 A1 WO2006124182 A1 WO 2006124182A1 US 2006014626 W US2006014626 W US 2006014626W WO 2006124182 A1 WO2006124182 A1 WO 2006124182A1
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WIPO (PCT)
Prior art keywords
monocrystalline silicon
gate electrode
layer
silicon layer
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PCT/US2006/014626
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French (fr)
Inventor
Mario M. Pelella
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Priority to DE112006001169T priority Critical patent/DE112006001169B4/en
Priority to GB0721841A priority patent/GB2440861B/en
Priority to JP2008511132A priority patent/JP5079687B2/en
Priority to KR1020077028975A priority patent/KR101201489B1/en
Publication of WO2006124182A1 publication Critical patent/WO2006124182A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/01—Manufacture or treatment
    • H10D8/043—Manufacture or treatment of planar diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/411—PN diodes having planar bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D87/00—Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326—Aspects related to lithography, isolation or planarisation of the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors

Definitions

  • the present invention generally relates to a method for fabricating semiconductor on insulator (SOI) devices, and more particularly relates to a method for fabricating SOI integrated circuits having devices in both the thin SOI layer and the substrate.
  • SOI semiconductor on insulator
  • FETs field effect transistors
  • MOSFETs metal oxide semiconductor field effect transistors
  • CMOS circuit complementary MOS or CMOS circuit.
  • Certain improvements in performance of FET ICs can be realized by forming the FETs in a thin layer of semiconductor material overlying an insulator layer.
  • SOI FETs semiconductor on insulator
  • Such semiconductor on insulator (SOI) FETs exhibit lower junction capacitance and hence can operate at higher speeds. It is advantageous in certain applications, however, to fabricate at least some devices in the semiconductor substrate that supports the insulator layer.
  • the devices formed in the substrate may have better thermal properties and can support higher voltages than devices formed in the thin semiconductor layer.
  • MOS transistors As the complexity of the integrated circuits increases, more and more MOS transistors are needed to implement the integrated circuit function. As more and more transistors are designed into the IC, it becomes important to shrink the size of individual MOS transistors so that the size of the IC remains reasonable and the IC can be reliably manufactured. Shrinking the size of an MOS transistor implies that the minimum feature size, that is, the minimum width of a line or the minimum spacing between lines, is reduced. MOS transistors have now been aggressively reduced to the point at which the gate electrode of the transistor is less than or equal to 45 nanometers ( ⁇ m) in width. Methods previously used to fabricate devices in the substrate of an SOI structure, however, have not be able to achieve the same minimum feature size in substrate devices as are realized in the devices formed in the thin semiconductor layer.
  • a method for fabricating a semiconductor on insulator (SOI) device includes, in one embodiment, providing a monocrystalline silicon substrate having a monocrystalline silicon layer overlying the substrate and separated therefrom by a dielectric layer.
  • a gate electrode material is deposited and patterned to form a gate electrode and a spacer.
  • Impurity determining dopant ions are implanted into the monocrystatline silicon layer using the gate electrode as an ion implant mask to form spaced apart source and drain regions in the monocrystalline silicon layer and into the monocrystalline silicon substrate using the spacer as an ion implant mask to form spaced apart device regions in the monocrystalline substrate. Electrical contacts are then formed that contact the spaced apart device regions.
  • FIG. 1-11 schematically illustrate, in cross section, process steps in accordance with various embodiments of the invention
  • FIG. 12 illustrates, in cross section, a prior art substrate diode
  • FIG. 13 schematically illustrates, in cross section, a substrate diode in accordance with an embodiment of the invention.
  • FIGS. 1-11 schematically illustrate method steps for the manufacture of a CMOS integrated circuit 20 in accordance with various embodiments of the invention.
  • MOS device properly refers to a device having a metal gate electrode and an oxide gate insulator, that term will be used throughout to refer to any semiconductor device that includes a conductive gate electrode (whether metal or other conductive material) that is positioned over a gate insulator (whether oxide or other insulator) which, in turn, is positioned over a semiconductor substrate.
  • CMOS integrated circuit 20 only a small portion of CMOS integrated circuit 20 is illustrated.
  • integrated circuit 20 is a CMOS circuit
  • the invention is also applicable to the fabrication of a single channel type MOS circuit.
  • the method in accordance with one embodiment of the invention begins with providing a semiconductor substrate 21.
  • the semiconductor substrate is preferably a silicon substrate with a monocrystalline silicon layer 22 formed overlying a monocrystalline silicon carrier substrate 24.
  • the terms "silicon layer” and “silicon substrate” will be used to encompass the relatively pure monocrystalline silicon materials typically used hi the semiconductor industry as well as silicon admixed with other elements such as germanium, carbon, and the like to form substantially monocrystalline semiconductor material.
  • Monocrystalline silicon layer 22 will be used in the formation of N-channel and P-channel MOS transistors.
  • Monocrystalline silicon substrate 24 will be used for the formation of a substrate device herein illustrated as a PN junction diode.
  • Monocrystalline silicon layer 22 can be formed, for example, by the well known layer transfer technique. In that technique hydrogen is implanted into a subsurface region of an oxidized monocrystalline silicon wafer. The implanted wafer is then flip bonded to monocrystalline silicon substrate 24. A two phase heat treatment is then carried out to split the hydrogen implanted wafer along the implanted region and to strengthen the bonding, leaving a thin monocrystalline silicon layer 22 bonded to the monocrystalline silicon substrate and separated from the substrate by a dielectric insulating layer 26. The monocrystalline silicon layer is then thinned and polished, for example by chemical mechanical planarization (CMP) techniques, to a thickness of about 50-300 nanometers (run) depending on the circuit function being implemented.
  • CMP chemical mechanical planarization
  • Both the monocrystalline silicon layer and the monocrystalline silicon carrier substrate preferably have a resistivity of at least about 1-35 Ohms per square.
  • the silicon can be impurity doped either N-type or P-type, but is preferably doped P-type.
  • monocrystalline semiconductor substrate 21 can be formed by the SIMOX process.
  • the SIMOX process is a well known process in which oxygen ions are implanted into a sub-surface region of monocrystalline silicon substrate 24.
  • the monocrystalline silicon substrate and the implanted oxygen are subsequently heated to form a sub-surface silicon oxide dielectric layer 26 that electrically isolates SOI layer 22 from the remaining portion of monocrystalline silicon substrate 24.
  • the thickness of SOl layer 22 is determined by the energy of the implanted ions.
  • Dielectric layer 26 is commonly referred to as a buried oxide or "BOX" and will so be referred to herein.
  • dielectric isolation regions 28, 30 extending through monocrystalline silicon layer 22 to dielectric layer or BOX 26.
  • the dielectric isolation regions are preferably formed by the well known shallow trench isolation (STI) technique in which trenches are etched into monocrystalline silicon layer 22, the trenches are filled with a dielectric material such as deposited silicon dioxide, and the excess silicon dioxide is removed by CMP.
  • STI regions 28 provide electrical isolation, as needed, between various devices of the CMOS circuit that are to be formed in monocrystalline silicon layer 22.
  • STI region 30 aids in electrically isolating the device to be formed in carrier substrate 24 from the devices to be formed in monocrystalline silicon layer 22. Either before or after the formation of dielectric isolation regions 28, 30, portions of monocrystalline silicon layer 22 can be doped, for example by ion implantation, to form P-type regions 32 and N-type regions 34.
  • a layer 35 of photoresist is applied overlying the surface of monocrystalline silicon layer 22 and dielectric isolation regions 28, 30.
  • the layer of photoresist is patterned to expose a portion of dielectric isolation region 30 as illustrated in FIG. 3.
  • the patterned photoresist is used as an ion implantation mask and conductivity determining ionic impurities are implanted, as indicated by arrows 36, into the surface of monocrystalline silicon substrate 24 to form a doped region 37.
  • phosphorus ions can be implanted into the monocrystalline silicon substrate at an energy of about
  • a layer of gate insulator material 38 is grown or deposited on the surface of silicon layer 22.
  • the gate insulator may be a thermally grown silicon dioxide formed by heating the silicon substrate in an oxidizing ambient, or may be a deposited insulator such as a silicon oxide, silicon oxynitride, silicon nitride, a high dielectric constant insulator such as HfSiO, or the like.
  • Deposited insulators can be deposited by chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD).
  • the gate insulator material is typically 1-10 nanometers (nm) in thickness.
  • gate insulator material 38 is a deposited layer that is deposited onto both the dielectric isolation regions 28, 30 and the remaining monocrystalline silicon layer 22.
  • a grown thermal oxide would be grown only on the monocrystalline silicon layer.
  • a layer 39 of gate electrode forming material such as polycrystalline silicon is deposited overlying gate insulator material 38, monocrystalline silicon layer 22, and the dielectric isolation regions 28, 30.
  • Layer 39 will hereinafter be referred to as a polycrystalline silicon layer although those of skill in the art will recognize that other conductive materials could be used as the gate electrode material.
  • the layer of polycrystalline silicon is preferably deposited as undoped polycrystalline silicon and is subsequently impurity doped by ion implantation.
  • Polycrystalline gate electrode layer 39 is patterned and etched to form a P-channel gate electrode 40 overlying N-type region 34 of monocrystalline silicon layer 22, an N-channel gate electrode 42 overlying P-type region 32 of monocrystalline silicon layer 22 and a spacer 44 overlying dielectric isolation region 30.
  • the etching of polycrystalline gate electrodes is well advanced in the art so that gate lengths of only 45 nm or less can be achieved.
  • Polycrystalline silicon gate electrode layer 39 is preferably etched using such well know and advanced patterning and etching techniques to preferably obtain gate electrodes 40 and 42 and spacer 44, each having minimum feature size.
  • Such advanced patterning and etching techniques generally involve patterning and etching the polycrystalline silicon using the minimum available photolithography exposure feature size followed by isotropically etching the polycrystalline silicon to further reduce the width of the resulting structure.
  • a layer 46 of photoresist is applied to the structure and is patterned to expose a portion of dielectric isolation region 30 and spacer 44.
  • the patterned layer of photoresist and spacer 44 are used together as an etch mask to etch openings 48 and 50 through dielectric isolation region 30 and dielectric insulating layer 26 and to expose portions of impurity doped region 37.
  • Openings 48 and 50 are anisotropically etched through dielectric isolation region 30 and dielectric insulating layer 26, preferably by reactive ion etching.
  • the dielectric layers can be reactive ion etched, for example, using a CF 4 or CHF 3 chemistry.
  • the spacing between openings 48 and 50 is determined, not by the spacing of openings in layer 46 of photoresist, but by the width of spacer 44 and hence, in accordance with an embodiment of the invention, is comparable to the minimum feature size.
  • the spacing between openings 48 and 50 can thus be less than the minimum photolithographic feature spacing otherwise attainable through photolithographic patterning and etching alone.
  • photoresist layer 52 can next be applied to the structure and patterned to expose one of openings 48 and 50 while masking the other of the openings.
  • the photoresist layer is also patterned to expose one of regions 32 and 34 while masking the other of the regions.
  • photoresist layer 52 has been patterned to expose opening 48 and P-type region 32.
  • Patterned photoresist layer 52 is used as an ion implantation mask and N-type impurity dopant ions, preferably arsenic ions, are implanted into the exposed areas as indicated by arrows 54.
  • the N-type impurity dopant ions form source 56 and drain 58 regions of an N-channel MOS transistor that are self aligned with gate electrode 42 and a cathode region 60 self aligned with one edge of spacer 44.
  • Layer 52 of photoresist is removed and another layer 62 of photoresist is applied to the structure and is patterned to expose the other of openings 48 and 50 and the other of regions 32 and 34 while masking the previously exposed opening and region.
  • photoresist layer 62 is patterned to expose opening 50 and region 34.
  • Patterned photoresist layer 62 is used as an ion implantation mask and P- type impurity dopant ions, preferably boron ions, are implanted into the exposed areas as indicated by arrows 64.
  • the P-type impurity dopant ions form source 66 and drain 68 regions of a P-channel MOS transistor that are self aligned with gate electrode 40 and an anode region 70 self aligned with the other edge of spacer 44.
  • Photoresist layer 52 is removed and the ion implanted regions are heated, preferably by rapid thermal annealing, to activate the implanted ions.
  • Other conventional method steps such as the formation of sidewall spacers on the gate electrodes, implantation of additional source and drain regions, removal of gate insulator material that is not disposed under a gate electrode, and the like, may now be carried out to complete the processing of the MOS transistors.
  • a layer of suicide forming metal such as nickel, cobalt, titanium, palladium, or the like is deposited onto the structure and in contact with the ion implanted source, drain, anode and cathode regions as well as to gate electrodes 40 and 42.
  • the suicide forming metal preferably has a thickness of about 5-15 nm.
  • the suicide forming metal is heated, preferably to a temperature of about 350° - ' 500 0 C to cause the metal to react with the silicon with which it is in contact to form a metal suicide contact region 72 at the surface of each of the ion implanted regions and on the gate electrodes as illustrated in FIG. 9.
  • the metal that is not in contact with silicon for example the metal that is deposited on the dielectric isolation regions, does not react during the heating step and is removed, for example by wet etching in a H 2 O 2 ZH 2 SO 4 or HNO 3 /HCI solution.
  • a layer 74 of insulating material is deposited and planarized to cover the contact regions.
  • the insulating material can be deposited, for example, by low pressure chemical vapor deposition using a tetraethylorthosilicate source.
  • Layer 74 is preferably planarized by CMP.
  • a layer of photoresist (not illustrated) is applied to the surface of the planarized insulating material and is used as an etch mask to etch contact openings 76 that extend through the insulating material to the metal silicide contact regions.
  • Contact plugs 78 are formed in each of contact openings 76 to allow electrical contact to the various device regions.
  • the contact plugs can be formed, for example, by depositing successive layers of titanium, titanium nitride, and tungsten in known manner. The excess metal layers can then be removed by CMP to leave contact plugs 78 as illustrated in FIG. 11.
  • CMP CMP
  • Prior SOI integrated circuits have included diodes fabricated in the monocrystalline silicon substrate as well as other circuit components formed in the thin monocrystalline silicon layer overlying an insulating layer, but in fabricating such circuits the anode and cathode regions have been defined in the substrate by patterning and etching the overlying thin silicon layer and the insulating layer using conventional photolithography techniques. That is, the anode and cathode regions were defined by separate mask patterns that were, at best, spaced apart by a distance equal to the minimum feature size. By fabricating substrate devices using an embodiment of the invention, it is possible to reduce the spacing between regions in the substrate to a distance equal to the width of the minimum achievable gate length.
  • FIG. 12 The benefit that can be realized by fabricating substrate devices in accordance with an embodiment of the invention can be seen by comparing a substrate diode fabricated by the conventional method, as illustrated in FIG. 12 with the substrate diode fabricated in accordance with an embodiment of the invention as illustrated in FIG. 13.
  • FIGS. 12 and 13 only the diode portion of the SOI integrated circuit is illustrated.
  • FIG. 13 the same numbering has been used as was used in FIG. 11; corresponding regions in FIG. 12 have been given the same numbers.
  • the spacing between the anode and the cathode of the prior art device, indicated by double headed arrow 86, is two and one half to 5ve times the spacing, indicated by the double headed arrow 88, between the anode and the cathode of the diode fabricated in accordance with an embodiment of the invention.

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Abstract

A method is provided for fabricating a semiconductor on insulator (SOI) device [20]. The method includes, in one embodiment, providing a monocrystalline silicon substrate [24] having a monocrystalline silicon layer [22] overlying the substrate and separated therefrom by a dielectric layer [26]. A gate electrode material [39] is deposited and patterned to form a gate electrode [40, 42] and a spacer [44]. Impurity determining dopant ions [54, 56] are implanted into the monocrystalline silicon layer [22] using the gate electrode [40, 42] as an ion implant mask to form spaced apart source [56, 66] and drain [58, 68] regions in the monocrystalline silicon layer [22] and into the monocrystalline silicon substrate [24] using the spacer [44] as an ion implant mask to form spaced apart device regions [60, 70] in the monocrystalline substrate [24]. Electrical contacts [76] are then formed that contact the spaced apart device regions [60, 70].

Description

METHOD FOR FABRICATING SOI DEVICE
TECHNICAL FIELD
[0001] The present invention generally relates to a method for fabricating semiconductor on insulator (SOI) devices, and more particularly relates to a method for fabricating SOI integrated circuits having devices in both the thin SOI layer and the substrate.
BACKGROUND
[0002J The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). The ICs are usually formed using both P-channel and N-channel FETs and the IC is then referred to as a complementary MOS or CMOS circuit. Certain improvements in performance of FET ICs can be realized by forming the FETs in a thin layer of semiconductor material overlying an insulator layer. Such semiconductor on insulator (SOI) FETs, for example, exhibit lower junction capacitance and hence can operate at higher speeds. It is advantageous in certain applications, however, to fabricate at least some devices in the semiconductor substrate that supports the insulator layer. The devices formed in the substrate, for example, may have better thermal properties and can support higher voltages than devices formed in the thin semiconductor layer.
[0003] As the complexity of the integrated circuits increases, more and more MOS transistors are needed to implement the integrated circuit function. As more and more transistors are designed into the IC, it becomes important to shrink the size of individual MOS transistors so that the size of the IC remains reasonable and the IC can be reliably manufactured. Shrinking the size of an MOS transistor implies that the minimum feature size, that is, the minimum width of a line or the minimum spacing between lines, is reduced. MOS transistors have now been aggressively reduced to the point at which the gate electrode of the transistor is less than or equal to 45 nanometers (πm) in width. Methods previously used to fabricate devices in the substrate of an SOI structure, however, have not be able to achieve the same minimum feature size in substrate devices as are realized in the devices formed in the thin semiconductor layer.
[0004] Accordingly, it is desirable to provide a method for fabricating SOI devices having minimum feature size. In addition, it is desirable to provide a self aligned method for fabricating SOI devices having minimum feature size substrate devices. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.
BRIEF SUMMARY
[0005] A method is provided for fabricating a semiconductor on insulator (SOI) device. The method includes, in one embodiment, providing a monocrystalline silicon substrate having a monocrystalline silicon layer overlying the substrate and separated therefrom by a dielectric layer. A gate electrode material is deposited and patterned to form a gate electrode and a spacer. Impurity determining dopant ions are implanted into the monocrystatline silicon layer using the gate electrode as an ion implant mask to form spaced apart source and drain regions in the monocrystalline silicon layer and into the monocrystalline silicon substrate using the spacer as an ion implant mask to form spaced apart device regions in the monocrystalline substrate. Electrical contacts are then formed that contact the spaced apart device regions.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] The present invention will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and wherein
[0007] FIG. 1-11 schematically illustrate, in cross section, process steps in accordance with various embodiments of the invention;
[0008] FIG. 12 illustrates, in cross section, a prior art substrate diode; and
FIG. 13 schematically illustrates, in cross section, a substrate diode in accordance with an embodiment of the invention.
DETAILED DESCRIPTION
[0009] The following detailed description is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or the following detailed description.
[0010] FIGS. 1-11 schematically illustrate method steps for the manufacture of a CMOS integrated circuit 20 in accordance with various embodiments of the invention. Although the term "MOS device" properly refers to a device having a metal gate electrode and an oxide gate insulator, that term will be used throughout to refer to any semiconductor device that includes a conductive gate electrode (whether metal or other conductive material) that is positioned over a gate insulator (whether oxide or other insulator) which, in turn, is positioned over a semiconductor substrate. In these illustrative embodiments only a small portion of CMOS integrated circuit 20 is illustrated. Various steps in the manufacture of CMOS devices are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well known process details. Although in this illustrative embodiment integrated circuit 20 is a CMOS circuit, the invention is also applicable to the fabrication of a single channel type MOS circuit.
[0011] As illustrated in FIG. 1, the method in accordance with one embodiment of the invention begins with providing a semiconductor substrate 21. The semiconductor substrate is preferably a silicon substrate with a monocrystalline silicon layer 22 formed overlying a monocrystalline silicon carrier substrate 24. As used herein, the terms "silicon layer" and "silicon substrate" will be used to encompass the relatively pure monocrystalline silicon materials typically used hi the semiconductor industry as well as silicon admixed with other elements such as germanium, carbon, and the like to form substantially monocrystalline semiconductor material. Monocrystalline silicon layer 22 will be used in the formation of N-channel and P-channel MOS transistors. Monocrystalline silicon substrate 24 will be used for the formation of a substrate device herein illustrated as a PN junction diode. Monocrystalline silicon layer 22 can be formed, for example, by the well known layer transfer technique. In that technique hydrogen is implanted into a subsurface region of an oxidized monocrystalline silicon wafer. The implanted wafer is then flip bonded to monocrystalline silicon substrate 24. A two phase heat treatment is then carried out to split the hydrogen implanted wafer along the implanted region and to strengthen the bonding, leaving a thin monocrystalline silicon layer 22 bonded to the monocrystalline silicon substrate and separated from the substrate by a dielectric insulating layer 26. The monocrystalline silicon layer is then thinned and polished, for example by chemical mechanical planarization (CMP) techniques, to a thickness of about 50-300 nanometers (run) depending on the circuit function being implemented. Both the monocrystalline silicon layer and the monocrystalline silicon carrier substrate preferably have a resistivity of at least about 1-35 Ohms per square. The silicon can be impurity doped either N-type or P-type, but is preferably doped P-type. Dielectric insulating layer 26, typically silicon dioxide, preferably has a thickness of about 50-200 nm.
[0012] As one alternative to the wafer bonding technique, monocrystalline semiconductor substrate 21 can be formed by the SIMOX process. The SIMOX process is a well known process in which oxygen ions are implanted into a sub-surface region of monocrystalline silicon substrate 24. The monocrystalline silicon substrate and the implanted oxygen are subsequently heated to form a sub-surface silicon oxide dielectric layer 26 that electrically isolates SOI layer 22 from the remaining portion of monocrystalline silicon substrate 24. The thickness of SOl layer 22 is determined by the energy of the implanted ions. Dielectric layer 26 is commonly referred to as a buried oxide or "BOX" and will so be referred to herein.
[0013] Having provided a semiconductor substrate 21, the method in accordance with one embodiment of the invention continues as illustrated in FIG. 2 by the formation of dielectric isolation regions 28, 30 extending through monocrystalline silicon layer 22 to dielectric layer or BOX 26. The dielectric isolation regions are preferably formed by the well known shallow trench isolation (STI) technique in which trenches are etched into monocrystalline silicon layer 22, the trenches are filled with a dielectric material such as deposited silicon dioxide, and the excess silicon dioxide is removed by CMP. STI regions 28 provide electrical isolation, as needed, between various devices of the CMOS circuit that are to be formed in monocrystalline silicon layer 22. In accordance with an embodiment of the invention, STI region 30 aids in electrically isolating the device to be formed in carrier substrate 24 from the devices to be formed in monocrystalline silicon layer 22. Either before or after the formation of dielectric isolation regions 28, 30, portions of monocrystalline silicon layer 22 can be doped, for example by ion implantation, to form P-type regions 32 and N-type regions 34.
[0014] In accordance with one embodiment of the invention, a layer 35 of photoresist is applied overlying the surface of monocrystalline silicon layer 22 and dielectric isolation regions 28, 30. The layer of photoresist is patterned to expose a portion of dielectric isolation region 30 as illustrated in FIG. 3. The patterned photoresist is used as an ion implantation mask and conductivity determining ionic impurities are implanted, as indicated by arrows 36, into the surface of monocrystalline silicon substrate 24 to form a doped region 37. For example, phosphorus ions can be implanted into the monocrystalline silicon substrate at an energy of about
200-300 KeV and dose of about lxl0l3-2xl014 cm'2 to form an N-type doped region 37. [OOliSj As illustrated in FIG. 4, after removing layer 35 of photoresist, a layer of gate insulator material 38 is grown or deposited on the surface of silicon layer 22. The gate insulator may be a thermally grown silicon dioxide formed by heating the silicon substrate in an oxidizing ambient, or may be a deposited insulator such as a silicon oxide, silicon oxynitride, silicon nitride, a high dielectric constant insulator such as HfSiO, or the like. Deposited insulators can be deposited by chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD). The gate insulator material is typically 1-10 nanometers (nm) in thickness. As illustrated, gate insulator material 38 is a deposited layer that is deposited onto both the dielectric isolation regions 28, 30 and the remaining monocrystalline silicon layer 22. As is well known, a grown thermal oxide would be grown only on the monocrystalline silicon layer. A layer 39 of gate electrode forming material such as polycrystalline silicon is deposited overlying gate insulator material 38, monocrystalline silicon layer 22, and the dielectric isolation regions 28, 30. Layer 39 will hereinafter be referred to as a polycrystalline silicon layer although those of skill in the art will recognize that other conductive materials could be used as the gate electrode material. The layer of polycrystalline silicon is preferably deposited as undoped polycrystalline silicon and is subsequently impurity doped by ion implantation.
[0016] The method in accordance with an embodiment of the invention proceeds as illustrated in FIG. 5. Polycrystalline gate electrode layer 39 is patterned and etched to form a P-channel gate electrode 40 overlying N-type region 34 of monocrystalline silicon layer 22, an N-channel gate electrode 42 overlying P-type region 32 of monocrystalline silicon layer 22 and a spacer 44 overlying dielectric isolation region 30. The etching of polycrystalline gate electrodes is well advanced in the art so that gate lengths of only 45 nm or less can be achieved. Polycrystalline silicon gate electrode layer 39 is preferably etched using such well know and advanced patterning and etching techniques to preferably obtain gate electrodes 40 and 42 and spacer 44, each having minimum feature size. Such advanced patterning and etching techniques generally involve patterning and etching the polycrystalline silicon using the minimum available photolithography exposure feature size followed by isotropically etching the polycrystalline silicon to further reduce the width of the resulting structure.
[0017] As illustrated in FIG. 6, a layer 46 of photoresist is applied to the structure and is patterned to expose a portion of dielectric isolation region 30 and spacer 44. In accordance with an embodiment of the invention, the patterned layer of photoresist and spacer 44 are used together as an etch mask to etch openings 48 and 50 through dielectric isolation region 30 and dielectric insulating layer 26 and to expose portions of impurity doped region 37. Openings 48 and 50 are anisotropically etched through dielectric isolation region 30 and dielectric insulating layer 26, preferably by reactive ion etching. The dielectric layers can be reactive ion etched, for example, using a CF4 or CHF3 chemistry. The spacing between openings 48 and 50 is determined, not by the spacing of openings in layer 46 of photoresist, but by the width of spacer 44 and hence, in accordance with an embodiment of the invention, is comparable to the minimum feature size. The spacing between openings 48 and 50 can thus be less than the minimum photolithographic feature spacing otherwise attainable through photolithographic patterning and etching alone.
[0018] After removing layer 46 of photoresist another layer 52 of photoresist can next be applied to the structure and patterned to expose one of openings 48 and 50 while masking the other of the openings. The photoresist layer is also patterned to expose one of regions 32 and 34 while masking the other of the regions. As illustrated in FIG. 7, photoresist layer 52 has been patterned to expose opening 48 and P-type region 32. Patterned photoresist layer 52 is used as an ion implantation mask and N-type impurity dopant ions, preferably arsenic ions, are implanted into the exposed areas as indicated by arrows 54. The N-type impurity dopant ions form source 56 and drain 58 regions of an N-channel MOS transistor that are self aligned with gate electrode 42 and a cathode region 60 self aligned with one edge of spacer 44.
[0019] Layer 52 of photoresist is removed and another layer 62 of photoresist is applied to the structure and is patterned to expose the other of openings 48 and 50 and the other of regions 32 and 34 while masking the previously exposed opening and region. As illustrated in FIG. 8, photoresist layer 62 is patterned to expose opening 50 and region 34. Patterned photoresist layer 62 is used as an ion implantation mask and P- type impurity dopant ions, preferably boron ions, are implanted into the exposed areas as indicated by arrows 64. The P-type impurity dopant ions form source 66 and drain 68 regions of a P-channel MOS transistor that are self aligned with gate electrode 40 and an anode region 70 self aligned with the other edge of spacer 44. Photoresist layer 52 is removed and the ion implanted regions are heated, preferably by rapid thermal annealing, to activate the implanted ions. Other conventional method steps (not illustrated) such as the formation of sidewall spacers on the gate electrodes, implantation of additional source and drain regions, removal of gate insulator material that is not disposed under a gate electrode, and the like, may now be carried out to complete the processing of the MOS transistors.
[00201 In accordance with an embodiment of the invention a layer of suicide forming metal such as nickel, cobalt, titanium, palladium, or the like is deposited onto the structure and in contact with the ion implanted source, drain, anode and cathode regions as well as to gate electrodes 40 and 42. The suicide forming metal preferably has a thickness of about 5-15 nm. The suicide forming metal is heated, preferably to a temperature of about 350° - '5000C to cause the metal to react with the silicon with which it is in contact to form a metal suicide contact region 72 at the surface of each of the ion implanted regions and on the gate electrodes as illustrated in FIG. 9. The metal that is not in contact with silicon, for example the metal that is deposited on the dielectric isolation regions, does not react during the heating step and is removed, for example by wet etching in a H2O2ZH2SO4 or HNO3/HCI solution.
[0021] As illustrated in FIG. 10 a layer 74 of insulating material is deposited and planarized to cover the contact regions. The insulating material can be deposited, for example, by low pressure chemical vapor deposition using a tetraethylorthosilicate source. Layer 74 is preferably planarized by CMP. Following the planarization, a layer of photoresist (not illustrated) is applied to the surface of the planarized insulating material and is used as an etch mask to etch contact openings 76 that extend through the insulating material to the metal silicide contact regions.
[0022] Contact plugs 78 are formed in each of contact openings 76 to allow electrical contact to the various device regions. The contact plugs can be formed, for example, by depositing successive layers of titanium, titanium nitride, and tungsten in known manner. The excess metal layers can then be removed by CMP to leave contact plugs 78 as illustrated in FIG. 11. Those of skill in the art will understand that contact openings 76 and contact plugs 78 may not be needed to contact each and every one of the silicide contact regions, but rather that such contacting will be dictated by the details of the circuit being implemented.
[0023] Those of skill in the art will appreciate that alternative and/or additional steps may be used to fabricate integrated circuit 20 and the order of the method steps may be changed without departing from the broad scope of the invention. For example, sidewall spacers may be formed at the edges of the gate electrodes and those spacers may be used as masks for additional ion implantations or to space the metal silicide contacts apart from the gate electrodes.
[0024] Prior SOI integrated circuits have included diodes fabricated in the monocrystalline silicon substrate as well as other circuit components formed in the thin monocrystalline silicon layer overlying an insulating layer, but in fabricating such circuits the anode and cathode regions have been defined in the substrate by patterning and etching the overlying thin silicon layer and the insulating layer using conventional photolithography techniques. That is, the anode and cathode regions were defined by separate mask patterns that were, at best, spaced apart by a distance equal to the minimum feature size. By fabricating substrate devices using an embodiment of the invention, it is possible to reduce the spacing between regions in the substrate to a distance equal to the width of the minimum achievable gate length. The benefit that can be realized by fabricating substrate devices in accordance with an embodiment of the invention can be seen by comparing a substrate diode fabricated by the conventional method, as illustrated in FIG. 12 with the substrate diode fabricated in accordance with an embodiment of the invention as illustrated in FIG. 13. In FIGS. 12 and 13 only the diode portion of the SOI integrated circuit is illustrated. In FIG. 13, the same numbering has been used as was used in FIG. 11; corresponding regions in FIG. 12 have been given the same numbers. The spacing between the anode and the cathode of the prior art device, indicated by double headed arrow 86, is two and one half to 5ve times the spacing, indicated by the double headed arrow 88, between the anode and the cathode of the diode fabricated in accordance with an embodiment of the invention.
[0025] While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the exemplary embodiment or exemplary embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope of the invention as set forth in the appended claims and the legal equivalents thereof.

Claims

CLAIMSWhat is claimed is:
1. A method for fabricating a semiconductor on insulator (SOI) device [20] having a monocrystalline silicon layer [22] overlying a monocrystalline silicon substrate [24] and separated therefrom by a dielectric layer [26], the method comprising the steps of:
depositing a gate electrode material [39] overlying the monocrystalline silicon layer [22];
patterning the gate electrode material [39] to form a gate electrode [40, 42] and a spacer [44];
ion implanting impurity determining dopant ions [54, 64] into the monocrystalline silicon layer [22] using the gate electrode [40, 42] as an ion implant mask to form spaced apart source [56, 66] and drain [58, 68] regions in the monocrystalline silicon layer;
ion implanting impurity determining dopant ions [54, 56] into the monocrystalline silicon substrate [24] using the spacer [44] as an ion implant mask to form spaced apart device regions [60, 70] in the monocrystalline substrate [24]; and
electrically contacting [76] the spaced apart device regions [60, 70].
2. The method of claim 1 wherein the step of patterning the gate electrode material [39] comprises the steps of:
photolithographically patterning and etching the gate electrode material using a minimum lithography feature size; and
thereafter reducing the width of the gate electrode [40, 42] and spacer [44] by isotropically etching the gate electrode material [39].
3. The method of claim 1 wherein the step of ion implanting to form spaced apart device regions comprises the steps of:
ion implanting an N-type impurity determining dopant [54] to form an N-type device region [60]; and
ion implanting a P-type impurity determining dopant [64] to form a P-type device region [70].
4. The method of claim 3 wherein the step of ion implanting an N-type impurity determining dopant [54] further comprises the step of ion implanting an N-type impurity determining dopant to form N-channel source [56] and drain [58] regions in the monocrystalline silicon layer [22] and the step of ion implanting a P- type impurity determining dopant [64] further comprises the step of ion implanting a P-type impurity determining dopant to form P-channel source [66] and drain [68] regions in the monocrystalline silicon layer [22].
5. A method for fabricating a semiconductor on insulator (SOI) device [20] having a monocrystalline silicon layer [22] overlying a monocrystalline silicon substrate [24] and separated therefrom by a dielectric layer [26], the method comprising the steps of:
forming a dielectric isolation region [30] extending through the monocrystalline silicon layer [22] to the dielectric layer [26];
depositing a layer of gate electrode material [39] overlying the monocrystalline silicon layer [22] and the dielectric isolation region [30];
patterning the layer of gate electrode material [39] to simultaneously form a gate electrode [40, 42] overlying the monocrystalline silicon layer [22] and a spacer [44] overlying the dielectric isolation region [30];
etching the dielectric isolation region [30] and the dielectric layer [26] using the spacer [44] as an etch mask; and
ion implanting impurity determining dopant ions [54, 64] to form spaced apart device regions [60, 70] in the monocrystalline silicon substrate [24] using the spacer [44] as an ion implantation mask.
6. The method of claim 5 wherein the step of patterning the layer of gate electrode material [39] comprises the step of patterning the layer of gate electrode material [39] to form a gate electrode [40, 42] and a spacer [44] each have a minimum width.
7. The method of claim 6 wherein the step of ion implanting impurity determining dopant ions [54, 64] to form spaced apart device regions [60, 70] comprises the steps of:
ion implanting a P-type region [70] to form an anode of a substrate diode; and
ion implanting an N-type region [60] to form a cathode of a substrate diode.
8. A method for fabricating a semiconductor on insulator (SOI) device [20] having a monocrystalline silicon layer [22] overlying a monocrystalline silicon substrate [24] and separated therefrom by a dielectric layer [26], the method comprising the steps of:
forming a dielectric isolation region [30] extending through the monocrystalline silicon layer [22] to the dielectric layer [26];
depositing a gate electrode layer [39] overlying the monocrystalline silicon layer [22] and the dielectric isolation region [30];
patterning the gate electrode layer [30] to form a P-channel gate electrode [40] and an N-channel gate electrode [42] overlying the monocrystalline silicon layer [22] and a spacer [44] overlying the dielectric isolation region [30]; etching through the dielectric isolation region [30] and the dielectric layer [26] using the spacer [44] as an etch mask to expose an anode region [70] and a cathode region [60] spaced apart in the monocrystalline silicon substrate [24];
implanting P-type impurity dopants [64] into the monocrystalline silicon layer [22] to form source [66] and drain [68] regions of a P-channel MOS transistor proximate the P-channel gate electrode [40] and into the anode region [70] in the monocrystalline silicon substrate [24] to form an anode of a substrate diode;
implanting N-type impurity dopants [54] into the monocrystalline silicon layer [22] to form source [56] and drain [58] regions of an N-channel MOS transistor proximate the N-channel gate electrode [42] and into the cathode region [60] in the monocrystalline silicon substrate [24] to form a cathode of a substrate diode;
forming a metal suicide [72] in electrical contact with the anode [70] and the cathode [60];
depositing an electrically insulating layer [74] overlying the metal suicide [72];
etching contact openings [76] extending through the electrically insulating layer [74] to expose a portion of the metal suicide [72]; and
forming electrical contacts [78] contacting the anode [70] and the cathode [60] through the contact openings [76].
9. The method of claim 8 further comprising the step of ion implanting a well region [37] in the monocrystalline silicon substrate [24] in which the anode [70] and the cathode [60] are formed.
10. The method of claim 8 wherein the step of patterning the gate electrode material [39] comprises the steps of:
patterning the gate electrode material [39] using a photolithographic patterning and etching process to achieve a spacer having a minimum photolithographic feature size; and
subsequently isotropically etching the spacer to reduce the minimum photolithographic feature size.
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GB2459072B (en) * 2007-01-31 2011-06-29 Advanced Micro Devices Inc An SOI device having a substrate diode with process tolerant configuration and method of forming the SOI device
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CN100562988C (en) 2009-11-25
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TW200735263A (en) 2007-09-16
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GB0721841D0 (en) 2007-12-27
US7741164B2 (en) 2010-06-22
US7361534B2 (en) 2008-04-22
GB2440861B (en) 2010-06-16
US20080138941A1 (en) 2008-06-12
DE112006001169B4 (en) 2012-04-26
DE112006004256A5 (en) 2013-04-25
GB2440861A (en) 2008-02-13
JP5079687B2 (en) 2012-11-21
US20060258110A1 (en) 2006-11-16
CN101180725A (en) 2008-05-14

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