JP2003224264A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that has a gate electrode having a width narrower than the minimum width formable by the patterning technology and an LDD structure the side wall thickness of which can be changed as the size of the gate electrode is reduced, and to provide a method of manufacturing the device. <P>SOLUTION: After a gate electrode forming film and a gate electrode cover film are formed on a semiconductor substrate, the gate electrode is formed by etching the gate electrode forming film by anisotropic etching and by using a gate electrode cover formed by patterning the gate electrode cover film as a mask. Then the width of the gate electrode is made narrower than that of the gate electrode cover by etching the side face of the gate electrode by isotropic etching. Thereafter, a side wall film is formed and a side wall which is made thicker by the amount of the protrusion of the protruded section of the gate electrode cover from the narrowed gate electrode is formed by etching the side wall film by anisotropic etching. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method.

[0002]

2. Description of the Related Art In recent years, with the demand for higher integration and higher performance in semiconductor devices, miniaturization of elements formed on a semiconductor substrate, which is the base of semiconductor devices, by microfabrication, and element characteristics. Is desired to be improved.

In particular, when a MOS transistor is formed on a semiconductor substrate, the electrode-width dimension of the gate electrode of the MOS transistor is reduced to reduce the source-drain distance and improve the switching operation speed of the MOS transistor. MOS can be done
The transistor itself can be downsized and the degree of integration can be improved. Therefore, reducing the electrode width of the gate electrode is particularly important in the development of fine processing technology.

Conventionally, the formation of the gate electrode of the MOS transistor is performed as follows. First, FIG.
As shown in (a), a gate oxide film 110 is formed on the surface of a semiconductor substrate 100 forming a MOS transistor, a polysilicon film 120 is formed on the upper surface of the gate oxide film 110, and further, a polysilicon film 120 is formed. A tungsten silicide film 130 is formed on the upper surface of the film 120. Then, a resist 140 is applied on the upper surface of the tungsten silicide film 130.

Next, the resist 140 is exposed to a desired pattern and patterned to form a mask 140 'made of the resist 140, as shown in FIG.

Next, as shown in FIG. 12C, the tungsten silicide film 130 and the polysilicon film 120 in the non-arranged portion of the mask 140 'are etched by anisotropic dry etching to dispose the mask 140'. Tungsten silicide film 130 and polysilicon film 120
To remain.

After that, ashing and wet cleaning are performed, and as shown in FIG.
Are removed to form the gate electrode 150.

Furthermore, in order to suppress the generation of hot carriers generated in the vicinity of the drain of the MOS transistor with the recent miniaturization of the MOS transistor,
An LDD (Light Doped Drain) structure is often adopted, and silicon dioxide (SiO ₂ ) or silicon nitride (Si) is formed on the side surfaces of the source side and the drain side of the gate electrode 150.
The sidewall 160 ′ made of N) or the like may be formed.

In the case of forming the LDD structure, after forming the gate electrode 150 as described above, necessary impurities are shallowly implanted into the source region and the drain region on both sides of the gate electrode 150, and then the sidewall 160 '. 12E, a side wall film 160 to be a side wall 160 ′ is formed on the upper surface of the semiconductor substrate 100 on which the gate electrode 150 is formed by using a thermal oxidation method, a CVD method, or the like. Form a film. As the sidewall film 160, a silicon dioxide film or a silicon nitride film is used.

After forming the side wall film 160, the semiconductor substrate 100 is uniformly etched by anisotropic dry etching until the side wall film 160 on the upper surface of the gate electrode 150 is completely removed. ), The sidewall film 160 is left only on the sidewall portion of the gate electrode 150 to form the sidewall 160 '.

After forming the side wall 160 ', the source region and the drain region of the MOS transistor are deeply implanted with an impurity this time, so that the lower region of the side wall 160' is shallowly implanted with the impurity. To form an LDD structure.

Here, the side wall 160 'is usually C
Sidewall film formed uniformly by VD method etc.
Since 160 is formed by etching by anisotropic dry etching, the thickness of the sidewall 160 'is
It is almost equal to the film thickness of the formed side wall film 160.

Therefore, when the sidewalls 160 'are formed on a plurality of MOS transistors formed on the semiconductor substrate 100, the thickness of the sidewalls 160' is equal to that of all the MOS transistors.
The transistors have the same thickness.

The MOS transistor is formed by the above method. In order to reduce the electrode width of the gate electrode of the MOS transistor in order to meet the demand for higher integration and higher performance of the semiconductor device, it is necessary to reduce the width of the mask in the gate electrode portion in resist patterning. Therefore, the width dimension of the mask is further reduced by using a resist that enables fine patterning and a light source for exposure.

[0015]

However, in the currently available mask forming technology, there is a limit to the width setting of the resist for reducing the electrode width of the gate electrode in order to narrow the source-drain distance of the MOS transistor. Therefore, the gate electrode width cannot be further reduced.

Further, when the gate electrode of the MOS transistor is formed by the LDD structure, a P channel MOS
Regardless of the type of transistor, N-channel MOS transistor, etc., the sidewalls formed on the gate electrodes of all MOS transistors could only be formed to have a substantially uniform thickness as a whole.

Therefore, the thickness of the sidewall cannot be changed for each MOS transistor to adjust each MOS transistor so as to have desired characteristics. For example, a P channel MOS transistor and an N channel MOS transistor such as a CMOS transistor cannot be adjusted. In the composite MOS transistor configured by combining with the transistor, the characteristics could not be improved.

[0018]

In order to solve the above problems, in the semiconductor device of the present invention, a conductor cover film is formed on the upper surface of an electrically conductive conductor forming film formed on a semiconductor substrate. A semiconductor device having a conductor formed by etching the conductor forming film using the conductor cover formed by patterning the conductor cover film as a mask,
The conductor has a width smaller than that of the conductor cover formed by patterning.

Further, the conductive body is the gate electrode of the MOS transistor, and further, on the side surface of the gate electrode,
It is also characterized in that the sidewall having a bulged lower portion is formed.

A method of manufacturing a semiconductor device according to the present invention is
A conductor cover film is formed on the upper surface of a conductive body forming film formed on a semiconductor substrate, the conductor cover film is patterned to form a conductor cover, and the conductor cover is masked. As described above, the conductor forming film was etched by anisotropic etching to form a conductor, and then the conductor side surface was further etched by isotropic etching to make the conductor narrower than the conductor cover.

Further, the conductor is also characterized in that it is a gate electrode of a MOS transistor.

The semiconductor device manufacturing method of the present invention is
A method of manufacturing a semiconductor device having a MOS transistor, comprising: forming a gate electrode cover film on an upper surface of a gate electrode forming film formed on a semiconductor substrate; and patterning the gate electrode cover film to form a gate electrode cover. After forming and etching the gate electrode forming film by anisotropic etching using the same gate electrode cover as a mask to form the gate electrode of the MOS transistor, the side surface of the gate electrode is further etched by isotropic etching to form the gate electrode cover. A protrusion is formed on the side edge of the MOS transistor, and then a sidewall film is formed on the upper surface of the semiconductor substrate after implanting impurities into the source region and the drain region of the MOS transistor, and the gate electrode cover is covered with the sidewall film by anisotropic etching. To form sidewalls by etching until exposed After, the source region and LDD injected deeper than the impurity ahead of impurity into the drain region
It was decided to form the structure.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor device and a method of manufacturing the same according to the present invention include the steps of forming a conductor on a semiconductor substrate.
First, a conductive body forming film having conductivity, which serves as a current carrying body, is formed on a semiconductor substrate, then a conductive body cover film is formed on the upper surface of the conductive body forming film, and then the conductive body cover film is formed. The conductor cover is formed by patterning, and the conductor forming film is etched by using the conductor cover as a mask to form a conductor having a width narrower than that of the conductor cover.

Particularly, the etching of the conductor forming film is performed by the first
By performing anisotropic etching as a step, and then performing isotropic etching as a second step,
The conductor is made narrower than the conductor cover.

More specifically, the conductor is a gate electrode of a MOS transistor, and in forming the gate electrode, first, a gate electrode forming film corresponding to a conductor forming film is formed on a semiconductor substrate, Next, a gate electrode cover film corresponding to the conductor cover film is formed on the upper surface of the gate electrode forming film, and the gate electrode cover film is patterned to form a gate electrode cover corresponding to the conductor cover. .

Then, the gate electrode cover is used as a mask for the gate electrode forming film to be etched to form the gate electrode. First, anisotropic etching is performed as a first step to etch the gate electrode forming film to thereby etch the gate electrode cover. A gate electrode of a MOS transistor having the same width as that of is formed.

Then, as a second step, isotropic etching is performed to etch the side surface of the gate electrode below the gate electrode cover to make the gate electrode narrower than the gate electrode cover.

In particular, when the width dimension of the gate electrode cover is the minimum width dimension possible by the conventional patterning technique, the width dimension of the gate electrode is made smaller than the technical limit of patterning. be able to. Therefore,
The source-drain distance of the MOS transistor can be further reduced, and the switching reactivity can be improved, so that the characteristics of the MOS transistor can be improved.

When a sidewall is provided on the gate electrode to form an LDD structure, the gate electrode is etched to be narrower than the gate electrode cover, and then M
A required impurity is shallowly implanted into the drain region and the source region of the OS transistor to form an extension region, and then a sidewall film is formed on the upper surface of the semiconductor substrate.

After that, the sidewall film formed to have a uniform thickness on the upper surface of the semiconductor substrate is etched by anisotropic etching to expose the gate electrode cover from the sidewall film, while the side surface of the gate electrode is covered. Sidewalls are formed by leaving the wall film.

By etching the side surface of the gate electrode by isotropic etching as described above, a protruding portion protruding from the gate electrode is formed on the side edge of the gate electrode cover.

When the side wall film is formed, the side wall film having the same thickness as the other regions is formed on the side surface portion of the protruding portion, and the protruding size of the protruding portion is formed on the upper end of the gate electrode. A bulge portion that bulges by the amount is formed.

Therefore, when the sidewall film is etched by anisotropic dry etching in this state,
The bulging portion serves as a mask for the sidewall film immediately below the bulging portion, and the sidewall film remains just below the bulging portion due to etching. It can have a wide width as a card.

After the formation of the above sidewalls, required impurities are implanted into the drain region and the source region of the MOS transistor deeper than the implantation depth for forming the extension region to form the contact region. Form an LDD structure.

By narrowing the width of the gate electrode to reduce the source-drain distance of the MOS transistor, the lower side wall is swollen to have a large width.
The extension area can be increased and the MOS
Since the generation of hot carriers can be suppressed while increasing the switching reaction speed of the transistor, the characteristics of the MOS transistor can be improved.

Further, before the formation of the sidewall film, isotropic dry etching is performed to form a projection on the side edge of the gate electrode cover and the gate electrode is covered with an appropriate cover film. By forming the side wall film and the side wall film by forming the gate electrode not forming the protrusion on the side edge of the gate electrode cover on the same semiconductor substrate without performing anisotropic dry etching. The thickness of the sidewall formed by the etching can be made different with or without the protruding portion on the side edge of the gate electrode cover.

Therefore, it is possible to form a gate electrode having a side wall with a desired thickness according to the type of MOS transistor formed on a semiconductor substrate, so that an LDD structure in which a desired extension region is provided in each MOS transistor is formed. Can, M
The characteristics of the OS transistor can be improved.

Particularly, in the P-channel MOS transistor, the size of the extension region regulated by the thickness of the sidewall has a greater effect on the current flowing between the source and drain of the MOS transistor than in the N-channel MOS transistor. When a P-channel MOS transistor and an N-channel MOS transistor such as a CMOS transistor are formed on a semiconductor substrate, the thresholds of the P-channel MOS transistor and the N-channel MOS transistor are made different by making them different from each other. By setting the value voltage and the source / drain current separately, the characteristics of the CMOS transistor can be extremely improved.

Hereinafter, the embodiment of the present invention will be described in more detail with reference to the manufacturing process explanatory diagrams of the gate electrode of the MOS transistor shown in FIGS. 1 to 9 schematically show the manufacturing process of the gate electrode, and are partially simplified for convenience of explanation.

First, the semiconductor substrate 1 made of a silicon substrate
Is provided with an oxide separation film (not shown) at a required position in order to electrically insulate the individual elements formed on the semiconductor substrate 1 from each other. Then, as shown in FIG. The gate oxide film 2 is formed on the surface of the substrate 1, and the gate oxide film 2 is formed.
A polysilicon film 3 is formed on the upper surface of the polysilicon film 3 by the CVD (Chemical Vapor Deposition) method, and a tungsten silicide film 4 is also formed on the upper surface of the polysilicon film 3 by the CVD method.

Here, the polysilicon film 3 and the tungsten silicide film 4 are gate electrode forming films, and in some cases, the polysilicon film 3 and the tungsten silicide film 4 are formed.
The gate electrode forming film may be formed only by the polysilicon film 3, or may be formed by using an appropriate film other than the tungsten silicide film 4 instead of the laminated structure. Further, phosphorus is added to the polysilicon film 3 or various metal silicide films are further formed on the upper surface of the tungsten silicide film 4 in order to reduce the wiring resistance of the gate electrode when the gate electrode forming film is used as a gate electrode as described later. May be formed into a film.

After forming the tungsten silicide film 4, a gate electrode cover film 5 is formed on the upper surface of the tungsten silicide film 4. For the gate electrode cover film 5, it is desirable to use a material having a high selection ratio in dry etching with respect to the polysilicon film 3 and the tungsten silicide film 4 which are gate electrode forming films, such as a silicon dioxide film or a silicon nitride film. desirable. Here, a silicon dioxide film is used, and the silicon dioxide film is formed by the CVD method.

After forming the gate electrode cover film 5, a resist 6 is applied on the upper surface of the gate electrode cover film 5 in order to pattern the gate electrode cover film 5. Resist 6
After the application, the desired pattern is exposed to perform patterning to form a resist mask 6'as shown in FIG.

The resist 6 is not directly applied to the upper surface of the gate electrode cover film 5, but the BARC (Bottom Anti Reflective Coat) is applied to the upper surface of the gate electrode cover film 5.
A resist 6 may be applied after forming an antireflection film called as, to improve the patterning property of the resist 6.

Since the gate electrode of the MOS transistor is required to be miniaturized as described above, the light source used for exposure has a wavelength of 365 nm in order to perform fine patterning also in the patterning of the resist mask 6 '.
A light source capable of irradiating a short wavelength light such as an I line or an excimer laser having a wavelength of 248 nm is used.

After the formation of the resist mask 6 ', the gate electrode cover film 5 is etched to remove the BARC.
When BARC is used, BARC is also etched at the same time, so that as shown in FIG.
Gate electrode cover with the same pattern as the arrangement pattern of
Form 5 '. The etching of the gate electrode cover film 5 is
Anisotropic dry etching is performed under the etching conditions that enable the gate electrode cover film 5 to be etched. Therefore, the gate electrode cover 5'has the same width dimension as the resist mask 6 '.

After the gate electrode cover 5'is formed, ashing and wet cleaning are performed to remove the resist mask 6'and the BARC together with the resist mask 6'when the BARC is used, as shown in FIG. To do. In the present embodiment, the gate electrode cover 5'is patterned by dry etching using the resist mask 6'formed on the upper surface of the gate electrode cover film 5 as described above. The patterning of 5 ′ is not limited to this form, and an appropriate patterning method may be used.

After removing the resist mask 6 ', the tungsten silicide film 4 and the polysilicon film 3 are anisotropically dry-etched using the gate electrode cover 5'as a mask.
Etching the gate electrode cover as shown in FIG.
The gate electrode 7 is formed by leaving the tungsten silicide film 4 and the polysilicon film 3 only in the portion where 5'is provided.

By etching the tungsten silicide film 4 and the polysilicon film 3 by anisotropic dry etching, the tungsten silicide film 4 and the polysilicon film 3 have the same width as the gate electrode cover 5 '.

In the formation of the gate electrode 7 by anisotropic dry etching, it is necessary to etch a fine pattern with high accuracy. Therefore, a dry etching apparatus capable of generating high density plasma should be used. Is desirable. As an apparatus corresponding to this, for example, RIE
(Reactive Ion Etch), MRIE (Magnetron Reactiv
e Ion Etch), ICP (Inductive Coupled Plasma),
ECR (Electron Cyclotron Resonance) and the like are known.

After etching the tungsten silicide film 4 and the polysilicon film 3 by anisotropic dry etching, if it is desired to make the thickness of the sidewall in the LDD structure, which will be described later, different for each MOS transistor, the thickness of the sidewall is changed. MOS that does not need to be thick
The gate electrode 7 of the transistor is covered with a cover resist 8 as shown in FIG.

To cover the resist 8 for the cover, first, a resist is applied to the upper surface of the semiconductor substrate 1 on which the gate electrode 7 is formed, and only the resist on the portion of the gate electrode 7 to be covered with the resist 8 for the cover is left. By patterning a resist on the substrate.

A required resist 8 for covering the gate electrode 7.
Then, isotropic dry etching is performed on the gate electrode 7 not covered with the cover resist 8 using the gate electrode cover 5 ′ as a mask to remove the tungsten silicide film 4 and the polysilicon film 3. Further etching.

Since high precision etching is also required here, it is desirable to use an apparatus capable of generating high-density plasma as the dry etching apparatus, and a dry etching apparatus capable of isotropic etching. Is used.

In etching, the gate electrode cover 5 '
Is a tungsten silicide film 4 and a polysilicon film 3
Since the etching selection ratio is higher than that, the tungsten silicide film 4 and the polysilicon film 3 can be selectively etched.

Moreover, by performing isotropic etching, only the side surface of the gate electrode 7 formed by the tungsten silicide film 4 and the polysilicon film 3 is etched, and as shown in FIG. The gate electrode can be made narrower than the gate electrode cover 5 ′ due to the etching of the side surface of the gate electrode.

That is, the width of the gate electrode can be made smaller than the minimum width of the resist mask 6 '. A gate electrode having a width smaller than the width of the gate electrode cover 5'is hereinafter referred to as a narrow gate electrode 7 ', in order to distinguish it from the gate electrode 7 which is not narrow.

The narrow gate electrode 7 ′ is the gate electrode cover 5 ′.
Since the width is narrower than that of the narrow gate electrode 7 ′, the side edges of the gate electrode cover 5 ′ mounted on the narrow gate electrode 7 ′ have protrusions 9 and 9 protruding from the narrow gate electrode 7 ′. Can be formed.

Further, in the MOS transistor using the narrow gate electrode 7'as a gate electrode, the source-drain interval can be reduced, so that the switching operation speed of the MOS transistor can be improved.

Narrow width gate electrode 7'formed as described above
When the LDD structure is adopted for the MOS transistor having the above, the LDD structure is further formed by the following manufacturing process.

First, the cover resist 8 of the gate electrode 7 covered with the cover resist 8 is removed because it is not necessary to form the side wall thickly. The cover resist 8 is removed by ashing and wet cleaning. In the gate electrode 7 covered with the cover resist 8, the cover resist 8
Therefore, the width dimension of the gate electrode 7 is substantially equal to the width dimension of the gate electrode cover 5'because it is not etched during the above-mentioned isotropic dry etching.

After removing the resist 8 for the cover, FIG.
As shown in FIGS. 11A and 11A, required impurities are shallowly implanted into the drain region and the source region of the MOS transistor to form the extension region 10.

After forming the extension region 10, as shown in FIG. 8, a sidewall film 11 is formed on the upper surface of the semiconductor substrate 1 on which the gate electrode 7 and the narrow gate electrode 7'are formed. The sidewall film 11 may be a silicon dioxide film, a silicon nitride film, or the like, and is formed by using a thermal oxidation method, a CVD method, or the like.

By forming the sidewall film 11 by using the thermal oxidation method, the CVD method, or the like, the sidewall film 10 is evenly formed on the semiconductor substrate 1. Therefore, the side wall film 11 can be evenly formed on the side portions of the protruding portions 9 and 9 on the side edges of the gate electrode cover 5 ′ mounted on the narrow gate electrode 7 ′. At the top of the electrode 7 ', there is a protrusion
It is possible to form the bulged portions 12 and 12 that bulge outward by the amount corresponding to the protruding dimension of 9,9.

After forming the side wall film 11, the side wall film 11 is etched under the condition that the side wall film 11 is etched.
By performing anisotropic dry etching of 11, as shown in FIG. 9, the gate electrode 7 and the narrow gate electrode 7 ′ are formed.
Side walls 11 'and 11' are formed on the side surfaces of the.

During this anisotropic dry etching, the bulging portions 12, 12 at the upper end of the narrow gate electrode 7 ′ serve as a mask for the sidewall film 11 located immediately below the bulging portions 12, 12. Therefore, the sidewall film 11 can be left immediately below the bulges 12 and 12 due to the etching. Therefore,
By the dry etching, the wide width portions 13 and 13 can be formed in the lower portions of the sidewalls 11 ′ and 11 ′ by bulging by the protrusion size of the protrusions 9 and 9 to have a large width.

That is, when the film thickness dimension of the sidewall film 11 is T and the protrusion dimension of the protruding portions 9 and 9 is α, the width dimension of the wide width portions 13 and 13 can be T + α. 9,9
Side wall in the gate electrode 7 not formed
It is possible to form the sidewalls 11 ′, 11 ′ of the narrow gate electrode 7 ′ thicker by α than the thicknesses of 11 ′, 11 ′.

Therefore, as shown in FIG. 9, on the same semiconductor substrate 1, the sidewalls 11 'having a thickness T and the thickness T + are formed.
The α side wall 11 ′ can be formed at the same time.

The anisotropic dry etching is terminated when the sidewall film 11 on the gate electrode cover 5'mounted on the upper surfaces of the gate electrode 7 and the narrow gate electrode 7'is removed, and the sidewall is etched. The gate electrode cover 5 ′ is exposed from the film 11.

After formation of the sidewalls 11 ', FIG.
As shown in FIG. 11B and FIG. 11B, required impurities are now deeply implanted into the drain region and the source region of the MOS transistor to form the contact region 14, and the LD
It forms a D structure.

At this time, FIG. 10 (b) and FIG.
As shown in (b), the width of the extension region of the narrow gate electrode 7'where the side walls 11 ', 11' are thickened is
Gate electrode 7 without thickening the sidewalls 11 ', 11'
Can be formed larger than the width of the extension region by α.

In particular, a MOS having a narrow gate electrode 7 '.
In the transistor, the distance between the extension region on the source side and the extension region on the drain side can be made narrower than in the case of the gate electrode 7. Therefore, the MOS transistor having the narrow gate electrode 7 ′ and the gate electrode 7 The threshold voltage and the source / drain current can be made different from those of the MOS transistor having the above.

That is, by adjusting the thickness of the side wall 11 'by making the gate electrode 7 thin, the MOS
The characteristics of each transistor can be adjusted, and moreover, by the above method, the MOS transistors having different thicknesses of the sidewalls 11 'can be simultaneously formed on the same semiconductor substrate 1, and the MOS transistors having different characteristics can be easily formed simultaneously. be able to.

Therefore, like a CMOS transistor,
P-channel MOS transistor and N-channel MOS
In the case of a MOS transistor or the like configured by combining a transistor, a P-channel MOS transistor,
Since the desired characteristics can be obtained by adjusting the thickness of the third wall separately for the N-channel MOS transistor, the characteristics of the CMOS transistor which is a composite thereof can be improved.

[0075]

According to the first aspect of the present invention, since the conductor is made narrower than the conductor cover formed by patterning, the conductor is made narrower than the minimum size that can be formed by patterning. Can form the body.

According to the invention of claim 2, the conductor is M
By using the gate electrode of the OS transistor, the gate electrode can be further miniaturized, so that the source-drain interval of the MOS transistor having the same gate electrode can be made smaller and the switching reaction speed of the MOS transistor can be reduced. It can be further improved.

According to the third aspect of the present invention, the sidewall having a bulged lower portion is formed on the side surface of the gate electrode, so that the gate electrode of the MOS transistor having the sidewall has the LDD structure. And LD
Since the extension region of the D structure can be enlarged, the effect of suppressing hot carriers can be improved and the characteristics of the MOS transistor can be improved.

According to the fourth aspect of the invention, the conductor forming film is etched by anisotropic etching using the conductor cover formed by patterning the conductor cover film as a mask to form the conductor. , Furthermore, by etching the conductor side surface by isotropic etching,
A conductor having a width narrower than the minimum size that can be formed by patterning can be formed.

According to the invention of claim 5, the conductor is M
By using the gate electrode of the OS transistor, the gate electrode can be further miniaturized, so that the source-drain interval of the MOS transistor having the gate electrode can be made smaller, and the switching reaction speed of the MOS transistor can be reduced. It can be further improved.

According to the sixth aspect of the present invention, the side surface of the gate electrode is etched by isotropic etching to form the protruding portion on the side edge of the gate electrode cover. LDD according to the amount of protrusion
The sidewall thickness of the structure can be adjusted. As a result, the MOS transistor characteristics such as the threshold voltage and the source / drain current can be made different between the MOS transistors having different side wall thicknesses by adjusting the side wall thicknesses. Therefore, in a transistor formed of a composite of different MOS transistors such as a CMOS transistor, by adjusting the characteristics of the sidewall by adjusting the sidewall thickness, the composite CM can be obtained.
The characteristics of the OS transistor can be improved.

[Brief description of drawings]

FIG. 1 is an explanatory diagram illustrating a step of forming a gate electrode of a MOS transistor formed in a semiconductor device according to the present invention.

FIG. 2 is an explanatory diagram illustrating a step of forming a gate electrode of a MOS transistor formed in a semiconductor device according to the present invention.

FIG. 3 is an explanatory diagram illustrating a step of forming a gate electrode of a MOS transistor formed in the semiconductor device according to the present invention.

FIG. 4 is an explanatory diagram illustrating a step of forming a gate electrode of a MOS transistor formed in the semiconductor device according to the present invention.

FIG. 5 is an explanatory diagram illustrating a step of forming a gate electrode of a MOS transistor formed in the semiconductor device according to the present invention.

FIG. 6 is an explanatory diagram illustrating a step of forming a gate electrode of a MOS transistor formed in the semiconductor device according to the present invention.

FIG. 7 is an explanatory diagram illustrating a step of forming a gate electrode of a MOS transistor formed in the semiconductor device according to the present invention.

FIG. 8 is an explanatory diagram illustrating a step of forming a gate electrode of a MOS transistor formed in the semiconductor device according to the present invention.

FIG. 9 is an explanatory diagram illustrating a step of forming a gate electrode of a MOS transistor formed in the semiconductor device according to the present invention.

FIG. 10 is a structural explanatory diagram in the vicinity of a gate electrode of an LDD structure in a MOS transistor having a narrow gate electrode portion.

FIG. 11 is a structural explanatory view in the vicinity of a gate electrode of an LDD structure in a MOS transistor in which a gate electrode portion is not narrow.

FIG. 12 is an explanatory diagram illustrating a conventional method of forming a gate electrode of a MOS transistor.

[Explanation of symbols]

1 Semiconductor substrate 2 Gate oxide film 3 Polysilicon film 4 Tungsten silicide film 5 Gate electrode cover film 5'gate electrode cover 6 resist 6'resist mask 7 Gate electrode 7'narrow gate electrode 8 Cover resist 9 Projection 10 Extension area 11 Sidewall film 11 'sidewall 12 Bulging part 13 Wide part 14 Contact area

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 4M104 AA01 BB01 BB40 CC05 DD43                       DD64 DD65 DD66 DD67 DD91                       EE03 EE05 EE09 EE16 EE17                       FF14 GG09 HH14                 5F048 AA01 AA08 AC01 AC03 BB03                       BB05 BB08 BB12 BB15 BC06                       DA25 DA27                 5F140 AA00 AA01 AA23 AA39 AB03                       BA01 BF01 BF04 BF11 BF18                       BG08 BG12 BG14 BG20 BG22                       BG28 BG38 BG45 BG49 BG52                       BG53 BH15 BK01 CE13

Claims (6)

[Claims] 1. A conductor cover film is formed on an upper surface of an electrically conductive conductor forming film formed on a semiconductor substrate, and the conductor cover film is patterned to form a conductor cover as a mask. A semiconductor device having a conductor formed by etching a conductor forming film, wherein the conductor has a width narrower than that of a conductor cover formed by patterning. 2. The semiconductor device according to claim 1, wherein the conductor is a gate electrode of a MOS transistor. 3. The semiconductor device according to claim 2, wherein a sidewall having a bulged lower portion is formed on a side surface of the gate electrode. 4. A conductor cover film is formed on an upper surface of a conductor forming film having electrical conductivity formed on a semiconductor substrate, and the conductor cover film is patterned to form a conductor cover. After the conductor forming film is formed by etching the conductor forming film by anisotropic etching using the conductor cover as a mask, the conductor side surface is further etched by isotropic etching, so that the conductor is made more conductive than the conductor cover. A method of manufacturing a semiconductor device having a narrow width. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the conductor is a gate electrode of a MOS transistor. 6. A method of manufacturing a semiconductor device having a MOS transistor, comprising: forming a gate electrode cover film on an upper surface of a gate electrode forming film formed on a semiconductor substrate; and patterning the gate electrode cover film. To form a gate electrode cover, the gate electrode cover is used as a mask to etch the gate electrode forming film by anisotropic etching to form the gate electrode of the MOS transistor, and then the side surface of the gate electrode is further etched by isotropic etching. Then, a protrusion is formed on the side edge of the gate electrode cover, and then a sidewall film is formed on the upper surface of the semiconductor substrate after implanting impurities into the source region and the drain region of the MOS transistor, and the gate electrode is formed by anisotropic etching. By etching the cover until it is exposed from the sidewall film, After forming the Lumpur, the source region and impurities are implanted deeper than the previous impurities LDD to the drain region (Ligh
t Doped Drain) structure is formed.