Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
  • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
  • H03F3/217—Class D power amplifiers; Switching amplifiers
  • H03F3/2176—Class E amplifiers
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/222—A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/318—A matching circuit being used as coupling element between two amplifying stages
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/411—Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising two power stages
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/75—Indexing scheme relating to amplifiers the amplifier stage being a common source configuration MOSFET

Definitions

• the present invention relates generally to circuits and methods for implementing power amplifiers for millimeter wave applications. More specifically, the invention relates to circuits and methods for implementing highly efficient RF (radio frequency) switch-mode power amplifiers using bipolar junction transistors as active switching devices at millimeter-wave frequencies.
• RF radio frequency
• RF power amplifiers are designed according to one of various classes commonly designated as class A 5 B, C, D, and F, or hybrids thereof (e.g., class A/B, Class E/F, etc.). These different classes of power amplifiers differ with respect to method of operation (linear mode, switched mode), efficiency, output impedance and power output capability. For applications in which highly efficient power amplifier designs are required, switched mode Class D, E or F power amplifiers are typically implemented, as opposed to linear mode class A, B or AB power amplifier designs.
• High efficiency is obtained by operating the active device(s) as a switch rather than a controlled current source, wherein various tuning methods can be implemented to minimize or eliminate overlap between the voltage and current waveforms across the switching devices to thereby reducing power dissipation (referred to as "zero voltage switching").
• High efficiency power amplifiers are typically used in applications such as power supply converter and power supply regulator circuits, for example, where zero voltage switching is needed to reduce power consumption.
• High-efficiency switched-mode power amplifiers the highest achievable frequency of operation is limited by various factors such as the type of switching devices implemented, for example.
• Power amplifiers providing Class E operation at high frequencies typically use MESFET, HEMT, or MOSFET switching devices.
• Class E amplifiers operating at 10 GHz are known to use GaAs MESFET switching devices, but Class E amplifiers frequencies greater than 10 GHz are not known to exist.
• Class E amplifiers using bipolar transistors, for example are generally restricted to lower operating frequencies and bipolar power amplifiers operating at millimeter wave frequencies are typically designed using Class A or Class A/B operating modes. Summary of the Invention
• Exemplary embodiments of the invention generally include circuits and methods for implementing highly efficient switch-mode power amplifiers using BJTs (bipolar junction transistors) as active switching devices at millimeter-wave frequencies. More specifically, exemplary embodiments of the invention include circuits and methods for driving power amplifiers with BJT switching devices to achieve highly efficient switch-mode (e.g., Class E) operation at millimeter wave frequencies (e.g., 60 GHz).
• BJTs bipolar junction transistors
• a power amplifier circuit includes an active switch device comprising a BJT (bipolar junction transistor), and an input network coupled to a base of the BJT to drive the active switch for a switch-mode operation.
• the input network which may comprise a passive or active driver network, is designed to provide optimal driving conditions according to exemplary embodiments of the invention.
• the input network is designed to present a real input impedance in a range of about 7 Ohms to about 15 Ohms as seen from the base of the active switch device.
• an optimal driving condition includes the input network being designed to provide an asymmetrical drive current to the base of the active switch device, wherein the negative peak base current exceeds the positive peak base current.
• an optimal driving condition comprises the input network being designed to provide such asymmetrical drive base current to the active switch device such that the base voltage has a swing that does not exceed about 400 mVpp (millivolts peak-to-peak).
• the asymmetrical base current has a negative peak voltage amplitude that is greater than a positive peak voltage amplitude.
• Exemplary amplifier designs according to the invention provide power amplifiers that can operate with a fundamental frequency of about 10 GHz or more, while providing an output power of +1OdBm or greater with a power added efficiency of 15% or greater.
• FIG. 1 schematically illustrates a general architecture of a Class E power amplifier which can be designed using exemplary circuits and methods of the present invention to provide highly-efficient switched mode operation at millimeter wave frequencies.
• FIGs. 2A and 2B are exemplary timing diagrams illustrating optimal current and voltage waveforms, respectively, of the Class E power amplifier of FIG. 1 to provide zero voltage switching.
• FIG. 3 is an exemplary graphical illustration of collector efficiency as a function of transistor turn-off time for a Class E power amplifier.
• FIG. 4 is an exemplary graphical illustration of power added efficiency (PAE) of a Class E power amplifier as a function of preamplifier (driver) power consumption for three different values of efficiency in the amplifier core (70% to 50%), assuming an output power of +10 dBm, and a total (driver plus Class E core) power gain of 1OdB.
• FIGs. 5A ⁇ 5D are exemplary graphical illustrations of simulation results of transducer gain and collector efficiency as a function of source power levels for a Class E amplifier having different source impedances (Zs) of 10 Ohms and 30 Ohms.
• FIGs. 6A and 6B are exemplary graphical illustrations of simulated base voltages of a Class E amplifier having a source impedance of 30 Ohms and 10 Ohms, respectively.
• FIG. 7 is a schematic circuit diagram of a Class E amplifier circuit comprising on-chip transmission line input and output matching networks, according to an exemplary embodiment of the invention.
• FIGs. 8A ⁇ 8D are exemplary graphical illustrations of simulation results for the circuit in FIG. 7, wherein the input matching network is designed such that a low real impedance (about 7 Ohms to about 10 Ohms) is seen form the base toward the source ( shown as Z$ in Fig.7).
• FIGs. 9A ⁇ 9D are exemplary graphical illustrations of simulation results for the circuit in FIG. 7, wherein the input matching network is designed to provide conjugate matching between the power source and the switch device (e.g., transistor base).
• the switch device e.g., transistor base
• FIGs. 1OA, 1OB and 1OC are exemplary graphical illustrations of collector current, collector voltage and load voltage waveforms, respectively, for the exemplary circuit of FIG. 7, when simulated with the input matching network designed to provide a real impedance of about 7 Ohms to about 10 Ohms.
• FIGs. 1 IA and 1 IB are exemplary graphical illustrations of base voltage and base current waveforms, respectively, for the exemplary circuit of FIG. 7, when simulated with the input matching network designed to provide a real impedance of 7 Ohms to about 10 Ohms.
• FIG. 12 is a schematic circuit diagram of a conventional driver circuit for a class E power amplifier.
• FIG. 13 is a schematic circuit diagram of a two-stage power amplifier circuit according to an exemplary embodiment of the invention.
• FIGs. 14A and 14B are exemplary graphical illustrations of base voltage and base current waveforms, respectively, for the exemplary class E switching transistor Tl in FIG. 13.
• FIGs. 15A ⁇ 15D are exemplary graphical diagrams of simulation results for the exemplary two-stage amplifier of FIG. 13.
• FIG. 16 is a schematic circuit diagram of a balanced differential switch-mode power amplifier circuit according to an exemplary embodiment of the invention.
• FIG. 17 is a schematic circuit diagram of a balanced differential switch-mode power amplifier circuit according to another exemplary embodiment of the invention.
• Exemplary embodiments of the invention as described in detail hereafter generally include circuits and methods for implementing highly efficient switch-mode power amplifiers using BJT active switching devices at millimeter-wave frequencies and, in particular, circuits and methods for driving power amplifiers with BJT switching devices to achieve highly efficient switch-mode (e.g., Class E) operation at millimeter wave frequencies (e.g., 60 GHz).
• highly efficient switch-mode e.g., Class E
• millimeter wave frequencies e.g., 60 GHz.
• Class E millimeter wave frequencies
• exemplary architectures, simulations, and circuit designs will be made with specific reference to Class E power amplifiers based on silicon-germanium (SiGe) bipolar process technologies, which enable highly efficient operation at millimeter wave frequencies such as 60 GHz.
• inventive principles described herein apply generally to all classes of switched-mode power amplifier designs in which BJTs are used as switches and operated close to their maximum frequency of operation, i.e., at a frequency of approximately 10% or more of/r orfuAX-
• switched-mode power amplifier designs according to the invention can be used for building highly integrated, low cost, millimeter wave radio transceivers in silicon, for use in portable devices for wireless local-area network (WLANs) applications, for example. Indeed, for such applications, strict requirements for battery operation of portable devices has resulted in strong need for highly-efficient power amplifiers, while cost constraints have precluded the use of external components or III-V semiconductor materials.
• Existing millimeter wave power amplifier designs using class A or AB operation with SiGe BJTs have achieved power-added efficiencies (PAEs) of 3-10% for output powers in the range of +10 dBm.
• PAEs power-added efficiencies
• circuits and methods described hereafter provide switched-mode SiGe BJT power amplifiers with even higher efficiency.
• circuits and methods according to exemplary embodiments of the invention are provided for constructing two-stage, single-ended and/or differential Class E power amplifiers with output powers of +10 dBm or greater and PAEs of 15% or greater.
• These exemplary designs can be fabricated using the B ⁇ CMOS8HP processing technologies of IBM (International Business Machines) Corporation.
• a schematic circuit diagram illustrates a general architecture of a Class E power amplifier (10) which can be designed using exemplary circuits and methods of the present invention to provide highly-efficient switched mode operation at millimeter wave frequencies.
• the power amplifier (10) comprises an active switch device Tl, which is implemented as a BJT (bipolar junction transistor).
• a base terminal of the transistor Tl is connected to a base DC bias voltage F & through RF choke (11), and a collector terminal of the transistor Tl is connected to VCC power supply through RF choke (12).
• An input signal P IN is applied to the base terminal of Tl through an impedance Rs (which denotes the impedance seen from the base of transistor Tl looking to the power source).
• the series tuned LiCi circuit is designed to block DC signals and harmonic frequencies of the fundamental operating frequency
• FIGs. 2A and 2B are timing diagrams that illustrate collector voltage and current waveforms of the transistor Tl of FIG. 1 under ideal conditions where the collector efficiency is 100%.
• the transistor Tl is in an "OFF" state, wherein the current through the transistor Tl (FIG. 2A) is 0 when the collector voltage is high (FIG. 2B). During this period, the transistor Tl operates as an open switch.
• the transistor Tl is in an "ON" state, where the collector voltage is low (nearly zero) (FIG. 2B) and high current (FIG. 2A) is flowing through the switch Tl. During this period, the transistor operates as a low resistance closed switch. Under these ideal conditions, the VI product (instantaneous power dissipation by the switch Tl) is minimized through the entire period of the input power.
• V sat the transistor saturation voltage
• V sat the minimum collector voltage that can actually be attained during the collector voltage downward swing.
• a non-zero V sat while current is flowing through the transistor Tl results in power being dissipated in the transistor Tl .
• the transistor "ON" state resistance and the ON-to-OFF transition time are other significant sources of power loss. For instance, a non-zero ON-to-OFF transition time, or “turn-off' time, t/, will cause the collector voltage and current waveforms to overlap, resulting in transistor power dissipation.
• the turn-off time if/and the interaction of t/ with V sat are particularly important. If the transistor T 1 is turned on hard and driven deeply into saturation, V sat is minimized, but the turn-off time is increased.
• the collector efficiency, ⁇ as a function of the turn-off ' time of the switch is specified as:
• FIG. 3 is an exemplary graphical diagram illustrating the collector efficiency 77 as a function of turn-off time (in picoseconds) for a frequency (1/T) of 60 GHz based on equation (1) above.
• the collector efficiency will significantly degrade with an increased turn-off ' time.
• it is necessary to reach some compromise between minimizing V sat and minimizing turn-off time, both of which will contribute to power loss in the collector circuit.
• PAE P o ⁇ -Pm (2) r DC ⁇ r DR
• FIG. 4 is a diagram that graphically illustrates PAE as a function of preamplifier (driver) power consumption assuming an output power of 1OdBm and a total power gain of 1OdB (driver plus class E core) for 3 different values of the efficiency in the amplifier core (70%, 60% and 50%), based on the above equation (2). As shown in FIG. 4, the PAE efficiency significantly degrades with increased preamplifier power. 12
• exemplary embodiments of the invention include circuits and methods for driving the active switching device Tl so as to maintain Tl in an "ON" state for a period of time that minimize the combined power loss due to non-zero V sat and non-zero turn-off time, and driving the switch voltage to zero (turning the transistor "OFF") in a manner that minimizes the power dissipation of the transistor Tl .
• a single-ended Class E amplifier (as shown in FIG. 1) which is implemented using IBM's BiCMOS ⁇ HP SiGe technology, and designed for an output power of +10 dBm, various optimal driving conditions have been determined for achieving highly efficient, Class E operation for bipolar power amplifiers at millimeter wave frequencies.
• an input network as shown in FIG. 1 which is implemented using IBM's BiCMOS ⁇ HP SiGe technology, and designed for an output power of +10 dBm
• various optimal driving conditions have been determined for achieving highly efficient, Class E operation for bipolar power amplifiers at millimeter wave frequencies.
• an optimal driving condition includes the input network being designed to provide an asymmetrical drive current to the base of the active switch Tl, wherein the negative peak base current exceeds the positive peak base current.
• an optimal driving condition comprises the input network being designed to provide such asymmetrical drive base current to the transistor Tl without forcing a base voltage swing exceeding about 400mVpp (millivolts peak-to-peak).
• the exemplary source impedance will scale with increased power designs.
• the switching transistor Tl when a power amplifier is scaled to higher power outputs, the switching transistor Tl will increase in size and the required base current drive will increase.
• the optimum source impedance will be reduced (i.e., the source impedance will scale proportionally with Ohm's law.). In this manner, the optimal source impedance will scale with the power output of the Class E power amplifier.
• FIGs. 5A ⁇ 5D depict exemplary graphical illustrations of simulation results of transducer gain and collector efficiency as a function of source power levels for a Class E amplifier having different source impedances (Zs) of 10 Ohms and 30 Ohms.
• FIG. 5A graphically illustrates simulated collector efficiency and power added efficiency (PAE) versus the source power level setting for Zs of 10 and 30 Ohms.
• FIG. 5B graphically illustrates power gain versus output power level for Zs of 10 and 30 Ohms.
• FIG. 5C graphically illustrates power gain versus the source power level setting for Zs of 10 and 30 Ohms.
• FIG. 5D graphically illustrates power output versus the source power level setting for Zs of 10 and 30 Ohms.
• the straight lines in FIG. 5D are the extrapolated small signal gain, and the where the simulated gain crosses the straight lines represents the output-referred 1-dB compression point.
• FIGs. 5A ⁇ 5D show that for the higher source impedance Rs of 30 Ohms, higher input power levels are needed to achieve the same power transducer gain and collector efficiency.
• the lower source impedance of 10 Ohms provides superior PAE when the power consumed by the preceding driver stage is taken into account.
• FIGs. 5A ⁇ 5D it can be seen that the peak efficiency and power gain occurs at a lower source power level when the source impedance is 10 Ohms.
• FIGs. 6A and 6B are diagrams that illustrate simulated base voltage waveforms that were obtained for source impedances RS of 30 Ohms and 10 Ohms, respectively.
• a base voltage waveform obtained has cycle-to- cycle amplitude variations, which indicate that the transistor Tl is not being completely turned off every cycle. As depicted in FIG.
• the lower source impedance RS of 10 Ohms results in a base voltage waveform with constant amplitude variation, which confirms an exemplary driving condition of the invention that a low source impedance enables complete discharge of the minority carrier charge in the base of Tl which ensures stable switching behavior.
• FIG. 7 is a schematic circuit diagram of a Class E amplifier (100) comprising on-chip transmission line input and output matching networks, according to an exemplary embodiment of the invention.
• the Class E amplifier (100) is similar to that of FIG. 1, except that the series output inductor Lu RF choke (12) and shunt capacitor Cs in FIG. 1 are replaced by practical output impedance transformation components formed by on-chip transmission lines, TL_C (101), TL_OUT (102), and OS_OUT (103), respectively.
• the transmission line TL_C (101) is designed to have a high impedance at the operating frequency (e.g.,60GHz) and takes the place of the RF choke (12).
• the transmission line TL_OUT (102) is an electrically short length of transmission line and OS_OUT (103) is an open-stub transmission line.
• the power amplifier (100) comprises an on-chip transmission line TLJB (104), which serves as a base RF choke (11), and an on-chip transmission lines TL_IN (105) and OS_IN (106), which perform input impedance matching.
• the 50 Ohm resistor (107) represents a typical on chip microstrip transmission line with a 50 Ohm characteristic impedance.
• the input transmission line TL_JN (105) and open stub OS_IN (106) were sized to provide a real source impedance Zs of about 7 Ohms to about 10 Ohms, as seen from the base of transistor Tl towards the power source PIN.
• FIGs. 8A ⁇ 8D are exemplary graphical illustrations of simulation results for the circuit in FIG. 7, wherein the input matching network is designed such that a low real impedance (about 7 Ohms to about 10 Ohms) is seen form the base toward the source ( shown as Zs in Fig.7).
• a peak PAE of 24% and a peak power gain of 5.7 dB are obtained with an input power of +5 dBm.
• FIG 8 A graphically illustrates PAE versus source power level setting for Zs equal to 7 and 10 Ohms.
• FIG. 8B graphically illustrates collector efficiency versus source power level setting for Zs equal to 7 and 10 Ohms.
• FIG. 8C graphically illustrates power gain versus source power level setting for Zs equal to 7 and 10 Ohms.
• FIG. 8D graphically illustrates output power versus source power level setting for Zs equal to 7 and 10 Ohms.
• the straight line in FIG. 8D is the extrapolated small signal gain, where the simulated gains cross the straight line are the output-referred 1-dB compression points.
• the input transmission line TLJDST (105) and open stub OS_IN (106) in FIG. 7 were sized to provide a conjugate match (and thus maximum power transfer) between the source and the base of the transistor Tl.
• This impedance matching technique is commonly used for microwave Class E amplifier implementations and other millimeter wave power amplifiers classes.
• FIGs. 9A ⁇ 9D are exemplary graphical illustrations of simulation results for the circuit in FIG. 7, wherein the input matching network is designed to provide conjugate matching between the power source and the switch device (e.g., transistor base).
• the switch device e.g., transistor base.
• FIG. 9A graphically illustrates PAE versus source power level setting
• FIG. 9B graphically illustrates collector efficiency versus source power level setting
• FIG. 9C graphically illustrates power gain versus source power level setting
• FIG. 9D graphically illustrates output power versus source power level setting.
• an input network (which is implemented with an input transmission line and open stub) for a class E amplifier circuit is preferably designed to provide low real impedance as seen from the base towards the source, which is in contrast to conventional methods wherein the input network is designed to provide optimum power transfer.
• an input network acts as an impedance transformer from 50 Ohms (107) to about 7 to about 10 Ohms.
• FIGs. 10A ⁇ 10C and 11A ⁇ 1 IB are diagrams that graphically illustrate other simulation results obtained for the exemplary Class E amplifier circuit (100) of FIG. 7 at 60 GHz with the input matching circuit designed to provide a low real impedance of 7-10 Ohms. More specifically, FIGs 1OA, 1OB and 1OC illustrate waveforms of collector current, collector voltage and load voltage, respectively, for the exemplary Class E power amplifier circuit of FIG. 7. FIGs. 1OA and 1OB illustrate the desired non-overlapping characteristics for the collector voltage and current. Due to the high frequency of operation (60 GHz), V sat does not fall below about 500 mV while still maintaining a sufficiently fast turn-off time.
• FIGs. 1 IA and 1 IB illustrate waveforms of the base voltage and base current for the switching transistor Tl, respectively, for the exemplary Class E power amplifier circuit (100) of FIG. 7.
• the base current for the exemplary optimum drive condition is actually asymmetrical, with the negative current peaks at 4.3 mA and the positive current peaks at 3.9 mA. This asymmetry is due to the necessity of removing excess minority carrier charge from the base in order to turn off the transistor Tl .
• the base voltage swing is shown to be about 340 mVpp.
• the input network to a Class E power amplifier can be implemented using an active driver stage or preamplifier to provide increased power gain of 10 dB, for example.
• the conventional driver circuit (201) comprises a common emitter stage (Sl) followed by a double emitter follower (S2), which is typically used in high speed digital circuits operating up to 100GHz. Due to its low output impedance, the circuit (201) of FIG. 12 was initially considered a good candidate for a preamplifier.
• FIG. 13 is a schematic circuit diagram illustrating a two-stage power amplifier circuit (300) according to an exemplary embodiment of the invention.
• the exemplary two- stage power amplifier circuit (300) comprises a preamplifier circuit (301) coupled to a Class E power amplifier circuit (302).
• the preamplifier circuit (301) comprises a common- emitter driver framework comprising a common-emitter transistor T2, a load transmission line TL_CP (303), base bias choke (304) and resistor Rb, input transmission line TLJN (305) and open stub OS_IN (306), which are connected to power source PIN via a 50 Ohm transmission line (307).
• the exemplary preamplifier circuit (301) is designed in accordance with the exemplary optimum driving conditions for a class E power amplifier as discussed above.
• the load transmission line (303) for the common emitter stage is neither chosen to achieve an inter-stage match for optimum power transfer nor to form a high impedance resonant tank with the input capacitance of the power amplifier (denoted Cin) (this later option leads to a relatively high voltage gain).
• the class E power amplifier (302) is driven by an asymmetric current swing (such as depicted in FIG. 11) without forcing a voltage swing larger than 400mVp ⁇ . This can be obtained through a driver with a small output impedance and enough current capability.
• a common emitter amplifier can be represented by a transconductance with a parallel output impedance and has a Thevenin equivalent of a voltage amplifier with a series output impedance.
• the load TL_CP (303) is sized such that Zs is as close as possible to a low real impedance. For example, in one exemplary embodiment, the achieved Zs corresponds to 10 Ohms plus a series inductive component.
• the resistors Rb are connected to the base nodes of transistors Tl and T2 to provide resistive loss in the bias network, which may otherwise show resonance at lower frequencies (about 1 OGHz). In this way, unconditional stability (through an s-parameter characterization) is obtained.
• Computer simulations were performed for the exemplary two-stage power amplifier circuit (300) of FIG. 13.
• FIGs. 14A and 14B graphically illustrate simulated base voltage and base current waveforms for the switching transistor Tl in FIG. 13. It is to be noted that the base current waveform (FIG. 14B) for the switching transistor Tl is the same as the simulation results of the base current waveform (FIG. 1 IB) obtained in the design with a passive impedance transformation for the exemplary circuit of FIG. 7.
• a larger voltage swing is obtained when an active driver (preamplifier) is implemented due to the increased output impedance, as compared to the smaller output impedance obtained when a passive impedance transformer network is used (FIG. 7), but the voltage swing still is less than 400 mVpp, which is a desired optimal condition.
• FIGs. 15A ⁇ 15D are exemplary graphical diagrams of simulation results for the exemplary two-stage amplifier of FIG. 13. Specifically, FIG. 15 A graphically illustrates PAE versus source power level setting, FIG. 15B graphically illustrates collector efficiency versus source power level setting, FIG. 15C graphically illustrates power gain versus source power level setting, and FIG. 15D graphically illustrates output power versus source power level setting.
• the exemplary design achieves a PAE of 16% for +2 dBm input power, and achieves a +10 dBm output power with 10 dB power gain and a PAE > 15% at 60 GHz.
• FIG. 16 is a schematic circuit diagram of a balanced differential switch-mode power amplifier circuit according to an exemplary embodiment of the invention.
• FIG. 16 schematically illustrates a differential amplifier circuit (400) comprising a first driver circuit (301) and class E power amplifier circuit (302) (having an architecture as depicted in FIG. 13), and a second driver circuit (301 A) and class E power amplifier circuit (302A), which are mirror images of the respective driver circuit (301) and class E amplifier circuit (302) with respect to the ground line G, as shown in Fig. 16.
• a differential source in this case, 100- ⁇ differential
• the ground connections to the differential input source and differential load could optionally be omitted.
• the exemplary design provides 3 dB more output power, but the operation is otherwise substantially identical to the circuit in Fig. 13.
• FIG. 17 is a schematic circuit diagram of a balanced differential power amplifier (500) according to yet another exemplary embodiment of the invention.
• the differential amplifier circuit (500) is similar to the exemplary differential power amplifier circuit (400) of FIG. 16, except that the driver circuits include totem pole driver stages to supply drive current to the bipolar switching transistors, enabling higher power output.
• the load transmission lines TL_CP of driver circuits (301) and (301A) are replaced with bipolar transistors T3, which are driven out-of-phase with the respective transistors T2, providing both an active pull-up and pull-down.
• the transistors T3 are driven by circuits (501) and (501A), which provides biasing for Q3, optional DC level shifting, and optional impedance matching.
• Each transistor pair T2 and T3 can be biased at different DC quiescent currents by use of optional biasing RF chokes or constant current sources (not shown in FIG. 17).
• the pull-up and pull-down currents and impedances supplied to the base of switching transistors Tl can be set independently.
• the gain in the signal paths through T2 and T3 can be set independently by adjustments made in the impedance matching circuits for T2 (OS_IN and TL_IN) and T3 (SUBCKTl).
• the exemplary circuit of FIG. 17 can be designed to drive the bases of transistors Tl using optimal driving conditions, e.g., an asymmetrical base current for transistors Tl as shown in Figs. 11 and 15, a base voltage swing for transistors Tl which does not exceed 400 mVpp, and a low source impedance Zs seen from the bases of transistors Tl which yields the optimal base voltage swing.
• optimal driving conditions e.g., an asymmetrical base current for transistors Tl as shown in Figs. 11 and 15, a base voltage swing for transistors Tl which does not exceed 400 mVpp, and a low source impedance Zs seen from the bases of transistors Tl which yields the optimal base voltage swing.
• totem pole driver transistors T2 and T3 could be preceded by other differential circuits which provide appropriate drive signals to T2 and T3 (e.g., differential amplifier pair of transistors or a transformer) without changing the basic functionality.

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