WO2006118466A1 - Dispositif à mémoire permanente - Google Patents

Dispositif à mémoire permanente Download PDF

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Publication number
WO2006118466A1
WO2006118466A1 PCT/NO2006/000152 NO2006000152W WO2006118466A1 WO 2006118466 A1 WO2006118466 A1 WO 2006118466A1 NO 2006000152 W NO2006000152 W NO 2006000152W WO 2006118466 A1 WO2006118466 A1 WO 2006118466A1
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WO
WIPO (PCT)
Prior art keywords
electrodes
memory
array
memory device
volatile memory
Prior art date
Application number
PCT/NO2006/000152
Other languages
English (en)
Inventor
Isak Engquist
Per-Erik Nordal
Hans Gude Gudesen
Original Assignee
Thin Film Electronics Asa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thin Film Electronics Asa filed Critical Thin Film Electronics Asa
Publication of WO2006118466A1 publication Critical patent/WO2006118466A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/221—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using ferroelectric capacitors

Definitions

  • a non-volatile memory device A non-volatile memory device
  • the present invention concerns a non- volatile memory device comprising a carrier substrate and a plurality of memory cells, wherein each memory cell contains a memory material in the form of an electrically polarizable material, in particular an electret or ferroelectric material exhibiting hysteresis, wherein said memory cell is a capacitor-like structure with a pair of electrodes contacting directly or indirectly a volume of said memory material, said pair of electrodes when electrically connected to electronic control circuits being capable of subjecting said memory material to an electric field as well as detecting a polarization response thereto in said memory material, in order to effect write- and/or read- and/or erase operations in said cell.
  • each memory cell contains a memory material in the form of an electrically polarizable material, in particular an electret or ferroelectric material exhibiting hysteresis
  • said memory cell is a capacitor-like structure with a pair of electrodes contacting directly or indirectly a volume of said memory material, said pair of electrodes when electrically connected to electronic
  • Electret- or ferroelectric-based solid-state memories have several advantages compared to many other current memory technologies.
  • One important advantage is that the information is non- volatile, i.e. that the ferroelectric polarization and thus the stored data are not lost when the power is turned off.
  • Other advantages include a wide choice of architectures and geometries, some of which provide very high data densities.
  • each memory cell storing a bit contains one or more active elements (transistors) for cell selection during writing, reading and erasing operations.
  • memory cells are capacitor- like structures that are electrically accessed without requiring an active element associated exclusively with each cell. This may be achieved by cells arranged in a passive crosspoint matrix, with cell selection being performed by applying potentials to the matrix lines in a coordinated fashion.
  • Ferroelectric memories of the active type are commercially available and are sold in chip sizes up to at least 256 kbit. Test modules exist up to at least 64 Mbit.
  • the conventional layout of such prior art active ferroelectric memory cells is shown in some detail in fig. Ia where the switching transistor and capacitor are juxtaposed, and in fig. Ib, where the capacitor is stacked atop the transistor to save real estate.
  • Fig 2 shows an example of a physical arrangement for the embodiment of fig. Ib, wherein a tungsten plug forms a via connection between the transistor and capacitor, and where SBT is used for memory material (cf. below).
  • the traditional basic cell structure is very simple as shown in fig. 3, with the memory material 2 being sandwiched between a pair of planar electrodes Ia, Ib in a capacitor-like configuration. Addressing is typically achieved by a matrix structure of crossed sets of parallel electrodes in a so- called passive matrix addressing configuration.
  • These types of architectures provide high data density and can be realized by simple manufacturing processes, since few manufacturing steps are involved.
  • the memory material 2 can be applied globally on top of the bottom electrode 1 a (BE), e.g. by spin coating, before the top electrode Ib (TE) is applied on top of the memory film.
  • BE bottom electrode 1 a
  • TE top electrode Ib
  • the electrode/memory material interface may suffer damage or may become undesirably modified. This is particularly critical in the usual case where the memory material thickness shall be as small as possible, particularly where polymer ferroelectric materials with high coercive fields are involved.
  • a primary object of the present invention is to provide a new generation of electret- or ferroelectric- based data storage devices and methods for manufacturing and operating same, whereby the advantages of the prior art such as simplicity, speed and data density of traditional passive ferroelectric memory cells are retained, but where fundamental problems mentioned above, namely of process-related damage to the memory material or interfaces can be reduced or eliminated.
  • This primary object of the present invention is realized with a non- volatile memory device which is characterized in that pairs of electrodes are arranged in an array of one or more dimensions, and that the plurality of memory cells are formed with pairwise combinations of adjacent array electrodes such that the memory cells likewise become arranged in a corresponding array with each memory cell defined in memory material provided in or adjacent to a spacing between the electrodes of pairs provided on the carrier substrate, whereby an electric field generated by applying a potential between the electrodes of a pair extends substantially parallel to said carrier substrate, such that the memory material of the memory cell when subjected to said electric field becomes polarized in a direction along an axis of the electric field, or responds to said electric field as applied with a change in the direction or value of an already therein set polarization.
  • the electrodes are arranged in rows and columns of a two-dimensional array, and in an equally preferred embodiment thereof each array electrode is provided as a pillar-like structure extending above the carrier substrate or integrated therein. Similarly, also then the pillar-like array electrodes are arranged in rows and columns of a two-dimensional array, with the memory material advantageously provided between opposite surfaces of adjacent pillar-like array electrodes
  • figs. Ia and Ib show electrical schematics of prior art FeRAM cells with the IT/ 1C (one transistor, one capacitor per cell) architecture, as mentioned above
  • fig. 2 shows geometric structure of prior art FeRAM cells with the IT/ 1C (one transistor, one capacitor per cell) architecture, as mentioned above
  • fig. 3 the prior art "vertical" capacitor-like structure for a single memory cell, as mentioned above
  • figs. 4a and 4b show two variants of a cell structure according to the present invention
  • fig. 5 shows another variant of a cell structure according to the present invention, figs.
  • 6a and 6b show a side view and a top view, respectively, of a two- dimensional array of lateral memory cells formed between arrayed electrodes on a surface
  • fig. 7 shows a portion of a quadratic array of memory cells being read by a full row/column read voltage protocol
  • fig. 8 a portion of a quadratic array of memory cells being written by a full row/column read voltage protocol, whereby half of the cells are over- written in the process
  • fig. 9 shows a portion of a quadratic array of memory cells being read by a full row/column read voltage protocol where only a portion of the electrodes in the matrix array are at a non-zero voltage
  • fig. 10 a write/read operation on a single cell in a quadratic array, where electrode voltages are controlled in a coordinated fashion, exposing non- addressed cells in both x- and y-directions to electrical fields of E/3 or less
  • fig. 11 a variant of the write/read operation shown in fig. 10 with a different set of electrode potentials
  • fig. 12 a portion of a quadratic array of memory cells where each electrode is shaped so as to avoid spurious diagonal switching fields in excess of E/3
  • fig. 13a and 13 b show a top and a side view, respectively, of an array of memory cells that can be addressed by a passive matrix scheme
  • fig. 14 shows a portion of a passive matrix built according to the architecture shown in figs.
  • fig. 15 a portion of a passive matrix built according to the architecture shown in figs. 13a, 13b, subjected to a voltage protocol that provides parallel readout of data from a full row of memory cells in the matrix.
  • the basic premise of the present invention is that the electrodes that define the capacitor-like memory cell are formed on or in a carrier surface or substrate in such a way that the electric field between them which polarizes and interrogates the memory material is directed predominantly in a direction parallel to the supporting surface.
  • figs. 4a, 4b and 5 show the prior art conventional "vertical" capacitor-like structure, where the memory material 2 is sandwiched between a bottom electrode Ia on the supporting surface and a top electrode Ib that has been deposited on top of the memory material.
  • a potential difference is applied between the two electrodes, an electrical field is set up in the memory material, pointing in a direction essentially perpendicular to the surface.
  • Figures 4a, 4b and 5 show variants of cell structures according to the present invention, termed "lateral" cells below and the background of this concept which is not entirely unknown in the prior art, shall now briefly be discussed in order to elucidate structural and operational aspects of the memory device according to the present invention.
  • JP publication 2002/299572A discloses the structure of a straight-forward lateral memory cell.
  • memory material in the form of ferroelectric film is sandwiched between a first and second electrode provided perpendicularly to the surface of a Si substrate. Since the faces of the electrodes sandwiching the ferroelectric memory material are perpendicular to the substrate and the direction of the polarization is parallel with the plane of the substrate, the element area is not increased even if the sandwiching face is increased.
  • the capacitance of a capacitor shall be dependent on the area of the dielectric between the capacitor plates, i.e. the electrodes.
  • this apparatus discloses a data storage apparatus which exploits the piezoelectric properties of a soft ferroelectric of electret memory material. Also this apparatus employs a first set of parallel electrodes wherein recesses extending crosswise have been formed, but then provided with an electrode pair or twin electrodes and surrounded by memory material provided in the recesses and between the twin electrodes and the vertical recess surfaces of the orthogonally crossing first set of electrodes, such that memory cells are formed in the memory material and with a lateral polarization direction, i.e. either parallel to the substrate or bottom of the recesses or with the extension of the first set of electrodes.
  • two near-planar low aspect ratio or "flat" electrodes are located side by side on a surface, with a film of memory material filling the gap between them and being subjected to an electrical field with predominant components parallel to the surface.
  • two near-planar electrodes and an inert dielectric filling the gap between the electrodes present a smooth surface supporting a layer of memory material.
  • a further variant closely similar to that shown in fig. 4b but not shown here, consists of two electrodes embedded into the substrate with the top of the electrodes flush with the substrate surface.
  • the memory material may in all these cases be subjected to field components in a direction perpendicular to the surface also, but always in the same field pattern within the memory material volume.
  • two higher aspect ratio, or "pillar" electrodes extend above the carrier substrate, with the volume between them being partly or completely filled with memory material.
  • the electrical field set up in the memory material can be almost exclusively in a direction parallel to the supporting surface, and it is possible to make a memory cell with a small gap between electrodes without making the volume of memory material too small (a small gap is required if low operating voltages are desired).
  • the conventional vertical configuration differs from the lateral ones in several respects.
  • a very significant advantage of the lateral cell structures compared to the vertical ones is that deposition of a top electrode onto the memory material is avoided. This removes a major source of problems that can arise due to damage or undesired modification of the memory film during the top electrode deposition step.
  • short circuits through pinholes in the memory film are a moot point with lateral cell structures, whereas they can pose major problems in vertical cell structures employing ultrathin memory films.
  • lateral structures lend themselves to manufacturing procedures whereby incorporation of the memory material into the device structures takes place in processing steps that follow after and are well separated from those where the electronic circuitry, including electrodes defining the memory cells, are formed.
  • lateral cell structures can be arranged in dense two-dimensional arrays as illustrated in figs. 6a and 6b.
  • a quadratic two- dimensional array of lateral memory cells formed between individually addressable pillar electrodes that extend upwards from the CMOS substrate (see illustration below).
  • sol-gel deposition it is possible to fill the volume between the electrodes with an inorganic ferroelectric material such as PZT.
  • PZT inorganic ferroelectric material
  • Independent memory cells can be created both in the "x" and "y" direction, depending on which electrodes are used.
  • the memory cells can also be arranged in a one-dimensional or linear array such that the entire memory device would be a row of memory cells.
  • the electrodes on each side of each addressed cell must be given electrical potential differences that set up the appropriate electrical field in the memory material between the electrodes.
  • electrical potential differences that set up the appropriate electrical field in the memory material between the electrodes.
  • Electrodes not designated with any voltage are assumed to be at zero potential.
  • the same pattern of electric potentials can be applied to several groups of electrodes simultaneously in a large matrix array for obtaining parallel read/write operations. Potentials would then be applied in multiple isolated clusters rather than in single rows or columns.
  • a large (in principle infinite) number of different electrode patterns can be selected that would be functionally equivalent to that shown in fig. 10.
  • One example is shown in fig. 11.
  • one electrode is given a negative polarity, i.e. a potential level below the zero potential applied to electrodes contacting non-addressed cells outside the cluster surrounding the addressed cell shown.
  • the field patterns between the electrodes shall depend on the local geometry, and may to a large extent be controlled by the shape of the electrodes. This may be used to minimize detrimental effects of stray or fringe fields or to enhance field strengths in selected regions.
  • fig. 12 is shown an example where the electrodes shown in figs. 7-11 are modified so as to diminish the possible disturb fields associated with the regions marked by question marks in figures 10 and 11.
  • the two-dimensional arrangement of electrodes may be selected in a number of different ways.
  • An example is given below in conjunction with so-called passive matrix addressing, where a rectangular rather than a quadratic electrode arrangement is chosen in order to bring disturb fields in non-addressed cells below a prescribed limit.
  • Other arrangements are possible, e.g. where the electrodes are centered on a hexagonal or a trigonal lattice.
  • passive matrix addressing arrays combine a very high cell density with a simple electronic driving and detection architectures and manufacturing methods.
  • the passive matrix scheme can be adapted for electronic circuitry and memory cells embedded in the same chip, or for devices where the memory cell part is separated from the electronic driver and detection circuitry. As shall be shown below, it is possible to achieve these advantages in a lateral cell matrix also, provided an appropriate device architecture and voltage protocol is used.
  • FIG. 13a and 13b An example of an architecture for lateral cell structures addressed by a passive matrix arrangement is shown in figures 13a and 13b.
  • the memory cells are formed in the spaces between a set of pillar electrodes arranged in a matrix. Every second electrode in each given column of electrodes is connected to a common conducting rail (a "column rail") embedded in the substrate underneath that column. In each column of electrodes, the remaining electrodes are connected to a set of parallel conducting rails (“row rails”) embedded in a higher stratum of the substrate and oriented perpendicular to the column rails as shown.
  • a layer of insulator ensures that short-circuits between the column and row rails is avoided and also provides distance between the memory cells and the embedded rails.
  • the comparative doubling of cell volume can be used in several ways to enhance overall device performance.
  • all row rails except one are maintained at potential zero, with the one remaining rail which represents the set of selected cells in the matrix, being kept at potential V.
  • each column rail is connected to a sense amplifier clamping the each column rail to zero potential.
  • each cell contiguous to the electrodes that connect to the selected row rail at potential V is subjected to the full switching field E, and the switching charge generated in those cells that experience polarization reversal is sensed by the sense amplifier connected to each column rail.
  • each memory device needs to be carefully designed with regards to physical dimensions, geometric shapes of electrodes, etc in order to obtain the proper electric field distributions for operating the devices.
  • the electric field strength required for switching the memory substance is very high, exceeding typical dielectric strength of many substances, including air.
  • sharp edges, points or asperities should be avoided, and the top of the electrodes should be embedded in a material of adequate dielectric strength (e.g. the memory substance itself) to avoid spurious arcing between the top of the electrodes selected for addressing a given memory cell.
  • an important attribute of the present invention is the separation of the processes that produce the substrate with conducting lines, electrodes and electronics on the one hand, and the processes for applying the memory substance in the form of an electret or ferroelectric on the other hand.
  • Beneficial aspects that can accrue from this separation include optimization of manufacturing flow (e.g. multiple production sites), and freedom from cross-contamination of production environments.
  • the choice of memory substance becomes much less restricted, permitting the use of both inorganic-based and organic-based memory substances in conjunction with aggressive processes such as implantation, high temperature anneal etc that might be involved in the manufacturing of the substrate with conductors, electrodes, electronics, etc.
  • Memory substances of relevance encompass an ever-widening range of materials, including several families of ceramic ferroelectrics as mentioned in the introduction, and polymeric ferroelectrics such as PVDF, P(VDF-TrFE), odd nylons, etc.
  • Several of these memory substances, in particular the ferroelectric polymers decompose or lose their functionality at temperatures well below those required for normal processing of silicon-based electronics, or are damaged during standard electrode-deposition processes required in manufacturing of top electrodes according to prior art ferroelectric memory devices, but this disadvantage can largely be obviated by relying on memory cells with lateral geometries, as disclosed hereinabove.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

Selon l'invention, dans un dispositif à mémoire permanente comprenant un substrat support et une pluralité de cellules de mémoire, chaque cellule de mémoire contient une matière de mémoire sous la forme d'une matière électriquement polarisable et présente une structure de type capacitif munie d'une paire d'électrodes en contact avec la matière de mémoire. Les paires d'électrodes sont disposées en réseau et la pluralité de cellules de mémoire est formée selon des combinaisons par paires d'électrodes de réseau adjacent, si bien que les cellules de mémoire sont organisées de la même façon en un réseau homologue. Chaque cellule de mémoire est délimitée dans la matière de mémoire occupant ou jouxtant un écartement entre les électrodes de paires disposées sur le substrat support, si bien que la matière de mémoire, lorsqu'elle est soumise à un champ électrique appliqué sur les électrodes de la paire, devient polarisée dans le sens d'un axe du champ électrique, ou réagit à l'application du champ électrique en modifiant le sens ou la valeur d'une polarisation déjà établie.
PCT/NO2006/000152 2005-04-29 2006-04-26 Dispositif à mémoire permanente WO2006118466A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NO20052128A NO20052128L (no) 2005-04-29 2005-04-29 Minneinnretning og fremgangsmater for drift av denne
NO20052128 2005-04-29

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WO2006118466A1 true WO2006118466A1 (fr) 2006-11-09

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002299572A (ja) * 2001-03-29 2002-10-11 Toshiba Corp 半導体装置およびその製造方法
WO2003046995A1 (fr) * 2001-11-28 2003-06-05 Thin Film Electronics Asa Appareil a adressage matriciel comprenant un ou plusieurs dispositifs memoire
WO2003081602A1 (fr) * 2002-03-25 2003-10-02 Thin Film Electronics Asa Dispositif de stockage de donnees volumetrique comportant une pluralite d'appareils memoire empiles a adressage matriciel

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002299572A (ja) * 2001-03-29 2002-10-11 Toshiba Corp 半導体装置およびその製造方法
WO2003046995A1 (fr) * 2001-11-28 2003-06-05 Thin Film Electronics Asa Appareil a adressage matriciel comprenant un ou plusieurs dispositifs memoire
WO2003081602A1 (fr) * 2002-03-25 2003-10-02 Thin Film Electronics Asa Dispositif de stockage de donnees volumetrique comportant une pluralite d'appareils memoire empiles a adressage matriciel

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Publication number Publication date
NO20052128D0 (no) 2005-04-29
NO20052128L (no) 2006-10-30

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