Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
  • G06F17/10—Complex mathematical operations
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/36—Circuit design at the analogue level
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
  • H03L2207/50—All digital phase-locked loop

Definitions

• the present invention relates to communication networks and, more particularly, to a method and apparatus for designing a Phase-Locked Loop (PLL).
• PLL Phase-Locked Loop
• Data communication networks may include various computers, servers, routers, switches, hubs, proxies, and other devices coupled to and configured to pass data to one another. These devices will be referred to herein as "network elements.” Data is communicated through the data communication network by passing data over an established circuit or by packetizing the data and routing the data packets between a series of network elements over the network.
• TDM Time Division Multiplexed
• packet networks There are two basic types of networks - Time Division Multiplexed (TDM) networks and packet networks. These two networks differ in how data are transmitted on the physical medium.
• TDM Time Division Multiplexed
• data belonging to different users are assigned different timeslots, otherwise called “circuits' or "channels" in a given time interval otherwise called a "frame".
• a user can only transmit in its assigned time slot in a frame that continuously repeats itself.
• the clocking or timing signal that generates the frames and timeslots on the physical medium has to be very accurate for transmissions to be successful.
• the network elements rely on accurate timing to determine which user data belong to which circuit, whereas in a packet network the packets are individually addressed in a manner that is able to be understood by the network elements.
• timing requirements of TDM networks are generally relatively stringent.
• timing is less important since each packet of data is self-contained and is able to specify to the network element its size and other associated parameters. Since timing is not as stringent on a packet network, the network elements on a packet network are generally not synchronized to a common timing source. Hence, packet networks are generally referred to as asynchronous networks.
• TDM networks are synchronous in nature. Consequently, the equipment connected to a TDM network has to be synchronized to it in some manner.
• a timing distribution network typically will link the TDM nodes to provide a synchronization signal that is traceable to a Primary Reference Source (PRS).
• PRS Primary Reference Source
• the network synchronization signal is derived from the PRS and distributed through a hierarchy of network nodes with lesser stratum clocks.
• An alternative timing solution is to maintain a distributed PRS architecture, where for example, each TDM node is timed from an accurate timing source, such as a PRS/Stratum 1 clock, Global Positioning System (GPS) based clock, or a standalone accurate clock (e.g., H Maser, Cesium, Rubidium, etc.).
• GPS Global Positioning System
• H Maser Cesium, Rubidium, etc.
• the particular timing requirements on a service interface depend on the services (Tl, El, T3, E3, etc.) carried over the network, which are typically specified in a
• packet-based networks such as Ethernet networks and Internet Protocol (IP) networks
• IP Internet Protocol
• service providers have sought to implement packet-based core networks intermediate existing TDM networks.
• the packet network must essentially behave as a transparent "link" in the end-to-end connection.
• the transparent inclusion of a packet network in an end-to-end path of a connection that carries circuit-switched time sensitive traffic is commonly referred to as "circuit emulation" on the packet network.
• the non-synchronous nature of the packet network and the packetizing and depacketizing processes used to format the data for transmission over the packet network all contribute to increased delay and delay variations in the transmission of packets, which makes transfers of synchronization between the TDM networks on either side of the packet core difficult. Additionally, while packet networks are able to carry traffic between the end TDM networks, they do not naturally carry accurate clock information due to their asynchronous nature. Thus, to enable TDM traffic to be carried over a packet network, it is necessary to have the end systems directly exchange clock information, so that the data ports on the network elements can be synchronized and to allow the different networks to be synchronized.
• a network element or a downstream terminal mode may use an adaptive timing technique to reconstruct the timing signal of the upstream TDM terminal. For example, where there are no reference clocks traceable to a PRS, a receiving TDM terminal node has to use an adaptive timing technique to reconstruct the timing signal of the transmitting TDM terminal.
• the TDM receiver derives an estimate of the transmitter clock from the received data stream. This is commonly done using a phase- locked loop (PLL) that slaves the receiver clock to a transmitter clock.
• PLL phase- locked loop
• the slave PLL is able to process transmitted clock samples encoded within the data stream, or process data arrival patterns, to generate timing signals for the receiver.
• the purpose of the slave PLL is to estimate and compensate for the frequency drift occurring between the oscillators of the transmitter clock and the receiver clock.
• Several adaptive timing techniques have been developed, including extracting clock information from arrival patterns over the network, observing the rate at which the buffers are being filled, and using encoded timing signals transmitted from the upstream terminal to the downstream terminal across the packet network.
• encoded timing signals timestamps
• U.S. Patent Application No. 10/076,415 entitled "Technique for Synchronizing Clocks in a Network", the content of which is hereby incorporated by reference.
• a PLL was developed that included a low-pass filter, however the PLL in that solution was not developed quantitatively, but rather was developed by experimental trials.
• a higher order PLL may be used at the slave clock.
• designing a PLL by experimental trials becomes increasingly difficult and cumbersome.
• a software program configured to assist in the design of a PLL given a set of performance specifications, (e.g., system damping factor, etc.) and component characteristics (such as VCO characteristic curve, digital-to-analog (DAC) v/ord size (in bits), etc.).
• a set of performance specifications e.g., system damping factor, etc.
• component characteristics such as VCO characteristic curve, digital-to-analog (DAC) v/ord size (in bits), etc.
• PLL design software is provided that is configured to enable initial component characteristics to be specified, enable design specifications of the PLL to be specified, and to compute the time constants for a loop filter that would be required to enable a PLL to meet the design specifications given the component characteristics.
• the performance or behavior characteristics of the PLL may then be computed for the PLL given the time constants and the initial set of components to determine whether the performance of the PLL would be considered satisfactory.
• the PLL design software may determine whether the PLL would be sufficiently stable if created using the particular selected components given the required design specifications.
• the PLL design software may provide guidance as to what component characteristics would improve performance of the PLL.
• the PLL design may be implemented in hardware to form a PLL.
• the PLL design software is particularly useful in designing timestamp-based PLLs for clock synchronization in a packet network.
• FIG. 1 is a functional block diagram of an example communication network over v/hich clock synchronization may take place using a PLL designed using the PLL design software according to an embodiment of the invention
• Fig. 2 is a functional block diagram of a PLL configured to use timestamps
• Fig. 3 is a graph illustrating the PLL input and output
• Fig. 4 is a graph illustrating the power spectrum of an output signal of a PLL
• Fig. 5 is a flow chart illustrating a process of synchronizing clocks on a network using timestamps
• Fig. 6 is a functional block diagram of a PLL implemented using a voltage controlled oscillator
• Fig. 7 is a graph illustrating the behavior of a phase detector in the PLL of Fig. 6;
• Fig. 8 is a graph illustrating the phase detector signals in both bits and radians
• Fig. 9 is a graph illustrating the phase detector characteristics over time
• Fig. 10 is a graph illustrating an ideal voltage controlled oscillator characteristic curve
• Fig. 11 is a functional block diagram illustrating a closed loop control model of the PLL of Fig. 6;
• Figs. 12a and 12b are magnitude and phase plots, respectively, of the frequency response of the 2 nd and 3 rd order PLLs that may be designed using the PLL design software according to an embodiment of the invention
• Fig. 13 is a functional block diagram of a PLL with error-DAC/VCO mapping functions shown in the discrete time domain
• Figs. 14a and 14b are flow charts of a dynamic mapping function process using, respectively, samples in non-overlapping windows and samples in overlapping windows;
• Fig. 15 is a flowchart illustrating a process of designing a PLL according to an embodiment of the invention.
• Fig. 16 is a functional block diagram of a computer system configured to run PLL design software configured according to an embodiment of the invention. Detailed Description
• Fig. 1 illustrates an example network 10 in which clock information 12 is carried across a packet network 14 from a master clock 16 to one or more slave clocks 18. As shown in Fig. 1, synchronization of the master and slave clocks is achieved over a packet (non TDM) portion of the network 14 by transmitting packets 12 containing clock state information from the master clock 16 to the slave clocks 18.
• packet non TDM
• a transmitter 16 When timestamps are used for clock synchronization, a transmitter 16 periodically sends explicit time indications, or timestamps, to a receiver 18 to enable the receiver to synchronize its local clock 22 to the transmitter's clock 20.
• Fig. 1 only shows a single receiver, the timestamp synchronization strategy also allows multiple receivers, for example in a broadcast or point-to-multipoint communication scenario, to synchronize their clocks to the transmitter.
• the transmitter clock includes an oscillator 30 and a pulse counter 32.
• the oscillator issues periodic pulses 34 that form the input to the pulse (timestamp) counter 32.
• the output of the counter 32 represents the transmitter clock signal 36, and is incremented by a fixed amount at each pulse. Samples of the transmitter clock signal are communicated to the receiver 18 as timestamps.
• the receiver clock 22 is formed as a Phase-Locked Loop (PLL) which uses the timestamps 12 (which form the PLL reference signal) to lock onto the transmitter clock 20.
• the PLL 22 has four main components: a phase detector 40, a loop filter 42, a local oscillator such as a Voltage Controlled Oscillator (VCO) or Current Controlled Oscillator (CCO) 44, and a timestamp counter 46.
• VCO Voltage Controlled Oscillator
• CCO Current Controlled Oscillator
• the phase detector 40 computes an error signal 50 as the difference between a reference signal 54 and the output signal of the PLL 56.
• the error signal 50 is passed on to the loop filter 42 which is responsible for eliminating possible jitter and noise in the input signal.
• the local oscillator such as the VCO 44, which typically has a center frequency, oscillates at a frequency which is determined by the output signal of the loop filter.
• Fig. 2 shows an example of a PLL configured to use a timestamps as an input.
• T(n) will be used to denote the time base (e.g., in clock ticks) of the transmitter and R(n) will be used to denote the time base of the receiver.
• R(n) will be used to denote the time base of the receiver.
• the timestamp difference between the nth and (w - l) th generated timestamp at the transmitter is defined as AT(n) - T(n) - T(n - 1) .
• AR(n) R(n) - R(n - 1) .
• the function of the PLL is to control the receiver clock frequency f s such that the error e goes to zero at which point the receiver frequency equals the transmitter frequency f s .
• the loop filter 42 in this PLL, is a simple low-pass filter.
• the PLL at the receiver therefore takes AT( ⁇ ) as its reference input and generates ARi ⁇ ) as its output (i.e., the controlled process).
• the two process variables AT in) and M( «) are illustrated in Fig. 3.
• To create a PLL it is necessary to select components that will provide the PLL with the desired characteristics and responsiveness.
• One way to do this is to select the components by iterative experimentation. For example, components may be selected, a loop filter designed, and the PLL may be tested to determine its responsiveness and stability characteristics.
• PLL design software is provided that is configured to automate the process of designing the PLL, given a set of performance specifications and component characteristics.
• R J (k) E[j(n + k)j(n)]
• AR(z) AT + j(z) (3)
• a suitable low pass filter may be designed given certain performance specifications of the PLL according to an embodiment of the invention.
• Fig. 5 illustrates a process used by the PLL to control the VCO to estimate the transmitter clock. The measurement/computational instants in the flowchart occur at the timestamp arrival instants at the receiver. Initially, the PLL at the receiver sets the initial digital loop filter parameters (100) and initializes variables (102). The PLL then waits for the first timestamp to arrive (104).
• the PLL When the first timestamp arrives it is loaded into the counter. From this point onwards, the PLL starts to operate in a closed-loop fashion.
• KXh K > 1 , where K is a downsampling parameter
• the difference AT ⁇ between this value T(n) and the value at the previous sampling instant T(n - Y) is determined.
• This error term is sent to the loop filter (112) whose output controls the frequency of the VCO.
• the output of the VCO in turn provides the clock frequency of the receiver and also drives the counter.
• Fig. 6 shows the basic components of a PLL architecture with a VCO.
• the phase detector 40 compares an arriving transmitter timestamp difference against the timestamp difference of the receiver clock.
• the output of the phase detector called the error, is a measure of the frequency difference between the two clocks.
• the error is then filtered by the loop filter 42.
• the signal u is converted to an analog signal using a digital- to-analog converter (DAC) 62.
• DAC digital- to-analog converter
• ZOH Zero-Order Hold
• the analog voltage is then amplified by an amplifier 64 before being applied to the VCO.
• the main function of the amplifier in this example, is to scale the input voltage to the VCO within the acceptable VCO voltage range.
• the control voltage on the VCO changes the frequency in a direction that reduces the difference between the input frequency and the local oscillator.
• the minimum frequency resolution of the VCO is dependent on the resolution (quantization step size) of the DAC. Higher resolution of the DAC provides finer frequency control of the VCO.
• the locked state the error between the local oscillator's output signal and the transmitter's signal is zero or remains a very small random quantity.
• a current-controlled oscillator (CCO) is used instead of the VCO.
• the output signal of the DAC is a controlled current source rather than a voltage source.
• the operating principle remains the same.
• phase detector To enable a PLL to be designed using an automated process such as a computer program, it is first necessary to develop control models for the phase detector, digital to analog converter, voltage controlled oscillator, and given some general structure of the loop filter, the PLL as a whole.
• the analysis will further provide design procedures for determining the parameters of the loop filter that will meet certain pre-specified design and performance requirements. Some design steps are provided so that those with limited knowledge of control systems can still determine the parameters of the PLL given only the performance specifications.
• the behavior of the phase detector is illustrated in Fig. 7. Assume that the timestamp generation period is constant, that is, ⁇ T(n) - AT and that there is no delay variation in the system. The phase detector will determine a phase error approximately every AT(n) (bit) interval.
• phase detector characteristic curve is shown in Fig. 9. As shown in Fig. 9, the phase detector gain is equal to the slope of its characteristic curve.
• the ranges of ⁇ e (t) are - ⁇ ⁇ ⁇ e (n) ⁇ ⁇ . This operation can be expressed as
• e ⁇ t K PD - ⁇ e ⁇ t) (7)
• the error signal output e(t) is then passed to the loop filter G LF (s) to be processed into the filtered error e ⁇ (t) .
• E(s) and & e (s) are the Laplace transforms of e(t) and ⁇ e (t) , respectively.
• DAC Digital to Analog Converter
• VCO Voltage Controlled Oscillator
• u(t) DAC output voltage (in volts)
• ⁇ V D ⁇ C DAC output voltage range (which is also the VCO input voltage range)
• E(s) DAC res where E(s) and U(s) are the Laplace transforms of ⁇ e(t) and u(t) , respectively.
• A I .
• the VCO oscillates at an angular frequency ⁇ vco (t) which is determined by the DAC output voltage u(t) .
• the angular frequency of the VCO ⁇ vco (t) is given by
• K vc0 is the VCO gain (in rad/sec-V).
• the operation of the PLL is complicated by the fact that it has to track the reference clock and simultaneously reject short term variations. From a functional point of view, the PLL should be able to operate to provide a very stable clock when synchronized to the external network, and should also be able to provide a stable clock when synchronization is lost (holdover mode). In holdover mode the feedback loop is open, and the circuit does not behave as a PLL.
• the gain of the VCO can be computed from the VCO data sheet, which is generally obtainable from the VCO supplier.
• the first requirement is the determination of the supply voltage(s) of the VCO (this can be determined from the data sheet).
• the VCO circuit may be able to be powered from a unipolar +5 V supply.
• U ly Let the VCO supply voltage be denoted by U ly .
• the VCO control signal ⁇ t) is usually limited to a range which is smaller than the supply voltage U supply .
• u mm and u max be the minimum and maximum value allowed for u(t) , respectively. With these, the VCO transfer characteristic curve may be described as shown in Fig. 10.
• the frequency axis of the VCO characteristics is sometimes expressed in Hertz instead of radians per second. In this case, the gain is obtained as
• the gain is calculated as
• f 0 is the VCO center frequency and ⁇ ppm is the VCO output frequency range in
• ⁇ re/ (s) the Laplace transform of ⁇ ref (t) .
• the closed-loop control model of the PLL is shown in Fig. 11.
• the order of the loop is equal to the number of perfect integrators within the loop structure. Since the VCO is modeled as a perfect integrator, the loop is at least of order 1. If the loop filter also contains one perfect integrator, then the loop is of order 2.
• the order of the loop can be shown to greatly influence the steady-state performance of the loop.
• the performance of the third-order PLL is compared with the conventional second-order PLL (with a lag-lead filter) as shown in Figs. 12a and 12b. As shown in Figs. 12a- 12b, an appropriately designed third-order PLL can exhibit much better performance than a second order
• a third order PLL may be more difficult to design than a second order PLL, however, where a trial and error approach is taken to PLL design.
• the transfer function for the PLL may be written as:
• the parameters from the above equations can easily be obtained from the supplier data sheets for the DAC and VCO.
• This enables the PLL software to compute the gain constant K of the PLL from available information once initial components have been selected.
• the only unknown component which is the loop filter, G 1 F (s) can then be designed to obtain the desired system steady- state behavior. Accordingly, these equations may be used in a computer program to enable a second order PLL to be designed given a set of performance specifications, (e.g., system damping factor, etc.) and component characteristics.
• a computer program may also be used to design a third-order PLL (that is, a PLL with a second-order loop filter), which may be used to obtain improved performance over the traditional second-order PLL (a PLL with a first-order loop filter).
• a third-order PLL that is, a PLL with a second-order loop filter
• Performance specifications may be considered to be constraints put on the system response characteristics, and may be stated in any number of ways.
• performance specifications take two forms: 1) frequency-domain specifications (i.e., pertinent quantities expressed as functions of frequency), and 2) time-domain specifications (in terms of time response).
• the desired system characteristics may be prescribed in either or both of the above forms. In general, they specify three important properties of dynamic systems: 1) the speed of response, 2) the relative stability of the system, and 3) the system accuracy or allowable error.
• a lag-lead filter also known as a proportional-integral (PI) filter
• PI proportional-integral
• ⁇ n and ⁇ are the natural frequency and damping factors, respectively, and are specified in terms of A ⁇ 01n , r, and x 2 as:
• the damping factor has an important influence on the dynamics of a PLL.
• ⁇ > 1 the poles are real; and when ⁇ ⁇ 1 , the poles are complex and conjugate.
• ⁇ ⁇
• the poles are repeated and real and the condition is called critical damping.
• ⁇ ⁇ 1 the response is underdamped and the poles are complex.
• the transient response of the closed-loop system is increasingly oscillatory as the poles approach the imaginary axis when ⁇ approaches zero.
• the above model can be directly applied to the PLL in the continuous-time domain.
• ⁇ nf (t) ⁇ - u(t) , (32) where u(t) is the unit step function. In the s-domain, this can be expressed as:
• phase step that is not the only type of change that may be applied to the PLL.
• a phase ramp i.e., frequency step
• a ⁇ applied at the input.
• ⁇ ref (t) A ⁇ - t , (35) which shows that the input phase is a ramp with slope ⁇ .
• this may be expressed as:
• the PLL may therefore be considered a digital PLL.
• the sampling of the phase error e(t) (and the computation of the filtered error ⁇ ( ⁇ ) occurs every ⁇ T bits assuming a delay variation free system.
• the period of ⁇ T bits is equivalent to a sampling period of
• At ATZf 0 , where f o is the nominal system frequency in bits per second.
• ⁇ T should be selected to be very high (e.g., ⁇ T>308800 bits for Tl rate) in order to minimize the loop tracking eiTor (due to thermal noise, input phase dynamics, and in particular, network delay variation).
• design by emulation involves designing a continuous time loop filter, digitizing the continuous time loop filter, and then using discrete analysis, simulations, or experimentation to verify the design.
• the gain of the DAC will then need to be computed. If the DAC register is specified as L bits long, giving the DAC a resolution of DAC res ⁇ 2 L , then the gain K ga ⁇ n
• the length L of the DAC should be input to the PLL design software.
• the natural frequency ⁇ n of the PLL will be determined by the PLL design software using the following equation:
• the PLL design software will then determine the parameters ⁇ x and ⁇ 2 of the loop filter from the following two equations:
• T 2 ⁇ - (43) ⁇ ..
• the PLL design software will proceed to determine the stability characteristics of the PLL. Knowing whether a system is absolutely stable or not is generally insufficient information for most control applications. Specifically, even if a system is stable, it is often desirable to know how close it is to being unstable. To do this, the PLL design software will need to be able to calculate the relative stability of the system. In addition to explaining how the relative stability may be determined, the following discussion will also help explain how the PLL design software may be used to design a third-order PLL.
• the gain margin (GM) which is a measure of relative stability, is defined as the magnitude of the reciprocal of the open-loop transfer function, evaluated at the frequency ⁇ c at which the phase angle is - 180° . This is,
• phase margin (PM), ⁇ which is a measure of relative stability, is defined as 180° plus the phase angle ⁇ ⁇ of the open-loop transfer function at unity gain. That is,
• phase margin is the amount by which the phase of G O[ (j ⁇ ) exceeds - 180° when I K OL G OI (j ⁇ )
• 1 .
• a positive phase margin is required for stability.
• the gain margin can be read directly from the Bode plot by measuring the vertical distance between the ⁇ K OL G OL (j ⁇ ) ⁇ curve and the I K 0L G 0L (j ⁇ )
• the gain margin can also be determined from the root locus with respect to K 01 by noting two values of K OL : at the point where the locus crosses the j ⁇ -axis, and at the nominal closed-loop poles.
• the GM is the ratio of these two values.
• Phase margin is the additional open-loop phase shift necessary to give 180° excess phase when the open-loop gain is unity. All PLLs have - 90° phase shift due to the ⁇ /s term, so excess phase is 90° even before any effect from the loop filter is considered. Whether a loop will oscillate when its gain exceeds unity at 180° is more easily seen from the Nyquist plot or from the root locus plot than from the Bode plot. However, in most cases it will not operate properly under these conditions, and the Bode plot is adequate.
• the PLL design software may use this process to design a second-order PLL.
• the characteristics of a third- order PLL may be more advantageous than those of a second-order PLL. Accordingly, in certain circumstances it may be advantageous to design a third-order PLL.
• the type 2 third-order loop has better noise suppression and faster lockup time.
• the order of the loop is defined as being equal to the number of poles in the open- loop transfer function. This is also the highest power of s in the denominator.
• the transfer function of the filter in a loop may be given as:
• the loop has two perfect integrators, one being the VCO and one being the phase integrator part of the filter, and three time constants.
• the closed-loop transfer function of the third-order loop may be expressed as:
• G PLL ⁇ s + K gO1n G 1S (s) T 1 T 3 S 3 + T 1 S 2 + K gam ⁇ 2 s + K gam
• the PLL design software will compute the following parameters r, , ⁇ 2 , and r 3 as follows:
• Fig. 12 shows the frequency response of second- and third-order PLLs that may be designed using this process. These plots are obtained from equations (24) and (48), respectively, for the second-order and third-order loops. From these figures it can be seen that the delay variation suppression characteristics of the third-order PLL are much better than that of the second-order PLL.
• the parameters used in the plots are: ⁇ - 0.707 ,
• ⁇ f vco 308.8 Hz
• K gam 2328.06
• ⁇ n 8.97598 rad/s
• ⁇ 2 0.157532 s
• T 1 69.76 s
• r 2 0.268964 ms
• T 3 0.0461469 ms.
• the invention is not limited to this particular example, which was rather provided to illustrates the performance differences between second and third order loops.
• At is the sampling interval for the system. Accordingly:
• the phase detector and the loop filter can be implemented in the digital domain with a sampling interval At .
• the PLL may be implemented in digital circuitry in a straightforward manner using known techniques.
• the frequency resolution f res of the VCO will be defined to be:
• a combined DAC-VCO model may be developed which can then be used to develop the error mapping function for the PLL. Specifically, assume that the
• the error mapping function maps a filtered error value ' e , which is a floating point number, to a corresponding DAC input value, which is a integer in the range [0,2 L - 1] .
• DAC VCO e [O, DAC res - 1] the DAC input DAC VCO
• the errors e(ri) from the phase detector are generated at this frequency / ⁇ r « f M , but, the receiver oscillator operates at the service frequency f s « f s .
• the loop parameters derived above are based on the sampling frequency / ⁇ 7 « / ⁇ , .
• the error v ⁇ ilues generated at the lower frequency f AT « f Ml have to be scaled to appropriate values so that they can applied to the receiver oscillator which operates at the service frequency
• DAC vco (f o ,t) will be used to denote the VCO control input at time t computed based on system parameters at the nominal frequency f 0 . Accordingly:
• DAC 0 ⁇ f 0 is the nominal DAC value corresponding to the nominal frequency f 0
• e " (/ o ,0 is the filtered error at time t computed based system frequency f 0 .
• DAC yco (f AT ,t) DAC o (f AT ) + e(f &r ,t) , (69) and the DACA 7 CO operations have been defined around the nominal DAC value DAC 0 (f 0 ) and frequency f o as
• DAC corr (f o ,t) is the DAC correction factor corresponding to the nominal frequency f 0 , at time t.
• DAC/VCO operations around the DAC value DAC 0 (A T ) and frequency / ⁇ r as:
• DAC VCO (U) ⁇ 7 1 • DAC vco (f AT ,t)
• DAC corr (U) ⁇ r • DAC C ⁇ rr (A ⁇ ,t) (7
• the error mapping function may be obtained as
• DAC yco (f o ,t) DAC 0 (Z 0 ) + lnt[AT - e (A ⁇ ,O] - (75)
• the above error mapping function is straightforward and very simple to implement as illustrated in Fig. 13.
• the DAC has a nominal value that affects the operating frequency of the oscillator. Ideally, the nominal DAC setting would produce a voltage that always caused the oscillator to produce the desired nominal frequency. During tracking of the reference frequency, any error encountered produces a DAC offset that, when added to the nominal DAC setting, minimizes the error (negative feedback control). In practice, the nominal DAC setting has to be determined and may have to be readjusted during operation to account for temperature changes and aging effects. In other situations, it may not be possible to accurately determine the exact nominal DAC value.
• Another advantage of adaptively determining the optimal nominal DAC setting is that it enables the DAC offset computed during operation to be as small as possible.
• the DAC offset needed to minimize the error is obtained, the error begins to get smaller and in turn, reduces the DAC offset, causing the error to grow again.
• the cycle will be long and the correction will be less accurate than when the DAC offset is small.
• Figs. 14a and 14b show the basic techniques to adaptively re-compute the optimal nominal DAC setting. Specifically, Fig. 14a shows a dynamic mapping function using samples in non-overlapping windows, and Fig. 14b shows the dynamic mapping function using samples in overlapping windows. Since these figures are self-explanatory, additional description of these figures has been omitted.
• Fig. 16 shows a process that may be implemented in the PLL design software to enable a second or third order PLL to be designed. Initially, when the software starts (200) the software will prompt the user to input component characteristics for an initial selected set of components (202). The user will also be prompted, at this stage, to input design specifications of the PLL to be designed (204). Inputting design specifications and selected components may occur simultaneously or in any desired order and the invention is not limited to the particular sequence shown in Fig. 15.
• the PLL design software will compute the time constants for a loop filter that would be required to enable the PLL top meet the design specifications given the selected components (206). These time constants may then be used to determine the PLL behavior characteristics, such as the stability of the system. (208). If the PLL behavior characteristics are satisfactory, the PLL design is complete (212). If not, the PLL design software may use the values of the time constants to help the user select different components that are more likely to produce a PLL with desirable behavior characteristics (214). For example, the PLL design software may indicate that the DAC does not have high enough resolution, or that a different VCO may work better given the desired PLL design specifications.
• Fig. 16 shows a computer system that may be used to implement the PLL design software according to an embodiment of the invention.
• the computer system may be a standard computer and the invention is not limited to any particular type of computer system.
• the computer 300 is connected to a display 302 for displaying results and one or more user input devices 304.
• the user input devices may be stand-alone devices such as a keyboard or mouse, or may be integrated into the display, such as where the display is touch or light sensitive.
• the invention is not limited to the particular types of display and user input devices to be used with the computer.
• the computer includes a display interface 306 and an input interface 308 to receive and transmit signals from the display and user input devices.
• the computer also includes a CPU 310 configured to implement control logic 312 so that the computer may perform the calculations described above to enable PLL design software 314 stored in memory 316 to be executed on the computer 300.
• a computer generally has many additional components that are not shown in this figure, as would be known to a person of ordinary skill in the art. The invention is not limited to the particular implementation shown in Fig. 16, but rather may be implemented on many differently configured computer platforms.
• a PLL may be implemented using discrete components, integrated circuitry, or using a combination of hardware and control logic implemented as a set of program instructions that are stored in a computer readable memory within the network element and executed on a microprocessor.
• programmable logic can be fixed temporarily or permanently in a tangible medium such as a read-only memory chip, a computer memory, a disk, or other storage medium.
• Programmable logic can also be fixed in a computer data signal embodied in a carrier wave, allowing the programmable logic to be transmitted over an interface such as a computer bus or communication network. All such embodiments are intended to fall within the scope of the present invention.

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• 2006
  • 2006-04-21 WO PCT/CA2006/000639 patent/WO2006113986A1/en not_active Application Discontinuation
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