EP1875609A4 - METHOD AND APPARATUS FOR DESIGNING PLL - Google Patents

METHOD AND APPARATUS FOR DESIGNING PLL

Info

Publication number
EP1875609A4
EP1875609A4 EP06741404A EP06741404A EP1875609A4 EP 1875609 A4 EP1875609 A4 EP 1875609A4 EP 06741404 A EP06741404 A EP 06741404A EP 06741404 A EP06741404 A EP 06741404A EP 1875609 A4 EP1875609 A4 EP 1875609A4
Authority
EP
European Patent Office
Prior art keywords
pll
designing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06741404A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP1875609A1 (en
Inventor
James Aweya
Delfin Montuno
Kent Felske
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ciena Luxembourg SARL
Original Assignee
Nortel Networks Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nortel Networks Ltd filed Critical Nortel Networks Ltd
Publication of EP1875609A1 publication Critical patent/EP1875609A1/en
Publication of EP1875609A4 publication Critical patent/EP1875609A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/50—All digital phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Data Mining & Analysis (AREA)
  • General Engineering & Computer Science (AREA)
  • Algebra (AREA)
  • Computational Mathematics (AREA)
  • Geometry (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Evolutionary Computation (AREA)
  • Pure & Applied Mathematics (AREA)
  • Databases & Information Systems (AREA)
  • Software Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
EP06741404A 2005-04-23 2006-04-21 METHOD AND APPARATUS FOR DESIGNING PLL Withdrawn EP1875609A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US67423205P 2005-04-23 2005-04-23
PCT/CA2006/000639 WO2006113986A1 (en) 2005-04-23 2006-04-21 Method and apparatus for designing a pll

Publications (2)

Publication Number Publication Date
EP1875609A1 EP1875609A1 (en) 2008-01-09
EP1875609A4 true EP1875609A4 (en) 2010-07-28

Family

ID=37214396

Family Applications (1)

Application Number Title Priority Date Filing Date
EP06741404A Withdrawn EP1875609A4 (en) 2005-04-23 2006-04-21 METHOD AND APPARATUS FOR DESIGNING PLL

Country Status (3)

Country Link
EP (1) EP1875609A4 (ko)
KR (1) KR20080017016A (ko)
WO (1) WO2006113986A1 (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101242419B1 (ko) 2009-07-20 2013-03-12 한국전자통신연구원 병렬처리 기반의 시각 동기화 장치

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5864248A (en) * 1995-11-20 1999-01-26 Nec Corporation Phase-locked loop circuit for reproducing clock signals synchronized with transmitter in receiver
EP0924862A2 (en) * 1997-12-19 1999-06-23 Nec Corporation PLL for reproducing standard clock from random time information
US6697445B1 (en) * 2001-05-24 2004-02-24 National Semiconductor Corporation Method and apparatus with enhanced jitter transfer characteristics in a phase-locked loop system

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6993106B1 (en) * 1999-08-11 2006-01-31 Broadcom Corporation Fast acquisition phase locked loop using a current DAC

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5864248A (en) * 1995-11-20 1999-01-26 Nec Corporation Phase-locked loop circuit for reproducing clock signals synchronized with transmitter in receiver
EP0924862A2 (en) * 1997-12-19 1999-06-23 Nec Corporation PLL for reproducing standard clock from random time information
US6697445B1 (en) * 2001-05-24 2004-02-24 National Semiconductor Corporation Method and apparatus with enhanced jitter transfer characteristics in a phase-locked loop system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2006113986A1 *

Also Published As

Publication number Publication date
WO2006113986A8 (en) 2008-05-02
KR20080017016A (ko) 2008-02-25
EP1875609A1 (en) 2008-01-09
WO2006113986A1 (en) 2006-11-02

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Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20071016

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR

DAX Request for extension of the european patent (deleted)
RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: NORTEL NETWORKS LIMITED

A4 Supplementary search report drawn up and despatched

Effective date: 20100629

RIC1 Information provided on ipc code assigned before grant

Ipc: H03L 7/093 20060101ALI20100623BHEP

Ipc: H03L 7/06 20060101AFI20061124BHEP

Ipc: G06F 17/50 20060101ALI20100623BHEP

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: CIENA LUXEMBOURG S.A.R.L.

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20110127