Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
  • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
  • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N9/00—Details of colour television systems
  • H04N9/79—Processing of colour television signals in connection with recording
  • H04N9/7921—Processing of colour television signals in connection with recording for more than one processing mode
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N5/00—Details of television systems
  • H04N5/76—Television signal recording
  • H04N5/78—Television signal recording using magnetic recording
  • H04N5/781—Television signal recording using magnetic recording on disks or drums
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N5/00—Details of television systems
  • H04N5/76—Television signal recording
  • H04N5/84—Television signal recording using optical recording
  • H04N5/85—Television signal recording using optical recording on discs or drums
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N9/00—Details of colour television systems
  • H04N9/79—Processing of colour television signals in connection with recording
  • H04N9/80—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback
  • H04N9/804—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback involving pulse code modulation of the colour picture signal components
  • H04N9/8042—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback involving pulse code modulation of the colour picture signal components involving data reduction

Definitions

• the present invention relates to a video output device, and in particular, a DVD (Digital Versatile Disk), an HDD.
• DVD Digital Versatile Disk
• the present invention relates to video output device technology that can be applied when playing back digital data such as video stored in (Hard Disk Drive).
• a conventional video output device shown in FIG. 5 has a read processing block 501 for reading digital data such as video recorded on a DVD, HDD, etc., and the read processing block 501 reads the digital data. Processing is performed in a decoding processing block 502 that decodes the compressed video data, a video output processing block 503 that outputs the decoded video, a reading processing block 501, a decoding processing block 502, and a video output processing block 503. And an external memory 504 for storing data to be stored.
• the video data is read by the read processing block 501, and the read video data is transferred to the decode processing block 502 to decode it.
• the decoded video signal is input to the video output processing block 503, and the decoded video signal is output from the video output processing block 503.
• Patent Document 1 Japanese Patent Laid-Open No. 2001-351332 (1st page, Fig. 1)
• the external memory 504 If the transfer capability is low, bus failure will occur, and in the worst case, the decoded video signal will not be output correctly. In order to avoid bus failure, the external memory 504 having a high transfer capability may be used. However, using the external memory 504 having a high transfer capability may lead to an increase in the cost of the video output device. It becomes.
• the present invention has been made in view of the above-described conventional problems.
• Read processing block, decode processing block, video output processing block power in the video output device Data transfer is performed by external memory and DMA transfer.
• the purpose is to provide a video output device that can alleviate bus failures that occur when the transfer capacity of the external memory is low and can output a correct video signal.
• the video output apparatus reads a digital data including video recorded on a recording medium, and reads the digital data including the video by the read processing block.
• the video output processing block includes: A plurality of video data stored in the external memory are DMA-transferred to an internal buffer having a predetermined capacity in the video output processing block, and image digital signal processing is performed on each video data, and these are synthesized.
• DMA transfer information indicating the type of video data to be transferred and the transfer amount obtained from the decode processing block and the video output processing block is acquired, and based on the acquired DMA transfer information, By changing the video output processing in the video output processing block, the bus failure of the DMA transfer with the external memory is alleviated.
• the video output processing block is based on the DMA transfer information indicating the type and transfer amount of each image data such as OSD, SPU, main video, thumbnail, etc. from the decoding processing block or the video output processing block.
• the video output device is the video output device according to claim 1, wherein the video output processing block is configured to perform DMA transfer of the video data from the external memory to the internal buffer.
• the output range power of each video data is obtained a period in which the video data overlaps each other, the display order and transparency of each video data are detected, and each video data is detected.
• the video data is determined not to be displayed as a monitor output display video when the video data is synthesized and then output and displayed based on the display order and transparency of the With respect to the video data, the DMA transfer from the external memory to the internal buffer is not performed, thereby reducing the failure of DMA transfer with the external memory. Than it is.
• the video output device is the video output device according to claim 1, wherein the video output processing block is configured to transmit the video data from the external memory to the internal memory.
• the display period and transparency of each video data are obtained from the output range of each video data by obtaining a period in which the video data overlap each other.
• the video data is synthesized and then output and displayed based on the display order and transparency of the video data, when it is determined that all the video data is displayed on the monitor,
• the amount of the internal buffer used for DMA transfer among the internal buffers of the predetermined capacity is increased!
• the video output device is the video output device according to claim 3, wherein the decoding processing block is selected based on a special reproduction state used in decoding in the block.
• the maximum DMA transfer time for the DMA transfer of video data to be used is calculated, and the video output processing block uses the internal buffer used for the DMA transfer in the video output processing according to the maximum DMA transfer time. It is characterized by reducing the DMA transfer bus failure with external memory by increasing the amount of data and increasing the amount of prefetched video data.
• the maximum DMA transfer time related to the DMA transfer of the video data used for the decoding is calculated from the special reproduction state used in the decoding in the decoding processing block, and based on this, the video output processing is calculated.
• the video output device is the video output device according to claim 3, wherein the decoding processing block relates to DMA transfer of video data used in the decoding based on the decoding format.
• the maximum DMA transfer time is calculated and the video output process is performed.
• the logical block is set to increase the amount of the internal buffer used for DMA transfer in the video output process according to the maximum DMA transfer time, and the video data to be read ahead is increased to increase the external data. It is characterized by alleviating bus failures in DMA transfer with memory.
• the maximum DMA transfer time related to DMA transfer of video data used in the decoding is calculated according to a decoding format such as MPEG1ZMPEG2ZMPEG4 in the decoding processing block, and based on this, the video output of the video output processing block is output
• a decoding format such as MPEG1ZMPEG2ZMPEG4 in the decoding processing block
• the video output device is the video output device according to claim 1, wherein the video output processing block includes a video format in processing performed by the decoding processing block, and the video output From the scaling ratio of each video data in the processing performed by the processing block, the maximum DMA transfer time for DMA transfer of the video data is calculated for the scaling process in the digital image signal processing. According to the maximum DMA transfer time, the output processing block increases the amount of the internal buffer used for DMA transfer when performing the enlargement / reduction processing in the image digital signal processing out of the predetermined capacity of the internal buffer. Reducing the DMA transfer bus failure with the external memory by setting and increasing the prefetched video data It is the Chi and Features.
• the video processing such as 4: 4: 4/4: 2: 2/4: 2: 0 in the processing performed by the decoding processing block, and the enlargement / reduction processing by the image digital signal processing in the video output processing block
• the maximum DMA transfer time related to the DMA transfer of the video data is calculated from the scaling rate of each video data in, and based on this, the amount of internal buffer used in the scaling process in the image digital signal processing is changed
• the video output device is the video output device according to claim 1, wherein the video output processing block is a video output format power progressive output. It is determined whether the output is interlaced, and in the case of the interlaced output, the number of executions of the DMA transfer of the video data from the external memory to the internal buffer and the internal buffer of the predetermined capacity are used for DMA transfer. By setting to reduce the amount of the internal buffer, the bus failure of the DMA transfer with the external memory is alleviated.
• interlace output the number of DMA transfer executions from the external memory of the video data to the internal buffer, and the internal By reducing the amount of buffers, it is possible to mitigate bus failures in DMA transfer with external memory.
• the video output device is the video output device according to claim 3, wherein when the capacity of the internal buffer is insufficient, the image digital signal processing block is enlarged or reduced.
• the number of taps of the digital filter of the processing that maximizes the number of taps of the digital filter is reduced, so that the main video data is transferred from the external memory to the internal buffer.
• the DMA transfer to the external memory is reduced, and in the video output processing, the amount of the buffer used for the DMA transfer is set to be reduced to reduce the DMA transfer failure with the external memory. To do.
• the video output device is the video output device according to claim 6, wherein when the capacity of the internal buffer is insufficient, the image digital signal processing block is enlarged or reduced.
• the number of taps of the digital filter of the processing that maximizes the number of taps of the digital filter is reduced, so that the main video data is transferred from the external memory to the internal buffer. Reducing the amount of buffer used for DMA transfer in the video output processing. It is characterized in that it is set so as to alleviate the failure of DMA transfer with the external memory.
• the image digital signal processing block is enlarged or reduced.
• the number of taps of the digital filter of the processing that maximizes the number of taps of the digital filter is reduced, so that the main video data is transferred from the external memory to the internal buffer.
• the DMA transfer to the external memory is reduced, and in the video output processing, the amount of the buffer used for the DMA transfer is set to be reduced to reduce the DMA transfer failure with the external memory. To do.
• the video output device is the video output device according to claim 3, wherein the DMA transfer allowable time of the video data is calculated from the set internal buffer amount used for the DMA transfer.
• the DMA transfer bus to the external memory is changed to a higher value. It is characterized by mitigating bankruptcies.
• the DMA transfer priority with the external memory can be alleviated by dynamically determining the DMA transfer priority based on the DMA transfer allowable time of the video data. Can do.
• the video output device is the video output device according to claim 6, wherein the DMA transfer allowable time of the video data is determined from the set internal buffer amount used for the DMA transfer.
• the DMA transfer bus to the external memory is changed to a higher value. It is characterized by mitigating bankruptcies.
• the DMA transfer priority with the external memory can be alleviated by dynamically determining the DMA transfer priority based on the DMA transfer allowable time of the video data.
• the video output device is the video output device according to claim 7, wherein the DMA transfer allowable time of the video data is determined from the set internal buffer amount used for the DMA transfer.
• the DMA transfer bus to the external memory is changed to a higher value. It is characterized by mitigating bankruptcies.
• the DMA transfer priority with the external memory can be alleviated by dynamically determining the DMA transfer priority based on the DMA transfer allowable time of the video data.
• the video output device is the video output device according to claim 8, wherein the DMA transfer allowable time of the video data is calculated from the set internal buffer amount used for the DMA transfer.
• the DMA transfer bus to the external memory is changed to a higher value. It is characterized by mitigating bankruptcies.
• the DMA transfer priority with the external memory can be alleviated by dynamically determining the DMA transfer priority based on the DMA transfer allowable time of the video data.
• the video output processing block when using the external memory 104 having a low transfer capability, the video output processing block is based on the information acquired from the decoding processing block 102 or the video output processing block 103.
• the DMA transfer bus failure of the external memory 104 by controlling the DMA transfer amount of each video data in 103, setting the internal buffer amount effective for the transfer of each video data, or assigning the DMA transfer priority
• the system can be constructed with high cost performance!
• FIG. 1 is a diagram showing a configuration of a video output apparatus according to Embodiment 1 of the present invention.
• FIG. 2 is a block diagram showing video output processing in the video output device according to the first embodiment.
• FIG. 3 is a diagram showing a flow of DMA transfer control processing in the video output device according to the first embodiment.
• FIG. 4 is a diagram showing a transfer rate of all video data between external buffers and internal buffers in the video output device according to the first embodiment.
• FIG. 5 is a diagram showing a configuration of a conventional video output device.
• N Proportional constant depending on transfer capacity of DMA controller and external memory 104
• the video output processing device according to the first embodiment of the present invention will be described below.
• the video output device includes a read processing block 101 for reading digital data such as video recorded on a DVD, an HDD, etc., and the read processing block 101.
• the decoding processing block 102 that decodes the compressed video data
• the video output processing block 103 that outputs the decoded video
• the reading processing block 101, the decoding processing block 102, and the video output processing block 103 perform processing.
• an external memory 104 for storing data to be stored.
• the video data is read by the read processing block 101, and the read video data is transferred to the decode processing block 102 for decoding.
• the decoded video data is input to the video output processing block 103, and a decoded video signal is output from the video output processing block 103.
• FIG. 2 is a diagram showing an internal configuration of the video output processing block 103 in the video output device according to the first embodiment.
• the external memory 104 stores video data such as main video data 202, thumbnail data 203, OSD (On Screen Display) data 204, SPU (Sub Picture Unit) data 205, and the like.
• the video output processing block 103 is composed of an internal buffer 206 and an image digital signal processing block 211.
• Each video data recorded in the external memory 104 is DMA-transferred to the internal buffer 206, and
• the thumbnail data 208, OSD data 209, and SPU data 210 transferred to the internal buffer 206 are added to the main video data 207 that has been subjected to each processing, and added to the image digital signal processing block 211 (212). ) Combine and output the combined video data.
• the digital filter of the processing that maximizes the number of taps of the digital filter among the enlargement / reduction processing, noise reduction processing, and IP conversion processing in the image digital signal processing block 211.
• the number of taps is set to X (X is an integer of 1 or more) taps so that the number of taps can be set variably, thereby adjusting the video data transfer amount used in the image digital signal processing block 211.
• FIG. 3 is a diagram showing a flow of DMA transfer control processing in the video output processing block 103 in the video output device according to the first embodiment.
• the flow of the DMA transfer control process is as follows: a (a is an integer equal to or greater than 1)
• the process should be designed to be performed once during the screen display period.
• the DMA transfer control process is performed during the period during which one screen is displayed. Is assumed to be controlled to call once.
• this DMA transfer control processing needs to be performed during a period when the DMA transfer amount is relatively small before a bus failure occurs.
• the DMA transfer control processing is performed once in a period for displaying a screen, and the information obtained from the decoding processing block 102 and the video output processing block 103 are used. Based on the obtained information, a DMA transfer time to the external memory 104 in the future for displaying a screen is predicted, the DMA transfer amount control of each video data in the video output processing block 103, and the transfer of each video data
• a DMA transfer time to the external memory 104 in the future for displaying a screen is predicted, the DMA transfer amount control of each video data in the video output processing block 103, and the transfer of each video data
• step S301 the transfer capacity of the external memory 104, the capacity of the internal buffer 206, the decoding format of the video such as MPEG1ZMPEG2ZMPEG4 from the decoding processing block 102, and 4: 4: 4/4: 2: Video formats such as 2/4: 2: 0 are acquired (step S301).
• the DMA transfer control process is performed once in a period for displaying a screen, and a vertical sync is detected a times in order to predict DMA in a period for displaying a screen in the future (step S3).
• the output range of each video data, the display order and transparency of each video when synthesizing each video data are acquired (step S 303).
• the higher the display order of the video data the more the image data is synthesized on the front of the screen and the transparency of the image data located on the front of the screen. If is not 0, the image data is combined so that the image data is transmitted and the image data of the next display order is displayed.
• step S304 It is determined whether the video data overlaps when the transparency is 0 and the display order is higher (step S304). If video data with a transparency of 0 and a higher display order overlaps, Since the video data that will be located at is not displayed, the DMA transfer of the non-displayed video data from the external memory 104 to the internal buffer 206 is stopped over the period for displaying a screen (step S 305). ).
• step S306 In order to predict the amount of DMA transfer of the main video data 207 from the external memory 104 to the internal buffer 206 in the period for displaying a screen in the future, whether the video output processing block 103 is interlaced or not.
• the video output format as to whether the output is progressive is acquired (step S306).
• Acquired video output format power It is determined whether the output is interlaced output or progressive output (step S307). If the video output format is progressive output, the execution rate of the image digital signal processing block 211 is set to progressive. Set the rate (step S308).
• the execution rate of the image digital signal processing block 211 is set to the interlaced rate (where the interlaced rate is 1Z2 of the progressive rate), and a screen for the future will be displayed.
• the video output processing block 103 displays the video special playback status such as fast-forward playback obtained from the decoding processing block 102.
• the obtained enlargement / reduction ratio of the image enlargement / reduction process in the image digital signal processing block 211 and the digital in the process executed at the forefront of the image enlargement / reduction process, the noise reduction process, and the IP conversion process are obtained.
• the number of filter taps x (x is an integer satisfying the relationship 1 ⁇ x ⁇ X) is acquired (step S310).
• video when the playback state is paused, the DMA transfer amount after one decoding process is predicted to be zero.
• the maximum DMA transfer time of video data in one line display period is the maximum DMA transfer time that the read processing block 101 and the decode processing block 102 output in one line display period, and the video output processing block 103. Based on how much transfer size is concentrated on the same line in DMA transfer from the external memory 104 to the internal buffer 206 in FIG.
• Maximum DMA transfer time of video data in 1 line display period (Maximum transfer size of main video data in 1 line display period + OSD data maximum transfer size in 1 line display period + Thumbnail in 1 line display period Maximum data transfer size + SPU data maximum transfer size during one line display period) XN + Read block and decode processing Maximum transfer time during one line display period for record data and decode data for which the block performs DMA transfer
• N is a proportional constant that depends on the transfer capability of the DMA controller and the external memory 104, and when the read block and the decode processing block execute DMA transfer, the recording data and the decode data respectively.
• the maximum transfer time for one line display period can be calculated according to the transfer capacity, reading speed, recording data error rate, decoding format, video format, special video playback status, etc. of the external memory 104. If it is difficult to calculate the transfer time depending on the information, or if it is difficult to obtain the information and the transfer time cannot be calculated, use the transfer time measured in advance.
• the amount of the internal buffer used for DMA transfer is calculated from the maximum transfer size of the video data in the one-line display period, and the amount of the internal buffer used is calculated in step S301. (Step S312), and if the amount of the internal buffer used for the above DMA transfer exceeds the capacity of the internal buffer 206 acquired in Step S301, the image By reducing the number of digital filter taps in the digital signal processing block 211 in which the number of taps of the digital filter is the maximum among the video enlargement / reduction processing, noise reduction processing, and IP conversion processing (step S313), DMA is performed. The amount of transfer can reduce the DMA transfer amount according to the capacity of the internal buffer 206.
• a DMA transfer request from the external memory 104 to the internal buffer 206 depends on the size of the internal buffer 207 to 210 of each data.
• the maximum allowable transfer time from when the data is made until the data in the internal buffer 206 is output is calculated (step S314).
• the calculated maximum allowable transfer time is compared with the maximum DMA transfer time of the video data (step S315). If the maximum DMA transfer time of the video data exceeds the maximum allowable transfer time, the DMA Set to increase the amount of internal buffer used for transfer, and change the transfer priority so that the maximum allowable transfer time for one line display period increases in order from the processing of one line display period with the shortest maximum allowable transfer time. (Step S316). If the maximum DMA transfer time does not exceed the maximum allowable transfer time in step S315, then the DMA transfer control process is terminated.
• FIG. 4 is a diagram showing a transfer rate between the external memory 104 and the internal buffer 206 of the video output processing block 103 in the video output processing device according to the first embodiment.
• the vertical axis represents the transfer rate of all video data between the external memory 104 and the internal buffer 206
• the horizontal axis represents time
• the transfer rate 401 for one line display period the transfer rate 401 for one line display period
• the transfer capacity of the external memory 104 or the capacity of the internal buffer 206 is used for this processing. If this is not sufficient, the processing in the video output processing block 103 is changed, for example, the number of digital filter taps in the image digital signal processing block 211 is reduced. Thereby, the transfer amount of each video data can be reduced, the average transfer rate 402 can be improved as indicated by the arrow 404, and the video output processing can be realized.
• the transfer capacity of the external memory 104 or the capacity of the internal buffer 206 is sufficient to execute the processing in the video output processing block 103.
• the DMA temporarily When the transfer is concentrated and the video is disturbed, the time for the DMA transfer from the external memory 104 to the internal buffer 206 and the transfer time are predicted in advance for a screen from the information that can be acquired, and the internal buffer 206 As shown in the arrow 405, the transfer rate is increased during the period T1 by changing the DMA transfer priority to the external buffer 206 and the external memory 104 power. Video output processing can be realized while preventing disturbance.
• the video output device including the reading processing block 101, the decoding processing block 102, the video output processing block 103, and the external memory 104.
• each video data stored in the external memory is DMA-transferred to an internal buffer in the video output processing block, and then image digital signal processing is performed on each video data to synthesize them.
• DMA transfer information indicating the type and transfer amount of each image data to be transferred is acquired, and based on the acquired DMA transfer information, the video output processing block By changing the video output process, the bus failure of DMA transfer with external memory was alleviated.
• DMA transfer processing is performed for each line display period.
• the present invention is not limited to this, and DMA transfer is performed for each predetermined period according to the type of video. The present invention is effective even when processing is performed.
• the present invention is effective when applied to a system that reproduces video data recorded on a DVD, HDD, or the like and uses an external memory with low transfer capability. It can also be used for external recording media.

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• 2006
  • 2006-02-23 WO PCT/JP2006/303326 patent/WO2006090802A2/fr active Application Filing

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