WO2006090802A2

WO2006090802A2 - Video output device

Info

Publication number: WO2006090802A2
Application number: PCT/JP2006/303326
Authority: WO
Inventors: Satoshi Kinoshita
Original assignee: Matsushita Electric Industrial Co., Ltd.
Priority date: 2005-02-25
Filing date: 2006-02-23
Publication date: 2006-08-31

Description

Specification

Video output device

Technical field

TECHNICAL FIELD [0001] The present invention relates to a video output device, and in particular, a DVD (Digital Versatile Disk), an HDD.

The present invention relates to video output device technology that can be applied when playing back digital data such as video stored in (Hard Disk Drive).

Background art

A conventional video output device shown in FIG. 5 has a read processing block 501 for reading digital data such as video recorded on a DVD, HDD, etc., and the read processing block 501 reads the digital data. Processing is performed in a decoding processing block 502 that decodes the compressed video data, a video output processing block 503 that outputs the decoded video, a reading processing block 501, a decoding processing block 502, and a video output processing block 503. And an external memory 504 for storing data to be stored.

[0003] When playing back video data recorded on a DVD, HDD, etc., the video data is read by the read processing block 501, and the read video data is transferred to the decode processing block 502 to decode it. The decoded video signal is input to the video output processing block 503, and the decoded video signal is output from the video output processing block 503.

[0004] When the read processing block 501, the decode processing block 502, and the video output processing block 503 transfer data by DMA transfer with the external memory 504, respectively, if the transfer capability of the external memory 504 is low, There is a problem that the bus is broken and the decoded video signal is not output correctly in the worst case.

[0005] Here, using the external memory 504 having a high transfer capability increases the cost of the video output device. Therefore, using the external memory 504 with low transfer capability, how to avoid bus failure, the read processing block 501, the decode processing block 502, and the video output processing block 503 are each transferred to the external memory 504 by DMA transfer. The ability to execute this is important as an effort to reduce the cost of video output devices. [0006] In order to avoid a bus failure using the external memory 504 having a low transfer capability, between each block of the read processing block 501, the decode processing block 502, and the video output processing block 503, and each processing block 501 It is necessary to perform DMA transfer control within ~ 503.

[0007] Here, a method has been proposed in which the read processing block 501 communicates with the decode processing block 502 to remedy bad bus bandwidth (Patent Document 1).

Patent Document 1: Japanese Patent Laid-Open No. 2001-351332 (1st page, Fig. 1)

Disclosure of the invention

Problems to be solved by the invention

[0008] As described above, when the reading processing block 501, the decoding processing block 502, and the video output processing block 503 transfer data with the external memory 504 by DMA transfer, respectively, the external memory 504 If the transfer capability is low, bus failure will occur, and in the worst case, the decoded video signal will not be output correctly. In order to avoid bus failure, the external memory 504 having a high transfer capability may be used. However, using the external memory 504 having a high transfer capability may lead to an increase in the cost of the video output device. It becomes.

[0009] The present invention has been made in view of the above-described conventional problems. Read processing block, decode processing block, video output processing block power in the video output device Data transfer is performed by external memory and DMA transfer. In some cases, the purpose is to provide a video output device that can alleviate bus failures that occur when the transfer capacity of the external memory is low and can output a correct video signal.

Means for solving the problem

In order to solve the above-described problem, the video output apparatus according to claim 1 of the present invention reads a digital data including video recorded on a recording medium, and reads the digital data including the video by the read processing block. A decoding processing block for decoding the compressed video data, a video output processing block for outputting the video decoded by the decoding processing block, a reading processing block, the decoding processing block, and the video output processing block. In the video output device including an external memory for storing video data to be used for processing, the video output processing block includes: A plurality of video data stored in the external memory are DMA-transferred to an internal buffer having a predetermined capacity in the video output processing block, and image digital signal processing is performed on each video data, and these are synthesized. When outputting, DMA transfer information indicating the type of video data to be transferred and the transfer amount obtained from the decode processing block and the video output processing block is acquired, and based on the acquired DMA transfer information, By changing the video output processing in the video output processing block, the bus failure of the DMA transfer with the external memory is alleviated.

[0011] Thus, the video output processing block is based on the DMA transfer information indicating the type and transfer amount of each image data such as OSD, SPU, main video, thumbnail, etc. from the decoding processing block or the video output processing block. By changing the video output processing at, the bus failure of DMA transfer with external memory can be alleviated.

[0012] The video output device according to claim 2 of the present invention is the video output device according to claim 1, wherein the video output processing block is configured to perform DMA transfer of the video data from the external memory to the internal buffer. In a certain period before executing the transfer, the output range power of each video data is obtained a period in which the video data overlaps each other, the display order and transparency of each video data are detected, and each video data is detected. When the video data is determined not to be displayed as a monitor output display video when the video data is synthesized and then output and displayed based on the display order and transparency of the With respect to the video data, the DMA transfer from the external memory to the internal buffer is not performed, thereby reducing the failure of DMA transfer with the external memory. Than it is.

[0013] With this, it is possible to predict in advance the overlap of the video data that occurs when the video data is synthesized, determine the video data that is not output from the monitor among the overlapped videos, and for the video data, the external memory By not performing the DMA transfer from to the internal buffer, it is possible to alleviate the bus failure of the DMA transfer with the external memory without changing the video output data result.

[0014] The video output device according to claim 3 of the present invention is the video output device according to claim 1, wherein the video output processing block is configured to transmit the video data from the external memory to the internal memory. In a certain period before executing the DMA transfer to the unit buffer, the display period and transparency of each video data are obtained from the output range of each video data by obtaining a period in which the video data overlap each other. When the video data is synthesized and then output and displayed based on the display order and transparency of the video data, when it is determined that all the video data is displayed on the monitor, In the video output process that displays each video data during the period when each video data overlaps, the amount of the internal buffer used for DMA transfer among the internal buffers of the predetermined capacity is increased! By setting the video data to be prefetched and increasing the video data to be prefetched, the bus failure of the DMA transfer with the external memory is alleviated.

[0015] With this, when it is determined in advance that the overlap of the video data generated when the video data is synthesized and it is determined that all the video data is displayed on the monitor, the internal buffer used in the video output process is used. By increasing the amount of data, the bus failure of the DMA transfer with the external memory can be alleviated.

[0016] The video output device according to claim 4 of the present invention is the video output device according to claim 3, wherein the decoding processing block is selected based on a special reproduction state used in decoding in the block. The maximum DMA transfer time for the DMA transfer of video data to be used is calculated, and the video output processing block uses the internal buffer used for the DMA transfer in the video output processing according to the maximum DMA transfer time. It is characterized by reducing the DMA transfer bus failure with external memory by increasing the amount of data and increasing the amount of prefetched video data.

Accordingly, the maximum DMA transfer time related to the DMA transfer of the video data used for the decoding is calculated from the special reproduction state used in the decoding in the decoding processing block, and based on this, the video output processing is calculated. By increasing the amount of internal buffer used in the video output processing of the block and increasing the prefetched video data, it is possible to alleviate DMA transfer bus failures with external memory.

[0018] The video output device according to claim 5 of the present invention is the video output device according to claim 3, wherein the decoding processing block relates to DMA transfer of video data used in the decoding based on the decoding format. The maximum DMA transfer time is calculated and the video output process is performed. The logical block is set to increase the amount of the internal buffer used for DMA transfer in the video output process according to the maximum DMA transfer time, and the video data to be read ahead is increased to increase the external data. It is characterized by alleviating bus failures in DMA transfer with memory.

[0019] Thus, the maximum DMA transfer time related to DMA transfer of video data used in the decoding is calculated according to a decoding format such as MPEG1ZMPEG2ZMPEG4 in the decoding processing block, and based on this, the video output of the video output processing block is output By increasing the amount of internal buffer used for processing and increasing the prefetched video data, it is possible to alleviate the bus failure of DMA transfer with external memory.

[0020] The video output device according to claim 6 of the present invention is the video output device according to claim 1, wherein the video output processing block includes a video format in processing performed by the decoding processing block, and the video output From the scaling ratio of each video data in the processing performed by the processing block, the maximum DMA transfer time for DMA transfer of the video data is calculated for the scaling process in the digital image signal processing. According to the maximum DMA transfer time, the output processing block increases the amount of the internal buffer used for DMA transfer when performing the enlargement / reduction processing in the image digital signal processing out of the predetermined capacity of the internal buffer. Reducing the DMA transfer bus failure with the external memory by setting and increasing the prefetched video data It is the Chi and Features.

[0021] With this, the video processing such as 4: 4: 4/4: 2: 2/4: 2: 0 in the processing performed by the decoding processing block, and the enlargement / reduction processing by the image digital signal processing in the video output processing block The maximum DMA transfer time related to the DMA transfer of the video data is calculated from the scaling rate of each video data in, and based on this, the amount of internal buffer used in the scaling process in the image digital signal processing is changed However, by increasing the prefetched video data, it is possible to alleviate the bus failure of DMA transfer with external memory.

[0022] The video output device according to claim 7 of the present invention is the video output device according to claim 1, wherein the video output processing block is a video output format power progressive output. It is determined whether the output is interlaced, and in the case of the interlaced output, the number of executions of the DMA transfer of the video data from the external memory to the internal buffer and the internal buffer of the predetermined capacity are used for DMA transfer. By setting to reduce the amount of the internal buffer, the bus failure of the DMA transfer with the external memory is alleviated.

[0023] This determines whether the video output format is progressive interlace output, which is progressive output. In the case of interlace output, the number of DMA transfer executions from the external memory of the video data to the internal buffer, and the internal By reducing the amount of buffers, it is possible to mitigate bus failures in DMA transfer with external memory.

[0024] The video output device according to claim 8 of the present invention is the video output device according to claim 3, wherein when the capacity of the internal buffer is insufficient, the image digital signal processing block is enlarged or reduced. Among the processing, noise reduction processing, and IP conversion processing, the number of taps of the digital filter of the processing that maximizes the number of taps of the digital filter is reduced, so that the main video data is transferred from the external memory to the internal buffer. The DMA transfer to the external memory is reduced, and in the video output processing, the amount of the buffer used for the DMA transfer is set to be reduced to reduce the DMA transfer failure with the external memory. To do.

[0025] Thereby, when the amount of the internal buffer is insufficient, the number of taps of the digital filter is maximized among the main video enlargement / reduction processing, noise reduction processing, and IP conversion processing in the image digital signal processing block. By reducing the number of taps of the processing digital filter and limiting the amount of internal buffer to be used, the monitor output data will be somewhat degraded, but the DMA transfer bus failure with the external memory can be alleviated. .

[0026] The video output device according to claim 9 of the present invention is the video output device according to claim 6, wherein when the capacity of the internal buffer is insufficient, the image digital signal processing block is enlarged or reduced. Among the processing, noise reduction processing, and IP conversion processing, the number of taps of the digital filter of the processing that maximizes the number of taps of the digital filter is reduced, so that the main video data is transferred from the external memory to the internal buffer. Reducing the amount of buffer used for DMA transfer in the video output processing. It is characterized in that it is set so as to alleviate the failure of DMA transfer with the external memory.

[0027] Thereby, when the amount of the internal buffer is insufficient, the number of taps of the digital filter is maximized among the main video enlargement / reduction processing, noise reduction processing, and IP conversion processing in the image digital signal processing block. By reducing the number of taps of the processing digital filter and limiting the amount of internal buffer to be used, the monitor output data will be somewhat degraded, but the DMA transfer bus failure with the external memory can be alleviated. .

[0028] In the video output device according to claim 10 of the present invention, in the video output device according to claim 7, when the capacity of the internal buffer is insufficient, the image digital signal processing block is enlarged or reduced. Among the processing, noise reduction processing, and IP conversion processing, the number of taps of the digital filter of the processing that maximizes the number of taps of the digital filter is reduced, so that the main video data is transferred from the external memory to the internal buffer. The DMA transfer to the external memory is reduced, and in the video output processing, the amount of the buffer used for the DMA transfer is set to be reduced to reduce the DMA transfer failure with the external memory. To do.

[0029] Thereby, when the amount of the internal buffer is insufficient, the number of taps of the digital filter is maximized among the enlargement / reduction processing, noise reduction processing, and IP conversion processing of the main video in the image digital signal processing block. By reducing the number of taps of the processing digital filter and limiting the amount of internal buffer to be used, the monitor output data will be somewhat degraded, but the DMA transfer bus failure with the external memory can be alleviated. .

[0030] The video output device according to claim 11 of the present invention is the video output device according to claim 3, wherein the DMA transfer allowable time of the video data is calculated from the set internal buffer amount used for the DMA transfer. By calculating and changing the DMA transfer priority from the external memory to the internal buffer in order from the processing in which the DMA transfer allowable time of the video data is short, the DMA transfer bus to the external memory is changed to a higher value. It is characterized by mitigating bankruptcies.

[0031] With this, the DMA transfer priority with the external memory can be alleviated by dynamically determining the DMA transfer priority based on the DMA transfer allowable time of the video data. Can do.

[0032] The video output device according to claim 12 of the present invention is the video output device according to claim 6, wherein the DMA transfer allowable time of the video data is determined from the set internal buffer amount used for the DMA transfer. By calculating and changing the DMA transfer priority from the external memory to the internal buffer in order from the processing in which the DMA transfer allowable time of the video data is short, the DMA transfer bus to the external memory is changed to a higher value. It is characterized by mitigating bankruptcies.

[0033] Thus, the DMA transfer priority with the external memory can be alleviated by dynamically determining the DMA transfer priority based on the DMA transfer allowable time of the video data.

[0034] The video output device according to claim 13 of the present invention is the video output device according to claim 7, wherein the DMA transfer allowable time of the video data is determined from the set internal buffer amount used for the DMA transfer. By calculating and changing the DMA transfer priority from the external memory to the internal buffer in order from the processing in which the DMA transfer allowable time of the video data is short, the DMA transfer bus to the external memory is changed to a higher value. It is characterized by mitigating bankruptcies.

[0035] Thereby, the DMA transfer priority with the external memory can be alleviated by dynamically determining the DMA transfer priority based on the DMA transfer allowable time of the video data.

[0036] The video output device according to claim 14 of the present invention is the video output device according to claim 8, wherein the DMA transfer allowable time of the video data is calculated from the set internal buffer amount used for the DMA transfer. By calculating and changing the DMA transfer priority from the external memory to the internal buffer in order from the processing in which the DMA transfer allowable time of the video data is short, the DMA transfer bus to the external memory is changed to a higher value. It is characterized by mitigating bankruptcies.

[0037] Thus, the DMA transfer priority with the external memory can be alleviated by dynamically determining the DMA transfer priority based on the DMA transfer allowable time of the video data. The invention's effect

[0038] According to the video output processing device according to the present invention, when using the external memory 104 having a low transfer capability, the video output processing block is based on the information acquired from the decoding processing block 102 or the video output processing block 103. The DMA transfer bus failure of the external memory 104 by controlling the DMA transfer amount of each video data in 103, setting the internal buffer amount effective for the transfer of each video data, or assigning the DMA transfer priority The system can be constructed with high cost performance!

Brief Description of Drawings

FIG. 1 is a diagram showing a configuration of a video output apparatus according to Embodiment 1 of the present invention.

FIG. 2 is a block diagram showing video output processing in the video output device according to the first embodiment.

FIG. 3 is a diagram showing a flow of DMA transfer control processing in the video output device according to the first embodiment.

[FIG. 4] FIG. 4 is a diagram showing a transfer rate of all video data between external buffers and internal buffers in the video output device according to the first embodiment.

FIG. 5 is a diagram showing a configuration of a conventional video output device.

Explanation of symbols

[0040] a: positive integer

X, X: Number of digital filter taps

N: Proportional constant depending on transfer capacity of DMA controller and external memory 104

101 Read processing block

102 Decoding processing block

103 Video output processing block

104 External memory

202 Main video data

203 Thumbnail data

204 OSD data

205 SPU data 206 Internal buffer

207 Main video data

208 Thumbnail data

209 OSD data

210 SPU data

211 Image digital signal processing block

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)

The video output processing device according to the first embodiment of the present invention will be described below.

The video output device according to the first embodiment shown in FIG. 1 includes a read processing block 101 for reading digital data such as video recorded on a DVD, an HDD, etc., and the read processing block 101. The decoding processing block 102 that decodes the compressed video data, the video output processing block 103 that outputs the decoded video, the reading processing block 101, the decoding processing block 102, and the video output processing block 103 perform processing. And an external memory 104 for storing data to be stored.

[0042] When playing back video data recorded on a DVD, HDD, etc., the video data is read by the read processing block 101, and the read video data is transferred to the decode processing block 102 for decoding. The decoded video data is input to the video output processing block 103, and a decoded video signal is output from the video output processing block 103.

[0043] Here, when the read processing block 101, the decode processing block 102, and the video output processing block 103 perform data transfer with the external memory 104 by DMA transfer, if the transfer capability of the external memory 104 is low, the bus This causes a failure, and in the worst case, the decoded video signal is not output correctly!

On the other hand, using the external memory 104 having a high transfer capability leads to an increase in the cost of the video output device. Therefore, using the external memory 104 with low transfer capability, Whether the read processing block 101, the decode processing block 102, and the video output processing block 103 can execute DMA transfer with the external memory 104, respectively, by avoiding bus failure, as an effort to reduce the cost of the video output device. It becomes important.

In this way, in order to avoid bus failure using the external memory 104 having a low transfer capability, between the blocks of the read processing block 101, the decode processing block 102, and the video output processing block 103, and each It is necessary to perform DMA transfer control within processing blocks 101-103.

FIG. 2 is a diagram showing an internal configuration of the video output processing block 103 in the video output device according to the first embodiment.

The external memory 104 stores video data such as main video data 202, thumbnail data 203, OSD (On Screen Display) data 204, SPU (Sub Picture Unit) data 205, and the like.

[0047] The video output processing block 103 is composed of an internal buffer 206 and an image digital signal processing block 211. Each video data recorded in the external memory 104 is DMA-transferred to the internal buffer 206, and For the main video data 207, in the image digital signal processing block 211, enlargement / reduction processing for changing the output size, noise reduction processing for reducing noise, and IP conversion processing for converting an interlaced image into a progressive image, The thumbnail data 208, OSD data 209, and SPU data 210 transferred to the internal buffer 206 are added to the main video data 207 that has been subjected to each processing, and added to the image digital signal processing block 211 (212). ) Combine and output the combined video data.

[0048] In addition, among the video output processing, the digital filter of the processing that maximizes the number of taps of the digital filter among the enlargement / reduction processing, noise reduction processing, and IP conversion processing in the image digital signal processing block 211. The number of taps is set to X (X is an integer of 1 or more) taps so that the number of taps can be set variably, thereby adjusting the video data transfer amount used in the image digital signal processing block 211.

In addition, the video output processing block 103 controls the transfer timing for prefetching the main video data 207 according to the size of the internal buffer 206. FIG. 3 is a diagram showing a flow of DMA transfer control processing in the video output processing block 103 in the video output device according to the first embodiment.

The flow of the DMA transfer control process is as follows: a (a is an integer equal to or greater than 1) The process should be designed to be performed once during the screen display period. Here, the DMA transfer control process is performed during the period during which one screen is displayed. Is assumed to be controlled to call once.

[0051] Here, this DMA transfer control processing needs to be performed during a period when the DMA transfer amount is relatively small before a bus failure occurs.

[0052] In the first embodiment, the DMA transfer control processing is performed once in a period for displaying a screen, and the information obtained from the decoding processing block 102 and the video output processing block 103 are used. Based on the obtained information, a DMA transfer time to the external memory 104 in the future for displaying a screen is predicted, the DMA transfer amount control of each video data in the video output processing block 103, and the transfer of each video data By effectively setting the capacity of the internal buffer 206 and assigning DMA transfer priority, it is possible to alleviate the DMA transfer bus failure with the external memory 104 and build a system with high cost performance. Can do.

Hereinafter, the flow of the DMA transfer control process shown in FIG. 3 will be described in detail.

In the flow of FIG. 3, first, the transfer capacity of the external memory 104, the capacity of the internal buffer 206, the decoding format of the video such as MPEG1ZMPEG2ZMPEG4 from the decoding processing block 102, and 4: 4: 4/4: 2: Video formats such as 2/4: 2: 0 are acquired (step S301).

[0054] However, information that is invariant during stream decoding does not necessarily need to be acquired for each DMA transfer control process.

[0055] The DMA transfer control process is performed once in a period for displaying a screen, and a vertical sync is detected a times in order to predict DMA in a period for displaying a screen in the future (step S3).

02).

[0056] In the future, in order to predict the DMA transfer amount during the display period of a screen, the output range of each video data, the display order and transparency of each video when synthesizing each video data are acquired (step S 303). [0057] When combining multiple image data such as OSD, SPU, main video, thumbnail, etc., the higher the display order of the video data, the more the image data is synthesized on the front of the screen and the transparency of the image data located on the front of the screen. If is not 0, the image data is combined so that the image data is transmitted and the image data of the next display order is displayed.

[0058] It is determined whether the video data overlaps when the transparency is 0 and the display order is higher (step S304). If video data with a transparency of 0 and a higher display order overlaps, Since the video data that will be located at is not displayed, the DMA transfer of the non-displayed video data from the external memory 104 to the internal buffer 206 is stopped over the period for displaying a screen (step S 305). ).

[0059] In order to predict the amount of DMA transfer of the main video data 207 from the external memory 104 to the internal buffer 206 in the period for displaying a screen in the future, whether the video output processing block 103 is interlaced or not. The video output format as to whether the output is progressive is acquired (step S306).

[0060] Acquired video output format power It is determined whether the output is interlaced output or progressive output (step S307). If the video output format is progressive output, the execution rate of the image digital signal processing block 211 is set to progressive. Set the rate (step S308).

[0061] If the video output format is interlaced output, the execution rate of the image digital signal processing block 211 is set to the interlaced rate (where the interlaced rate is 1Z2 of the progressive rate), and a screen for the future will be displayed. The DMA transfer from the external memory 104 to the internal buffer 206, which is unnecessary for the interlace rate during the period, is stopped (step S309).

[0062] In the future, in order to predict the DMA transfer amount during the period for displaying a screen, the video output processing block 103 displays the video special playback status such as fast-forward playback obtained from the decoding processing block 102. The obtained enlargement / reduction ratio of the image enlargement / reduction process in the image digital signal processing block 211 and the digital in the process executed at the forefront of the image enlargement / reduction process, the noise reduction process, and the IP conversion process are obtained. The number of filter taps x (x is an integer satisfying the relationship 1 ≤ x ≤ X) is acquired (step S310). Here, for example, video In particular, when the playback state is paused, the DMA transfer amount after one decoding process is predicted to be zero.

[0063] Information acquired as described above, transfer capability of external memory 104, decoding format, video format, output range of video data, display order and transparency during composition of video data, video output format, video From the special playback status, video scaling ratio, and the number of digital filter taps in the first stage of the video scaling processing, noise reduction processing, and IP conversion processing, the video data for one line display period Calculate the maximum DMA transfer time (step S311).

Here, the maximum DMA transfer time of video data in one line display period is the maximum DMA transfer time that the read processing block 101 and the decode processing block 102 output in one line display period, and the video output processing block 103. Based on how much transfer size is concentrated on the same line in DMA transfer from the external memory 104 to the internal buffer 206 in FIG.

[0065] Maximum DMA transfer time of video data in 1 line display period = (Maximum transfer size of main video data in 1 line display period + OSD data maximum transfer size in 1 line display period + Thumbnail in 1 line display period Maximum data transfer size + SPU data maximum transfer size during one line display period) XN + Read block and decode processing Maximum transfer time during one line display period for record data and decode data for which the block performs DMA transfer

[0066] Here, N is a proportional constant that depends on the transfer capability of the DMA controller and the external memory 104, and when the read block and the decode processing block execute DMA transfer, the recording data and the decode data respectively. The maximum transfer time for one line display period can be calculated according to the transfer capacity, reading speed, recording data error rate, decoding format, video format, special video playback status, etc. of the external memory 104. If it is difficult to calculate the transfer time depending on the information, or if it is difficult to obtain the information and the transfer time cannot be calculated, use the transfer time measured in advance.

[0067] Next, the amount of the internal buffer used for DMA transfer is calculated from the maximum transfer size of the video data in the one-line display period, and the amount of the internal buffer used is calculated in step S301. (Step S312), and if the amount of the internal buffer used for the above DMA transfer exceeds the capacity of the internal buffer 206 acquired in Step S301, the image By reducing the number of digital filter taps in the digital signal processing block 211 in which the number of taps of the digital filter is the maximum among the video enlargement / reduction processing, noise reduction processing, and IP conversion processing (step S313), DMA is performed. The amount of transfer can reduce the DMA transfer amount according to the capacity of the internal buffer 206.

[0068] By performing the control in steps S305, S309, and S313, the average allowable transfer time (transfer rate) with the outer memory 104 can be improved.

[0069] When the amount of the internal buffer used for the DMA transfer is less than or equal to the capacity of the internal buffer 206, a DMA transfer request from the external memory 104 to the internal buffer 206 depends on the size of the internal buffer 207 to 210 of each data. The maximum allowable transfer time from when the data is made until the data in the internal buffer 206 is output is calculated (step S314).

[0070] The calculated maximum allowable transfer time is compared with the maximum DMA transfer time of the video data (step S315). If the maximum DMA transfer time of the video data exceeds the maximum allowable transfer time, the DMA Set to increase the amount of internal buffer used for transfer, and change the transfer priority so that the maximum allowable transfer time for one line display period increases in order from the processing of one line display period with the shortest maximum allowable transfer time. (Step S316). If the maximum DMA transfer time does not exceed the maximum allowable transfer time in step S315, then the DMA transfer control process is terminated.

FIG. 4 is a diagram showing a transfer rate between the external memory 104 and the internal buffer 206 of the video output processing block 103 in the video output processing device according to the first embodiment.

[0072] In FIG. 4, the vertical axis represents the transfer rate of all video data between the external memory 104 and the internal buffer 206, the horizontal axis represents time, the transfer rate 401 for one line display period, and the average transfer rate Beat 402!

[0073] As shown in FIG. 4, for example, when video data overlaps the same line, DMA transfers from the external memory 104 to the internal buffer 206 are concentrated in the period T1 in the figure! / If this happens, transfer all video data between the external memory 104 and the internal buffer 206. The rate temporarily drops to 401a as indicated by arrow 403.

In contrast, in the first embodiment, when the processing in the video output processing block 103 is executed as described above, the transfer capacity of the external memory 104 or the capacity of the internal buffer 206 is used for this processing. If this is not sufficient, the processing in the video output processing block 103 is changed, for example, the number of digital filter taps in the image digital signal processing block 211 is reduced. Thereby, the transfer amount of each video data can be reduced, the average transfer rate 402 can be improved as indicated by the arrow 404, and the video output processing can be realized.

[0075] In addition, the transfer capacity of the external memory 104 or the capacity of the internal buffer 206 is sufficient to execute the processing in the video output processing block 103. As shown by 403 in the figure, the DMA temporarily When the transfer is concentrated and the video is disturbed, the time for the DMA transfer from the external memory 104 to the internal buffer 206 and the transfer time are predicted in advance for a screen from the information that can be acquired, and the internal buffer 206 As shown in the arrow 405, the transfer rate is increased during the period T1 by changing the DMA transfer priority to the external buffer 206 and the external memory 104 power. Video output processing can be realized while preventing disturbance.

As described above, according to the video output device of the first embodiment, the video output device including the reading processing block 101, the decoding processing block 102, the video output processing block 103, and the external memory 104. In the video output processing block power, each video data stored in the external memory is DMA-transferred to an internal buffer in the video output processing block, and then image digital signal processing is performed on each video data to synthesize them. From the decode processing block and the video output processing block to be output, DMA transfer information indicating the type and transfer amount of each image data to be transferred is acquired, and based on the acquired DMA transfer information, the video output processing block By changing the video output process, the bus failure of DMA transfer with external memory was alleviated. By appropriately controlling the DMA transfer amount of each video data in the video output processing block 103 and assigning an effective capacity of the internal buffer 206 to each video data and assigning DMA transfer priority according to the information, Relieve DMA transfer bus failure with memory 104 The effect that a system with high performance can be constructed is obtained.

In the first embodiment, an example in which DMA transfer processing is performed for each line display period has been described. However, the present invention is not limited to this, and DMA transfer is performed for each predetermined period according to the type of video. The present invention is effective even when processing is performed.

Industrial applicability

The present invention is effective when applied to a system that reproduces video data recorded on a DVD, HDD, or the like and uses an external memory with low transfer capability. It can also be used for external recording media.

Claims

The scope of the claims

[1] A reading processing block for reading digital data including video recorded on a recording medium;

A decoding processing block for decoding the compressed video data read by the reading processing block;

A video output processing block for outputting the video decoded by the decoding processing block;

In a video output device comprising an external memory for storing video data used in the processing in the reading processing block, the decoding processing block, and the video output processing block,

The video output processing block includes:

A plurality of video data stored in the external memory is DMA-transferred to an internal buffer having a predetermined capacity in the video output processing block, image digital signal processing is performed on each video data, and these are combined and output. In this case, DMA transfer information indicating the type of video data to be transferred and the transfer amount obtained from the decode processing block and the video output processing block is acquired, and the video is based on the acquired DMA transfer information. By changing the video output processing in the output processing block, the bus failure of the DMA transfer with the external memory is alleviated.

A video output device characterized by that.

[2] In the video output device according to claim 1,

The video output processing block includes:

In a certain period before the DMA transfer of the video data from the external memory to the internal buffer, a period in which the video data overlap each other is determined from the output range of the video data, The display order and transparency of the data are detected, and after the video data are synthesized based on the display order and transparency of the video data, it is determined that the video is not displayed as a monitor output display video when output and displayed. When there is video data, the video data before the synthesis is not subjected to DMA transfer from the external memory to the internal buffer. Alleviate transfer bus failures,

A video output device characterized by that.

[3] The video output device according to claim 1,

The video output processing block includes:

In a certain period before the DMA transfer of the video data from the external memory to the internal buffer, a period in which the video data overlap each other is determined from the output range of the video data, When the display order and transparency of the data are detected, and after the video data are synthesized based on the display order and transparency of each video data, when all the video data are output and displayed, If it is determined, in the video output process for displaying the video data during a period in which the video data overlaps, a setting is made to increase the amount of the internal buffer used for DMA transfer in the internal buffer of the predetermined capacity. By increasing the video data to be pre-read, the bus failure of DMA transfer with the external memory is alleviated,

A video output device characterized by that.

[4] The video output device according to claim 3,

The decoding processing block is

The maximum DMA transfer time related to the DMA transfer of the video data used in the decoding is calculated from the special reproduction state used in the decoding in the block, and the video output processing block determines the video according to the maximum DMA transfer time. In the output processing, it is set to increase the amount of the internal buffer used for DMA transfer, and by increasing the pre-read video data, the DMA transfer bus failure with the external memory is alleviated.

A video output device characterized by that.

[5] The video output device according to claim 3,

The decoding processing block is

From the decoding format, calculate the maximum DMA transfer time for DMA transfer of video data used in the decoding,

The video output processing block has its video output processing according to the maximum DMA transfer time. In practice, the amount of the internal buffer used for DMA transfer is set to be increased, and the video data to be prefetched is increased to alleviate the bus failure of the DMA transfer with the external memory.

A video output device characterized by that.

[6] The video output device according to claim 1,

The video output processing block includes:

From the video format in the processing performed by the decoding processing block and the scaling ratio of each video data in the processing performed by the video output processing block, the DMA transfer of the video data used in the scaling processing in the image digital signal processing Calculate the maximum DMA transfer time,

According to the maximum DMA transfer time, the video output processing block increases the amount of the internal buffer used for DMA transfer when performing enlargement / reduction processing in the image digital signal processing among the internal buffers of the predetermined capacity! To reduce the bus failure of DMA transfer with the external memory by increasing the video data to be pre-read,

A video output device characterized by that.

[7] The video output device according to claim 1,

The video output processing block determines whether the video output format is a force interlace output which is a progressive output,

In the case of the interlaced output, the number of executions of the DMA transfer of the video data from the external memory to the internal buffer and the amount of the internal buffer used for the DMA transfer among the internal buffers of the predetermined capacity are set to be reduced. By reducing the bus failure of the DMA transfer with the external memory,

A video output device characterized by that.

[8] In the video output device according to claim 3,

When the capacity of the internal buffer is insufficient, the number of taps of the digital filter in the processing that maximizes the number of taps of the digital filter among the enlargement / reduction processing, noise reduction processing, and IP conversion processing in the image digital signal processing block is reduced. By letting DMA transfer of the main video data from the external memory to the internal buffer is reduced, and the video output processing is set so as to reduce the amount of the internal buffer used for DMA transfer. Alleviate transfer bus failures,

A video output device characterized by that.

[9] The video output device according to claim 6,

When the capacity of the internal buffer is insufficient, the number of taps of the digital filter in the processing that maximizes the number of taps of the digital filter among the enlargement / reduction processing, noise reduction processing, and IP conversion processing in the image digital signal processing block is reduced. By reducing the DMA transfer of the main video data from the external memory to the internal buffer, the video output processing is set so as to reduce the amount of the internal buffer used for the DMA transfer. Relieve DMA transfer bus failure with external memory,

A video output device characterized by that.

[10] The video output device according to claim 7,

A video output device characterized by that.

[11] In the video output device according to claim 3,

The DMA transfer allowable time of the video data is calculated from the set internal buffer amount used for the DMA transfer,

The DMA transfer allowable time of the video data is shortened. In order from the processing, the DMA transfer priority from the external memory to the internal buffer is changed to a higher value to reduce the DMA transfer bus failure with the external memory. Let

A video output device characterized by that.

[12] The video output device according to claim 6, The DMA transfer allowable time of the video data is calculated from the set internal buffer amount used for the DMA transfer,

A video output device characterized by that.

[13] The video output device according to claim 7,

A video output device characterized by that.

[14] The video output device according to claim 8,

A video output device characterized by that.