WO2006085373A1 - Non-volatile semiconductor memory and semiconductor device - Google Patents

Non-volatile semiconductor memory and semiconductor device Download PDF

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Publication number
WO2006085373A1
WO2006085373A1 PCT/JP2005/002006 JP2005002006W WO2006085373A1 WO 2006085373 A1 WO2006085373 A1 WO 2006085373A1 JP 2005002006 W JP2005002006 W JP 2005002006W WO 2006085373 A1 WO2006085373 A1 WO 2006085373A1
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plurality
region
gate
non
control circuit
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PCT/JP2005/002006
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French (fr)
Japanese (ja)
Inventor
Takashi Yamaki
Jiro Ishikawa
Toshihiro Tanaka
Akira Kato
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Renesas Technology Corp.
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • G11C16/102External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure
    • G11C16/3454Arrangements for verifying correct programming or for detecting overprogrammed cells

Abstract

A non-volatile semiconductor memory (20) includes a plurality of non-volatile memory cells (1) having a threshold voltage which is increased by electron injection into a charge accumulation region and lowered by hot hole injection into the charge accumulation region. The non-volatile semiconductor memory (20) further includes control circuits (25, 36) capable of repeating the process for applying high voltage pulses for hot hole injection to a plurality of non-volatile memory cells selected as hot hole injection objects while shifting the timing by some of the cells until a desired threshold voltage is obtained. The control circuit can select non-overlap or partial overlap of the high voltage pulses for which the timing is shifted. If the non-overlap is selected firstly, it is possible to minimize the peak value of the current consumption accompanying the application of the high voltage pulse. When overlap mode is selected later, the peak value of the current consumption is not increased so much but it is possible to reduce the entire processing time required for lowering the threshold voltage.

Description

Specification

Nonvolatile semiconductor memory and a semiconductor device

Technical field

[0001] The present invention relates to a semiconductor device equipped with it adopted the nonvolatile semiconductor memory and a method of injecting Hottoho Le in the charge accumulation region to lower the threshold voltage of the nonvolatile memory cell, and applied to, for example, a flash memory It relates to an effective technology Te.

BACKGROUND

[0002] As a method of performing electron injection to the charge storage area of ​​the nonvolatile memory cell (for example that referred to as writing) and release or neutralizing (e.g. referred to erase), electrons using a tunnel current under the entire surface of the gate electrode a method according to the performing F- N tunneling current out of a method by hot carriers. The former is necessary to be higher operating voltage of the writing operation and erasing, since it is possible to reduce the operating current, the number of memory cells to be write operation or erase operation is large, non-volatile multi, it is used in sexual memory. The latter can reduce the operating voltage of the write and erase, and its operation because it can be performed at high speed, relatively small instrument height speed operation requires a memory cell to be a write operation or erase operation multi-!, it is used in a non-volatile memory.

[0003] For example, in cross-nitride film and a memory gate that is insulated and has formed a MONOS (Metal Oxide Nitride Oxide Semiconductor) type of nonvolatile memory Riseru on the channel-forming region, the erasing by hot-carrier system, in one forming a Kochikara high electric field to either et memory gate source 'drain electrode end, the source-drain electrode force of the one also flow a current to the substrate. This Yotsute, said at one of the source 'drain electrode end near occur ionizing collisions, electrons, hole pairs are generated. Holes having sufficient energy exceeds Potensha Le barrier gate Sani 匕膜 of generated holes becomes hot holes are injected into Naitora id film. When the hot holes are injected into the nitride film, there already injected, and acts to neutralize Ru electrons, this threshold voltage of Yotsute memory cell is changed to the low !, square direction . The hot hole injection erase due to the shall flow a current to the source 'drain region into a channel forming region in one ヽ. It must flow a large current as a whole As the number of nonvolatile memory cells as a unit of erase, a large power supply circuit or the step-up circuit of the current capacity is required.

[0004] General techniques to shift the write timing for each memory cell of the write target in order to reduce the peak value of the Patent Document 1, the current consumption is described. In the Patent Document 2 is described a technique of performing hot hole injection erase operation of the memory cell.

[0005] Patent Document 1: JP 2002-109894 JP

Patent Document 2: International Publication No. 02Z19342 pamphlet

Disclosure of the Invention

Problems that the Invention is to you'll solve

[0006] The present inventors have studied the nonvolatile semiconductor memory described in Patent Document 1. Nonvolatile memory described in Patent Document 1 is subject each word line of the first write operation, since the object 1 in the erase operation is block unit including a plurality of word lines, at the write operation in a number of memory cells to be write target, the number of memory cells to be erased in an erase operation, it can be considered that there are more memory cells to be erased. A current flowing in a channel formation region of the memory cell when the performed by Hottoho Lumpur injected erase operation, and to current flow in a channel formation region of the memory cell in order to perform hot electron injection Te you, the write operation when compared, the amount of current required in the erasing operation, be greater than the amount of current required to have you in the writing operation becomes bright et force.

[0007] On the other hand, the non-volatile memory described in Patent Document 2, in accordance with some of the memory cells to be erased target during the erase operation, a constant I a change in rate of rise of the voltage applied to Ueru region the amount of current flowing in the channel-shaped formation region of the memory cell of the force erased are examined to spoon Nitsu, consider is Te, Do, it became bright et force.

[0008] Based on the above consideration, the present inventors have to divide the block, which is an external force addressable erase unit further, the erasing in sector units in which the memory cells connected to one word line as a unit It was investigated method to reduce the maximum erase current by. In short, it is shifted an erase pulse of a high voltage applied to the one source over scan 'drain region in sectors. While only, that there is a problem that only erase processing time correspondingly to shift the application of the erase pulse becomes longer revealed by the present inventors. [0009] An object of the present invention, a nonvolatile semiconductor memory that can be minimized to increase the processing time as a whole even if the injection of hot holes by shifting the application timing of the high voltage pulses to the non-volatile memory cell It is to provide.

[0010] The above and other objects and novel features of the present invention will be described and accompanying drawings force become apparent herein.

Means for Solving the Problems

[0011] as follows explains briefly the outline of a typical invention among the inventions disclosed in the present application.

[0012] [1] A typical one of the non-volatile semiconductor memory according to the present invention, the threshold voltage is high by injecting electrons against the charge storage region, the threshold voltage by injecting Hottoho Le for the charge storage region comprising a plurality of nonvolatile memory cells (1) to be low, the high-voltage pulse for hot hole injection at different timings by its part the selected plurality of nonvolatile memory cells as an implantation target hot hole has applied to process can be repeated a plurality of times until the threshold voltage of Nozomu Tokoro a control circuit (25, 36), the control circuit, Nono a plurality of high voltage pulse shifted the timing the choice is whether or partially overlapping with burlap are possible.

[0013] As the overlap if a plurality of high voltage pulses and non-overlap can be the peak value of the current consumption due to the application of high voltage pulses to the minimum, if a plurality of high-voltage pulses with overlapping the degree of! /, the overall processing time to lower the threshold voltage with a peak value increases the current consumption is reduced according to increase.

[0014] One of the source-drain current hot holes flowing to the end of contributing force the current generation of non-volatile memory cell becomes smaller as the hot holes are injected into the charge storage region. Focusing on this characteristic, if the process is repeated to apply a high voltage pulse of the hot hole injection for a plurality of times until the desired threshold voltage, flows to the one of the source 'drain end of the post as compared with the first current is reduced. Thus, initially favors suppression of current peaks to a high-voltage pulse and non-overlap because a large current flows to one of a source 'drain terminals. Because people with is summer small current force S flowing through the one of the source and drain ends after, favors shortened during the time who the high voltage pulse was partially overlap process, just because otherwise the current nor peak becomes excessive.

[0015] From the above, it is possible to minimize the increase in the processing time as a whole even if the injection of Hottoho Le shifting the application timing of a high voltage pulse to the nonvolatile memory cell.

[0016] As one specific form of the present invention, the control circuit can select the degree of partial overlap of the high-voltage pulse. In high-voltage pulse application process towards the rear of the current flowing to one of the source-drain terminal becomes small, it may benefit from a longer pulse applying time than more first is desired, to be compatible with such requirements Become.

[0017] Specific another one form of the present invention, the control circuit, non-overlapping application of high voltage pulses shifted timing earlier in hot hole injection to be repeated a plurality of times and then, and partially overlaps the application of high voltage pulses different timings in hot hole injection towards after repeated a plurality of times. It is suitable when employing the control method focusing on the nature of the control circuit.

[0018] Specific another one form of the present invention, the control circuit, when lowering the threshold voltage of the nonvolatile memory cell, it suited to the channel region mosquito ゝ et storage region of the nonvolatile memory cell field while forming, injecting hot holes in the accumulation area (6) that occur in one of the source and drain electrode (3) end.

[0019] [2] Typical single semiconductor device according to the present invention (60) includes a non-volatile semiconductor memory (20), said nonvolatile semiconductor memory is the source 'drain regions (3, 4) an array (21) of the non-volatile memory cells (1) each having a dielectric charge storage region (6) and the memory gate region (8) on top of the sandwiched Chiyane Le forming region (2), said nonvolatile memory one source over scan cells 'first wiring drain region (3) is coupled with (SL), the other sources of non-volatile memory cells' second wiring drain region (4) is bonded (BL) When the third wiring memory gate region of the nonvolatile memory cells are coupled with (MG), performs control to increase the threshold voltage by injecting electrons into the charge storage region of the nonvolatile memory cell, the charge control circuit for performing control by injecting hot holes into the storage area to lower the threshold voltage (25, 36) Wherein the control circuit is desired a process for applying a high voltage pulse for hot hole injection at different timings by a portion to the hot hole injection of multiple selected as the target non-volatile main Moriseru a is possible to repeat a plurality of times until the threshold voltage, the selected or a plurality of high voltage pulse shifted the timing and non-overlap and be Luke or partially overlapping possible it is.

[0020] the same manner, the said control circuit, it is preferable to employ a selectable configuration the degree of partial overlap of the high-voltage pulse. In addition, the said control circuit, the application of high voltage pulses different timings in hot hole injection for the first person who is repeated divided Ke multiple times and non-overlap, for the later repeated a plurality of times it is preferable to employ a configuration that partially overlaps the application of high voltage pulses different timings in hot hole injection.

[0021] As one specific form of the present invention, the control circuit, when lowering the threshold value voltage of the nonvolatile memory cell, the counter force ゝ U electric field in the storage region from the channel region of the non-volatile memory cell in forming state, injecting hot holes into the storage region generated in one of the source and drain electrodes end.

[0022] In this case, it said array a plurality of nonvolatile memory cells matrix arrangement, a plurality of nonvolatile memory cells arranged in a matrix is ​​to share the first wiring (SL) row by row, Retsutan position in the second shared wiring (BL), and share the third wiring multiline units (MG), the control circuit includes a first high voltage pulse to the third wiring selected (-5V) was applied, the selected third to the first wiring connected to a plurality of nonvolatile memory cells sharing the wiring at different timings between the first wiring mutual second high voltage pulse (5V) it may be adopted a structure for applying a.

[0023] At this time, the control circuit, counter to form a plurality of selection signals for selecting a plurality of first wiring according to the nonvolatile main Moriseru multiline sharing the third wiring multiple performing a circuit (50), wherein a plurality of counter control circuit for controlling the timing of change of the selection signal and (51), said counter circuit, a shift operation in synchronization with the change of the shift clock (SCLK) has a storage stage (50A- 50D) in series, the output of said plurality of storage units is a pre SL plurality of selection signals,

The counter control circuit, said stage of supplying a pulse counter circuit (EPLS) a pulse generating circuit that generates (56), the pulse width selection circuit to select available-the width of the pulses generated by the pulse generating circuit and (55), wherein the shift quantity selection circuit by the period selection of the shift clock to vary a shift amount of said pulse (58), Ru can be configured to have. Pulse width and the overlapping amount of the high-voltage pulse is variably by a relatively simple configuration.

[0024] As a further specific form of the present invention, the nonvolatile memory cell is selected via the insulating film on the channel forming region of the source 'side of the drain region of the second wiring is connected to the gate region (10) is formed, having a split-gate structure in which the memory gate region and the select gate region is isolated. At this time, the gate breakdown voltage as viewed from the select gate region is better to be lower than the gate breakdown voltage as viewed from the memory gate region. Thus split gate structure, the one against the source scan upon injection of electrons or hot holes to the charge accumulation region 'high voltage indicia force on the drain end!] To be the other of the source of the select gate region side' channel to the drain end from ヽ high voltage, such is applied through an area, This is because it is not necessary to make a selection gate region side and the high breakdown voltage. Thus, when reading the information stored in the nonvolatile memory cell also selecting gate region side force, it is easy size Kusuru transconductance of the select gate region side (gm).

[0025] As a further specific form of the present invention, the further comprises a non-volatile semiconductor memory access system Gosuru controller (61), a gate breakdown voltage as viewed from the select gate region is a gate constituting said controller may one same der the gate breakdown voltage of the field effect transistor of the insulated.

Effect of the invention

[0026] as follows briefly describes the effects obtained by the typical ones of the inventions disclosed in the present application.

[0027] That is, it is possible to minimize the increase in the processing time as a whole even if the injection of Hottoho Lumpur shifting the application timing of a high voltage pulse to the nonvolatile memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIG. 1 is a block diagram illustrating the configuration of a flash memory.

FIG. 2 is a longitudinal sectional view many electronic vertical cross-sectional views of the split gate type nonvolatile memory cell in the charge storage region is illustrated as a state of being accumulated.

A [3] longitudinal sectional view illustrating a longitudinal sectional structure of the nonvolatile memory cell as the state number was less summer of trapped electrons in the charge storage region with respect to FIG.

[Figure 4] to inject more hot holes gradually to the nonvolatile memory cell in the state where electrons are injected as in Figure 2, a characteristic diagram showing the relationship between time and the erase current when having der Ru.

[5] erase willing relationship between the time and the erasing current at the start of the erased from the state threshold voltage of the nonvolatile memory cell has decreased somewhat lower (state electrons stored in the charge storage region is small) it is a characteristic diagram showing the.

6 is a circuit diagram showing a detailed example of a memory array and writing erasing decoder.

7 is a logic circuit diagram showing a specific example of selecting the timing control circuit (TCNT).

8 is a timing chart showing waveforms of the selection signals CountO- count3 in case that is one period of the pulse width PW1 shift clock SCLK erase pulse EPLS.

9 is a timing chart showing waveforms of the selection signals CountO- count3 in cases that are the four cycles of the erase pulse the pulse width PW2 shift clock SCLK of EPLS.

It is a timing chart of the erase operation when equal erase pulse width erase Parusushi shift amount in the erase block EBLK0 of the circuit structure of FIG. 10 FIG.

11 is a timing chart of the erase operation when longer than the erase pulse shift amount erase pulse width in the erase block EBLK0 of the circuit structure of FIG.

It is a flowchart illustrating an example of FIG. 12 erase flow.

13 is a block diagram showing an overall configuration of a flash memory on-chip microcomputer.

DESCRIPTION OF SYMBOLS

1 non-volatile memory cell

2 channel forming region

3 one of the source 'drain region (source)

4 other source 'drain region (drain)

6 charge storage region

8 memory gate

10 Select gate 20 flash memory

21 memory array

CG selection gate line

MG memory gate line

SL source line

BL bit line

24 selection gate driver

25 write-erase decoder

27 driver circuit

MMOO- MMxy non-volatile Memorisenore

CGO-CGy selection gate line

SLO- SLy source line

BLO- BL pin 'Tsu Bok line

47 selection timing control circuit (TCNT) countO- count3 selection signal

50 counter circuit (COUNT)

51 counter control circuit (CUCNT)

SCLK shift clock

50A- 50D. Development flip-flop (FF)

52 oscillator (OSC)

53 frequency divider (DIV)

54 erase pulse width selector signal

55 erasing Roh pulse width selector (EPWS)

EPLS erase Panoresu

56 pulse generation circuit (PGEN)

57 erase pulse shift amount selector signal

58 erasing Roh Noresushifuto amount selector (EPSS)

60 micro-computer 61 CPU

BEST MODE FOR CARRYING OUT THE INVENTION

[0030] FIG. 2 is a vertical sectional structure of the nonvolatile memory cells of the split gate type is illustrated. Nonvolatile memory cell 1 has a channel formation area 2 to p-type Ueru region 16 provided on a silicon substrate, a pair of source 'drain regions 3 sandwiching the channel forming region 2, 4 Ru is formed. For convenience one source 3, it referred to the other as a drain 4. Source 'drain regions 3, 4 is constituted by n-type diffusion layer (n-type impurity regions). Charge accumulation region through a gate Sani 匕膜 5 to source 3 toward the top of the channel formation region 2 (for example, a silicon nitride film) 6, insulating film 7 及 beauty memory gate (e.g. n-type polysilicon layer) 8 is disposed It is. On the channel forming region 2 select gate (e.g. n-type polysilicon layer) through the gate Sani 匕膜 9 to the drain 4 closer 10 is formed. The charge storage region 6, the memory gate 8 and select gate 10 are mutually insulated phase with the insulating film 11. For convenience, a channel formation region 2 of the source 3 toward refers to the vicinity of the charge storage region 6 and the memory gate 8 memory transistor section, a selection transistor section in the vicinity of the channel formation region 2 and the select gate 10 of the drain 4 closer.

[0031] layer in conjunction with said charge storage region 6 and disposed on the front and back insulating film 5 and the insulating film 7

The thickness of the (called memory gate insulating layer) tm, tc the thickness of the gate insulating film 9 of the select gate 10, and the thickness of the insulating film 11 between the select gate 10 and the memory gate 8 and ti, the relationship of tc <tm≤ti is realized. Than its thickness (layer thickness) dimension difference, the gate withstand voltage of the selection transistor section is lower than a gate withstand voltage of the memory transistor portion. Incidentally, means that it in convenience allocated drain 4 data read operation in the source 'drain region functions as the drain electrode of the MOS DOO transistor, a source 3 which functions as a source electrode of which is MOS transistors in the data read operation to. If the erase and write operations in the drain 4 and the source 3 of necessarily reverse is not necessarily to function to its name as Ru mower.

[0032] The nonvolatile memory cell, the threshold voltage is higher by electron injection into the charge storage region 6 (for example referred to as writing), the threshold voltage by injecting hot holes to said charge storage region 6 (for example referred to as erasure) It is low. In the write operation, For example, 8V voltage of the memory gate 8 (Vmg), the voltage of the source 3 (Vs) and 5V, 1. 8V voltage of the select gate 10 (Vcg), the write select memory cell drain 4 voltage (Vd) OV (ground potential of the circuit), by a 1. 8V voltage of the drain 4 (Vd) of the unselected memory cells, the source 3 a current flows to the drain 4, immediately below the insulating layer 11 a high electric field is formed in parts of the channel region 2, which by connexion generated hot electrons are injected into the charge storage region 6.

In [0033] the erasing operation, as shown in FIG. 2, Vmg = - 5V, Vs = 5V, the substrate and OV, to form Kochikara high electric field on the end force the memory gate 8 of the source 3, the source current flows from the 3 to the substrate. This Yotsute, occur ionizing collisions by the source 3 end near, electronic, hole pairs are generated. Holes having sufficient energy exceeds the potential barrier of the gate Sani 匕膜 5 out of the generated holes becomes hot holes are injected into the charge storage region 6. When the hot Tohoru are injected into the charge storage region 6, and acts in the direction you neutralize electrons are there already injected, this threshold voltage of the O connexion nonvolatile memory cell 1 in a low, variation in the direction It is.

[0034] In the write and erase operations for the non-volatile memory cell 1, the selection gate 10 及 beauty drain does not require the application of high voltage. This is, the gate breakdown voltage of the selection transistor portion is relatively low! To ensure that ヽ.

[0035] In FIG. 2 12- 14 are equipotential lines near the source at the time of erasing. The equipotential lines 1 2, for example 3V, equipotential lines 13 are, for example IV, equipotential lines 14 for example OV. Condition being shown in Figure 2 is a state immediately after the start of the state force erase operation many electrons stored in the charge storage region 6, a relatively large number of free without being neutralized in the charge storage region 6 since electrons are caught capturing, act to intensify the electric field between the source terminal portion 15, the equipotential lines for the potential of the portion 15 is lowered becomes dense, the voltage of the portion 15 in other words gradient descent current flowing from the source 3 as indicated by the large instrument arrow in the p-type Ueru region 16 is increased relatively.

[0036] state when the threshold voltage of the nonvolatile memory cell 1 has decreased somewhat lower progressed erased in FIG. 3 (i.e., number somewhat less summer was state of the trapped electrons in the charge storage region 6) if we erase shows a case in which. Potential of the substrate immediately below the charge storage region 6 small instrument charge storage region is the influence of accumulated electrons 6 becomes higher than the FIG. Therefore, the distance between the equipotential lines 12 14 spreads than 2 in the near vicinity of the source end portion 15. That is, the inclination of the voltage drop becomes smaller in the near vicinity of the source end portion 15, the current flowing from the source 3 to the p-type Ueru region 16 in FIG. 2 Yorichi / J, it made fences.

[0037] the relationship between the time and the erase current when is gradually injecting hot holes in pairs in the nonvolatile memory cell 1 in the state in which many electron are injected as in Figure 2 Figure 4 It is shown. In this case, the peak current is large. Furthermore, since over time the erase progresses gradually erasing current is reduced. In contrast, FIG. 5 proceeds erase, low to some extent the threshold voltage of the nonvolatile memory cell 1, from the state (i.e., small, electrons stored in the charge storage region 6, state) from at the start of the erasure It shows a relationship between time and erase current. The influence of the stored in the charge storage region 6 electrons is small, the peak current than 4 is small. Since erasing progresses over time, gradually erase current as in FIG 4 is decreased.

[0038] configuration of a flash memory is illustrated in Figure 1. Flash memory 20 includes a memory array (ARY) 21 in which a plurality matrix arrangement nonvolatile memory cell 1 of FIG. In Figure 1 is shown the two typically. Matrix arrangement is a plurality of nonvolatile memory cells 1 were the the select gate 10 selects gate lines CG, connected to the memory gate 8 memory gate line MG, the source 3 is source line SL, and the drain 4 to the bit lines BL It is. X address decoder (XDEC) 22 decodes the X address signal input to § address buffer (ADB) 23. Selection Getodora I bus circuit (CGDRV) 24 is dynamic selectively driving the selected gate lines CG in accordance with the decoded result. Selection of the nonvolatile memory cell 1 is performed by selectively driving to the selected gate line CG is a read operation and downy Rifai operation. Write erase decoder (PEDEC) 2 5 performs the selection of the memory gate line MG and the source line SL in the writing and erasing. Selection of operation writes uses the decode result by the X address decoder 22 via a selection gate line CG. Selection of the erase operation is performed based on the instruction information of the erase blocks are erased. The driver circuit (PEDRV) 27 drives the memory gate line MG and the source line SL based on the selection signal output from the write erase decoder 25.

[0039] the bit line BL a sense latch (SL) and the data register circuit (DREG) 30 is connected. Sense latch (SL) is detecting and holding the stored information read out to the bit line BL from the nonvolatile memory cell 1. Data register (DREG) is utilized, such as the holding of the memory cell storing information to be saved before the holding and erasing write data supplied externally force, data held in use in the control of the bit line BL level in the write operation It is. Sensura Tutsi and the data register circuit 30 is connected to the data output buffer (DTB) 32 via a Y selection circuit (YG) 31, it is the data bus 33D and interfaces available-contained external bus 33. Y selection circuit 31 in a read operation in accordance with the address decode signal outputted from the Y address decoder (YDEC) 3 4, selects the data out read latched by the sense latch (SL). Read the selected data is to be output to the outside through the data input-output buffer 32. Y address decoder 34 in a write operation, controls whether to correspond to write data supplied from the data input buffer 32 in which bit lines BL is latched in the data register (DREG).

[0040] Address signals are supplied from the external bus address bus 33A to an address buffer 23 is supplied from § address buffer 23 to the X address decoder 22 and the Y address decoder 34. Read, erase, 5V required for writing, -5V, a high voltage such as 8V VPP1, VPP2, ..., boosting circuit VPPi (VPG) 35 is generated based on the external power supply Vdd, the Vss.

[0041] according to the control circuit (CONT) 36 is control information set in the control register (CREG) 37, a read operation, for switching example control of the erase operation, and the control sequence and operation power of the write operation. The switching control of the operating power, the read operation, in response to the erase operation, and write operation is suitably switched controlled in accordance with the operation mode and operating power driver circuit 24, 27.

[0042] Detailed examples of the memory array and writing the erase decoder is shown in Figure 6. A plurality of nonvolatile memory cells MMOO- MMxy that the Oite memory array in FIG. In a matrix arrangement is illustrated. Nonvolatile memory cell MMOO- MMxy has the same device structure as the nonvolatile Memorise le 1. Connected to the selected gate line CGO- CGy corresponding to a selective gate 1 0 row unit of the nonvolatile memory cell MMOO- MMxy, the source line corresponding with the source 3 units of rows of nonvolatile memory cells M MOO- MMxy SLO- SLy is connected to the drain 4 of the nonvolatile memory cell MMOO- MMxy is connected bit line BLO- B Lx 〖this corresponding column by column. One line of the nonvolatile memory cell is referred to as a sector. And erase block to be erased in units of non-volatile memory cells of the four sectors for nonvolatile memory cells MMOO- MMxy, the erase block to be erased in units of non-volatile memory cells of one sector is assigned, memory gate 8 of the nonvolatile memory cells are commonly connected to the memory gate line MG units of erase blocks. Erase block EBLKO of four sectors, as representatively shown in FIG. 6 are commonly connected to the memory gate line MGO, erase block EBLKm for one sector are commonly connected to Memorige over preparative line MGm.

[0043] The driver circuit (PEDRV) 27 has an output inverter 40 and a level converting circuit (LVSFT) 41 corresponding to each source line SLO- SLy and the memory gate line MgO-MGm. The output inverter 40 erase, write, operating power in response to the operation mode of the reading is switched et al. The level conversion circuit (LVSFT) 41 into a signal level to comply input signals also front forces operating power output inverter 40. Driver circuit (PEDRV) 27 are high withstand voltage MOS transistor is used in relation to its operating power supply.

[0044] Write erase decoder (PEDEC) 25 includes an output inverter 42 output to the level conversion circuit 41 is coupled, and three NAND gates (NAND) 43- 45 force is also composed of a selector 46, selects a timing control circuit It has a (TCNT) 47, a decode logic (DECLCG) 48. mgselO- mgselm is a selection signal of the memory gate lines MgO-MGm, those corresponding on the basis of a selection signal which is transmitted via the selection Gate line CGO- CGy is the selected level. prog instruction signal of the write operation, slselO- slsely is the source line SL0- SLy selection signal definitive for the write operation. In the write operation source line corresponding on the basis of a selection signal which is transmitted via the selection gate lines CG0- CGy is the selected level may be a write operation is performed in sector units.

[0045] erase the instruction signal of the erase operation, eraseblockO- eraseblockm are selection signals of the erase block EBL K0- EBLKm. Erase block selection signal eraseblockO- erasebloc km is the selected level in accordance with the erase block designation information supplied to DECLCG48 from CREG37. CountO- count3 is a selective signal of the source line SL4i in erase block when the erase operation, SL4i + l, SL4i + 2, SL4i + 3 (i = 0- n).

[0046] For example, in the erase operation the memory gate line MG0 memory gate control line selection signal mgselO is the high level (H) is - is to 5V, the erase block select signal eraseblockO is Haile base Le (H), the erase operation instruction signal erase the high level (H), by erase block in the source line select signal countO is the high level (H), as illustrated in FIG. 6, the memory gate lines MG0 of Memoriare I 21 - to 5V is, the source line SLO is to 5V, the erase pulse to the non-volatile memory cell MMOO- MMxO sectors SCTO is applied. Selection signal power s CountO sequentially activated in accordance with the change in count 1, count2, count3, sector erase pulse is applied SCT0, SCT1, SCT2, becomes a sequentially switched can come to SCT3. In this way, shifting the timing sectors in the erase block is possible to apply a high voltage Bruno Luz hot Tohoru injection.

[0047] In FIG. 7 embodiment of the selection timing control circuit (TCNT) 47 is shown. Selecting the timing control circuit 47 includes a counter circuit (COUNT) 50 for forming the selection signal CountO- count3, and a counter control circuit (CUCNT) 51 for controlling the change timings of the plurality of selection signals countO- count3. The counter circuit 50 has a plurality of storage units such as D-type flip-flop (FF) 50A one 50D performs synchronization with a shift operation to the change of the shift clock SCLK to the serial output of said plurality of flip-flops 50A- 50D There are a plurality of selection signals countO- count3.

[0048] The counter control circuit 51 includes an oscillator (OSC) 52, frequency divider the output of the oscillator 52 by dividing to form a plurality of divided clock signal (DIV) 53, output frequency divider mosquito ゝ al based on a plurality of frequency division division clock signal selected by the pulse width selector (EPWS) 55 and the erase pulse width selector 55, erase selecting one by erasing pulse width selector signal 54 from the clock signal that Clear one of the plurality of frequency-divided clock signal outputted from the pulse generating circuit (PGEN) 56, and the frequency dividing circuit 53 for generating erase pulses EPLS supplied to the first stage flip-flop 50A of the counter circuit 50 select a pulse shift amount selector signal 57 consisting of the erase pulse shift amount selector (EPSS) 58 for selecting the period of the shift clock SCLK.

[0049] waveforms of the selection signal CountO- count3 formed in accordance with the pulse width of the erase pulse EPLS the period of the shift clock SCLK is illustrated in FIGS. Shift amount SFT erase pulse in each figure will be one cycle of the shift clock SCLK. In order to change the shift amount SFT may be changed to the cycle of the shift clock. Pulse width PW1 of the erase pulse EPLS 8 is one cycle of the shift clock SCLK. This Yotsute selection signal countO one count3 to is pulsed change in sequential non-overlapping. Pulse width PW2 of the erase pulse EPL S 9 are the four cycles of the shift clock SCLK. This Yotsute selection signal co untO- count3 to is 4 cycles Dzu' pulse change of shift clock SCLK in the overlap shifted sequentially one period Dzu' of the shift clock SCLK.

[0050] As described above, the erase pulse width selected by the erase pulse width selector 55, the erase pulse shift amount selected by the erase pulse Sushifuto weight selector 58, and either overlap the selection signal countO one count3 a non-overlap or together selected to become the overlap amount to variably selectable.

[0051] in FIG. 10 and FIG. 11 a timing chart of the erase operation in the erase block EBLK0 the circuit configuration of FIG. 6 is shown. The non-volatile memory cells in the erase block EBLK0 MM00, MMxO, MM01, MMxl, MM02, MMx2, MM03, to clear the MMx3, selection gate lines CG0, CG1, CG2, CG3, for example the OV is applied, the bit line BL0, for example, to open BLx. Then an erase signal erase the high level (H), selecting the erase block EBLK0 in the subsequent selection signal er AseblockO a high level (H). Then the selection signal mgselO a high level (H), is applied to the memory gate line MG0 example 5V. And the following signals countO the high level (H), is applied, for example, 5V to the source line SL 0, erasing nonvolatile memory cell in the erased sectors SCT0. Predetermined time after the signal countO to a low level (and, the voltage of the source line SL0 to 0V. Then the signal countl and Nono Ireberu (H), is applied, for example, 5V to the source line SL1, nonvolatile memory erase sector SCT1 erasing the cells. Similarly signal count2 and count3 to pulse changing, sequentially erasing the nonvolatile memory cell in the erased sectors SCT3 the erase sector SCT2. Note that the time Nono Ireberu (H) period of the signal CountO- count3 erase pulse width, the signal rise time difference of the rise of the next signal counti + 1 signals Counti, for example, defined as an erase pulse shift amount of time difference between the rising time and the rising time of Counti of CountO. source lines during the erase SL 0, SL1, SL2, SL 3, the sum of the erase current flowing in the Sly defined as source the total current.

[0052] Figure 10 shows the timing chart when equals erase pulse shift amount and the erase pulse width. In this case, the source line SL 0, SL1, SL2, SL3 period voltage is 5V, that do not overlap between selected 択期. Therefore, as shown, the peak current of the peak current and each of the source lines of the source the total current is equal U,.

[0053] FIG. 11 is long than the amount erase pulse width is erased Norusushifuto, shows the timing chart when. In this case, there is a period of overlap in the selection period of the source line SLO, SL1, SL2, SL3. Therefore, the source line SLO, SL1, SL2, period SL3 is selected whole, the peak of the source the total current current becomes largest. And then force, because of repeated selection period of the source line SLO, SL1, SL2, SL3, can shorten the erase time. The ratio of the 11 and the erasing pulse width and the erasing Parusushi shift amount is 4: a is the force is not limited to this one.

[0054] shows an example of the erase flow in FIG. This erase flow, carried erased first in Thailand timing chart of FIG. 10, that is carried out by setting equal the erase pulse shift amount and the erasing pulse width (SI, S2). Next, Rifai base or erased all erased area (S 3). If not erased is completed, carrying out erasure of second timing chart of FIG. 11, that is carried out longer than the erase pulse shift amount erase pulse width (S4, S5). Next, Rifai base forces are erased area are all erased (S6). Third and subsequent are the same as those of the second time.

[0055] Many electronic and is injected into the charge storage region 6 as shown in FIG. 2 is a first erasing step SI, S2. Thus, the current flowing from the source 3 to the substrate 16 in the erase operation by applying large damage, the timing chart of FIG. 10, suppressing the peak current of the source the total current. By suppressing the peak current of the source over scan total current, it is possible to suppress the current supply capability of the power supply circuit 35 for supplying a source current. Since it is possible suppress the current supply capability of the power supply circuit for supplying a source current can be reduced and the power supply circuit area, can contribute to miniaturization of the chip.

[0056] In the erase the second and subsequent number of electrons stored in the charge storage region 6 as shown in FIG. 3 is small Nakunatsu. Therefore, since the current flowing from the source 3 to the substrate 16 smaller, even by applying the timing chart of FIG. 11, it is possible to suppress the peak current of the source the total current. Furthermore, it is possible to select the source line timing (application timing of the erase pulse) overlapped have Runode, shortening the erase time.

[0057] In FIG. 13 the overall arrangement of a microcomputer with on-chip the flash memory 20 is shown. The microcomputer 60 is not particularly limited, on one semiconductor substrate such as single crystal silicon (semiconductor chips) are formed by CMOS integrated circuit manufacturing technology. The microcomputer 60 includes a central processing unit (CPU) 61, RAM 62 as a volatile memory, a flash memory (FLASH) 20 as a nonvolatile memory, Roh scan state controller (BSC) 63, and the input and output port circuits with input and output circuits (IZO) 64, which circuit module is connected to the internal bus 66. Internal bus 66 includes address, data, and each signal line of the control signal. CPU61 includes an execution unit and the instruction control unit decodes the instruction that full Tutsi, performs arithmetic processing in accordance with the decoded result. Flash memory 20 stores an operation program and data CPU 61. RAM62 is a CPU61 work area or de one coater during storage area. Operation of the flash memory 20 is controlled based on the control data CPU61 is set in the control register 37. Bus state controller 63 access via the internal bus 66, the number of access cycles to external Bruno scan access, wait states inserted, controls the bus width and the like.

[0058] circuits other than the region 69 surrounded by a two-dot chain line in FIG. 13 means a circuit portion constituted by a thin MOS transistors relatively gate Sani 匕膜. Circuit region 69 will circuit portion constituted by a thick high-voltage MOS transistors relatively gate Sani 匕膜. For example, an area where you! / To the flash memory 20, PEDRV27 like Te is formed is a high voltage MOS transistor circuit portion, a thin MOS transistor circuit portion region of the gate Sani 匕膜 that CGDRV24 like in the flash memory 20 is formed It is.

[0059] Although the present invention made by the inventor has been concretely described based on the embodiments, the present invention is that the needless to say the present invention is not limited thereto and various modifications are possible within a scope not departing from the gist of Nag, .

[0060] was deleted Panoresushifuto amount 7 and one period of the shift clock SCLK for example, but not limited to one period. In this case 7, and add the flip-flop in the preceding stage of the flip-flop 50Arufa, or flip-flop 50Α- another between each of 50D Prefectural flop insertion Surebayo.

[0061] Further, although set equal first erase only erase Panoresu width erase Panoresushifuto amount erase flow of FIG. 12, such a configuration is not limited to the first. It erases several times while set equal to the erase pulse width erase Norusushifuto amount, erase after may be carried out longer than the erase pulse shift amount erase pulse width. Also, the erase pulse widths in accordance with the number of times of erasing, the erase pulse shift amount, a memory gate voltage may be arbitrarily change the source voltage.

[0062] Moreover, Do nonvolatile memory cell is limited to a split gate structure. Further, not limited to the charge accumulation region is an insulating trapping regions such as silicon nitride, it may be in a floating type nonvolatile Memorise Le of having a charge accumulation region of a conductivity such as policy silicon .

Industrial Applicability

[0063] The present invention may be a flash memory, apply more so etc. microcomputer having a flash memory widely.

Claims

The scope of the claims
[1] is the threshold voltage is higher by injection of electrons to the charge accumulation region, comprising a plurality of non-volatile memory cell threshold voltage is lowered by the injection of hot holes for said charge storage area,
Multiple times processing for applying the high voltage pulse for a part hot hole injection at different timings by the selected plurality of nonvolatile memory cells as an implantation target hot hole until the desired threshold voltage have a control circuit that can be repeated divided into,
Wherein the control circuit, the timing may be more than one of either of the selected high voltage pulses to or partially overlapping with non over wrapping shifted nonvolatile semi-conductor memory.
[2] The control circuit includes a non-volatile semiconductor memory according to claim 1, wherein the degree of partial overlap of the high-voltage pulse is selectable ability.
[3] The control circuit, after the beginning of the hot hole injection to be repeated a plurality of times of the application of the high voltage pulse shifted timing as non-overlapping, returned Ri Repetitive plural times square hot nonvolatile semiconductor memory according to claim 1, wherein the application of a high voltage pulse different timings in hole injection partially to overlap.
[4] The control circuit, when lowering the threshold voltage of the nonvolatile memory cell, in a state of forming a Kochikara Cormorant field to the storage region from the channel region of the nonvolatile memory cell, one of the source 'drain collector extreme the nonvolatile semiconductor memory according to claim 1, wherein injecting hot holes generated in the storage area.
[5] A semiconductor device having a nonvolatile semiconductor memory,
The nonvolatile semiconductor memory includes an array of nonvolatile memory cells each having a isolated charge storage region and the memory gate regions on the channel forming region sandwiched between the source and drain regions,
'First wiring drain region are coupled, the other of the source of the nonvolatile memory cells' one of the source of the nonvolatile memory cell and the second wiring drain region are coupled, the memory gate of the nonvolatile memory cell a third interconnection region is bound, performs control to increase the threshold voltage by injecting electrons into the charge storage region of the nonvolatile memory cell, the threshold voltage by injecting hot holes into the charge storage region and a control circuit for performing control of the lower,
Wherein the control circuit, the hot hole high voltage pulse is applied to process the desired threshold voltage of the hot hole injection at different timings by a portion the selected plurality of nonvolatile memory cells as an implantation target a is possible to repeat a plurality of times until, it is possible to do the selection plurality of high voltage pulses to the non-overlap and be Luke or partially overlapping shifted the timing semiconductor device.
[6] wherein the control circuit, the high voltage pulse semiconductor device according to claim 5, wherein the degree of partial overlap is selectable ability.
[7] wherein the control circuit, after the beginning of the hot hole injection to be repeated a plurality of times of the application of the high voltage pulse shifted timing as non-overlapping, returned Ri Repetitive plural times square semiconductor device according to claim 5 wherein the partially overlaps the application of high voltage pulses different timings in hot hole injection.
[8] The control circuit, when lowering the threshold voltage of the nonvolatile memory cell, in a state of forming a Kochikara Cormorant field to the storage region from the channel region of the nonvolatile memory cell, one of the source 'drain collector extreme the semiconductor device according to claim 5, wherein injecting hot holes into the storage region occurs.
[9] a plurality of nonvolatile memory cells arranged in a matrix on the array,
Matrix arrangement is a plurality of nonvolatile memory cells are share the first wiring line by line, to share the second wiring per column, it shares a third wire in a multi-line basis,
Wherein said control circuit, first the first wiring connected to the third of the first high-voltage pulse is applied to the wiring, a plurality of nonvolatile memory cells sharing the third wirings and the selected the selected semiconductors according to claim 5, wherein applying a second high voltage pulse by shifting the timing between wiring mutually.
[10] The control circuit includes a counter circuit for forming a plurality of selection signals for selecting a plurality of first wiring according to the non-volatile memory cells in the plurality of rows that share the third wiring, before Symbol plurality of and a counter control circuit for controlling the timing of change of the selection signal, said counter circuit has a plurality of storage units to perform a shift operation in synchronism with the shift clock changes in series, the plurality of storage units output is the plurality of selection signals, said counter control circuit includes a pulse generation circuit for generating a pulse to be supplied to the first stage of the counter circuit, pulse to be selected the width of the pulses generated by the pulse generating circuit and width selection circuit, the semiconductor device according to claim 9 having a shift amount selection circuit to variable shift amount of the pulse by the period selection of said shift clock.
[11] The nonvolatile memory cell, the select gate region said over the channel formation region through the insulating film of the second source-drain region side where the wiring is connected is formed, the memory gate and the select gate region the semiconductor device according to claim 9, further comprising a split-gate structure which regions are separated.
[12] The selection gate region force saw gate breakdown voltage semiconductor device of low claim 11 than the gate breakdown voltage viewed the memory gate region force.
[13] The nonvolatile semiconductor memory further comprises a controller for controlling access, billing the gate breakdown voltage as seen selected Gate region force is the same as the gate breakdown voltage of the field effect transistor of the insulated gate constituting the controller the semiconductor device of claim 12, wherein.
PCT/JP2005/002006 2005-02-10 2005-02-10 Non-volatile semiconductor memory and semiconductor device WO2006085373A1 (en)

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