JP4683494B2 - Nonvolatile semiconductor memory and semiconductor device - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory that employs a method of injecting hot holes into a charge storage region to lower the threshold voltage of a nonvolatile memory cell, and a semiconductor device equipped with the nonvolatile semiconductor memory, and is effective when applied to a flash memory, for example. Regarding technology.

  As a technique for injecting (e.g., referred to as writing) and releasing or neutralizing (e.g., referred to as erasing) electrons into and from the charge storage region of the non-volatile memory cell, electrons are taken in and out using a tunnel current all over the gate electrode. There are a method using an FN tunnel current and a method using a hot carrier. In the former, it is necessary to increase the operation voltage for the write operation and the erase operation, but since the operation current can be reduced, the nonvolatile memory having a large number of memory cells to be subjected to the write operation or the erase operation. It is often used for. In the latter case, the operation voltage for writing and erasing can be lowered and the operation can be performed at a high speed. Therefore, there are relatively few memory cells to be subjected to the writing operation or the erasing operation, and a high-speed operation is necessary. Often used for non-volatile memory.

  For example, in a MONOS (Metal Oxide Nitride Oxide Semiconductor) type nonvolatile memory cell in which a nitride film and a memory gate which are insulated from each other are formed on a channel forming region, one of the source and drain is erased by the hot carrier method. A high electric field from the electrode end toward the memory gate is formed, and a current flows from the one source / drain electrode to the substrate. As a result, an ionizing collision occurs in the vicinity of the one end of the source / drain electrode, and an electron / hole pair is generated. Of the generated holes, holes having sufficient energy to exceed the potential barrier of the gate oxide film become hot holes and are injected into the nitride film. When hot holes are injected into the nitride film, they act in the direction of neutralizing the electrons already injected therein, thereby changing the threshold voltage of the memory cell in the lower direction. In this erasing by hot hole injection, on the one hand, a current must flow from the source / drain region to the channel formation region. If the number of non-volatile memory cells as an erasing unit increases, a large current must be flowed as a whole, and a power supply circuit or a booster circuit having a large current capacity is required.

  Patent Document 1 describes a general technique in which the write timing is shifted for each memory cell to be written in order to reduce the peak value of current consumption. Patent Document 2 describes a technique for injecting hot holes in an erase operation of a memory cell.

JP 2002-109894 A International Publication No. 02/19342 Pamphlet

  The inventor examined the nonvolatile semiconductor memory described in Patent Document 1. In the nonvolatile memory described in Patent Document 1, one write operation target is a word line unit, and one erase operation target is a block unit including a plurality of word lines. It can be considered that the number of memory cells to be erased is larger than the number of memory cells to be erased and the number of memory cells to be erased during the erase operation. When erasing operation is performed by hot hole injection, the current flowing in the channel formation region of the memory cell is compared with the current flowing in the channel formation region of the memory cell in order to perform hot electron injection in the writing operation. It has been found that the amount of current required for the operation is greater than the amount of current required for the write operation.

  On the other hand, in the nonvolatile memory described in Patent Document 2, it is considered that the change in the boosting speed of the voltage applied to the well region is made constant according to the number of memory cells to be erased during the erase operation. However, it has become clear that the amount of current flowing through the channel formation region of the memory cell to be erased has not been studied.

  Based on the above examination, the present inventor further divides a block, which is an erasing unit that can be designated from the outside, and performs erasing in units of sectors with memory cells connected to one word line as a unit. We studied a method to reduce the amount. In short, the high-voltage erase pulse applied to the one source / drain region is shifted sector by sector. However, it has been clarified by the present inventor that there is a problem that the erase processing time becomes longer by the amount of application of the erase pulse.

  An object of the present invention is to provide a nonvolatile semiconductor memory that can suppress an increase in processing time as a whole even if hot hole injection is performed by shifting the application timing of a high voltage pulse to a nonvolatile memory cell. is there.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] One typical nonvolatile semiconductor memory according to the present invention is a nonvolatile memory in which the threshold voltage is increased by injection of electrons into the charge storage region and the threshold voltage is decreased by injection of hot holes into the charge storage region. Desirable to have a plurality of cells (1) and apply a high voltage pulse for hot hole injection to a plurality of non-volatile memory cells selected as hot hole injection targets while shifting their timings one by one. A control circuit (25, 36) that can be repeated in a plurality of times until the threshold voltage is reached, and the control circuit makes the plurality of high voltage pulses shifted in timing non-overlapping or It is possible to select whether to partially overlap.

  If multiple high voltage pulses are non-overlapping, the peak value of current consumption due to application of high voltage pulses can be minimized, and if multiple high voltage pulses are overlapped, the degree of overlap increases. Accordingly, the peak value of current consumption increases and the overall processing time for lowering the threshold voltage is shortened.

  The current flowing through one source / drain end of the nonvolatile memory cell contributes to the generation of hot holes, but the current decreases as hot holes are injected into the charge storage region. Focusing on this property, when the process of applying a high voltage pulse for hot hole injection is repeated several times until the desired threshold voltage is reached, the latter flows to one of the source / drain ends compared to the first. The current becomes smaller. Therefore, at first, a large current flows through one of the source / drain ends, so it is convenient for suppressing the current peak to make the high voltage pulse non-overlapping. In the latter case, the current flowing through one of the source / drain ends is smaller, so it is more convenient to shorten the processing time by partially overlapping the high-voltage pulse. There will be no overload.

  From the above, even if hot hole injection is performed by shifting the application timing of the high voltage pulse to the nonvolatile memory cell, it is possible to suppress the increase in the processing time as a whole.

  As a specific form of the present invention, the control circuit can select the degree of partial overlap of the high voltage pulse. In the latter high voltage pulse application process, the current flowing to one end of the source / drain becomes smaller. In some cases, it may be desirable to extend the pulse application time rather than the first. Become.

  As another specific form of the present invention, the control circuit sets the application of a high-voltage pulse with a non-overlapping timing in the first hot hole injection repeated in a plurality of times as a non-overlap. In the later hot hole injection, which is repeated separately, the application of high voltage pulses with shifted timing is partially overlapped. This is suitable when a control method focusing on the above properties is adopted in the control circuit.

  As another specific form of the present invention, when the threshold voltage of the nonvolatile memory cell is lowered, the control circuit is configured in a state in which an electric field directed from the channel region of the nonvolatile memory cell toward the storage region is formed. Hot holes generated at the ends of the source / drain electrodes (3) are injected into the storage region (6).

  [2] A typical semiconductor device (60) according to the present invention includes a nonvolatile semiconductor memory (20), and the nonvolatile semiconductor memory is sandwiched between source / drain regions (3, 4). An array (21) of nonvolatile memory cells (1) having a charge storage region (6) and a memory gate region (8), which are insulated on the channel formation region (2), respectively, and one of the nonvolatile memory cells A first wiring (SL) coupled with a source / drain region (3); a second wiring (BL) coupled with the other source / drain region (4) of the nonvolatile memory cell; and the nonvolatile memory. Control is performed to increase the threshold voltage by injecting electrons into the charge storage region of the nonvolatile memory cell and the third wiring (MG) to which the memory gate region of the cell is coupled, and hot holes are formed in the charge storage region. Injection to lower threshold voltage And a control circuit (25, 36) for performing control, wherein the control circuit shifts the timing of each of the plurality of nonvolatile memory cells selected as the hot hole injection targets one by one. The process of applying the high voltage pulse for injection can be repeated in a plurality of times until the desired threshold voltage is reached, and the plurality of high voltage pulses shifted in timing are made non-overlapping or partially It is possible to select whether to overlap automatically.

  Similarly to the above, it is preferable to adopt a configuration in which the degree of partial overlap of the high voltage pulse can be selected for the control circuit. In the control circuit, in the first hot hole injection that is repeated in a plurality of times, the application of a high voltage pulse with a shifted timing is made non-overlapping, and the later hot hole that is repeated in a plurality of times is repeated. In the hole injection, it is preferable to adopt a configuration in which application of a high voltage pulse with a shifted timing is partially overlapped.

  As a specific form of the present invention, the control circuit is configured such that when the threshold voltage of the non-volatile memory cell is lowered, an electric field from the channel region of the non-volatile memory cell toward the storage region is formed. Hot holes generated at the end of the drain electrode are injected into the accumulation region.

  At this time, a plurality of non-volatile memory cells are arranged in a matrix in the array, and the plurality of non-volatile memory cells arranged in a matrix share the first wiring (SL) in units of rows and the second in units of columns. A wiring (BL) is shared, a third wiring (MG) is shared in units of a plurality of rows, and a first high voltage pulse (−5 V) is applied to the selected third wiring in the control circuit, A configuration in which the second high voltage pulse (5 V) is applied to the first wiring connected to the plurality of nonvolatile memory cells sharing the selected third wiring while shifting the timing between the first wirings. Adopt it.

At this time, the control circuit forms a plurality of selection signals for selecting a plurality of first wirings related to a plurality of rows of nonvolatile memory cells sharing the third wiring. And a counter control circuit (51) for controlling the change timing of the plurality of selection signals, and the counter circuit performs a shift operation in synchronization with the change of the shift clock (SCLK). ˜50D) in series, and the outputs of the plurality of storage stages are the plurality of selection signals,
The counter control circuit includes a pulse generation circuit (56) that generates a pulse (EPLS) supplied to the first stage of the counter circuit, and a pulse width selection circuit (55) that enables selection of the width of the pulse generated by the pulse generation circuit. ) And a shift amount selection circuit (58) that makes the shift amount of the pulse variable by selecting the cycle of the shift clock. The pulse width and overlap amount of the high voltage pulse can be varied with a relatively simple configuration.

  As a more specific form of the present invention, the nonvolatile memory cell includes a select gate region (10) over the channel formation region on the source / drain region side to which the second wiring is connected via an insulating film. And a split gate structure in which the selection gate region and the memory gate region are separated. At this time, the gate breakdown voltage seen from the selection gate region is preferably lower than the gate breakdown voltage seen from the memory gate region. Due to the split gate structure, even when a high voltage is applied to one of the source / drain ends when electrons or hot holes are injected into the charge storage region, the other source / drain end on the side of the select gate region has a high voltage via the channel region. This is because no voltage is applied, and it is not necessary to make the select gate region side have a high breakdown voltage. Thereby, when the storage information of the nonvolatile memory cell is read from the selection gate region side, it is easy to increase the mutual conductance (gm) on the selection gate region side.

  As a more specific form of the present invention, a controller (61) for controlling access to the nonvolatile semiconductor memory is further provided, and a gate breakdown voltage viewed from the selection gate region is a gate insulating type electric field constituting the controller. It may be the same as the gate breakdown voltage of the effect transistor.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, even if hot hole injection is performed by shifting the application timing of the high voltage pulse to the nonvolatile memory cell, the increase in the processing time as a whole can be suppressed as much as possible.

1 is a block diagram illustrating a configuration of a flash memory. It is a longitudinal cross-sectional view illustrating a vertical cross-sectional structure of a split gate type nonvolatile memory cell as a state where many electrons are accumulated in a charge accumulation region. FIG. 3 is a vertical cross-sectional view illustrating a vertical cross-sectional structure of a nonvolatile memory cell as a state in which the number of trapped electrons in the charge storage region is reduced with respect to FIG. 2. FIG. 3 is a characteristic diagram showing a relationship between time and erase current when hot holes are gradually injected into a nonvolatile memory cell in which many electrons are injected as shown in FIG. 2. A characteristic diagram showing the relationship between time and erase current when erasing is started from a state where the threshold voltage of the nonvolatile memory cell is lowered to some extent (a state where the number of electrons accumulated in the charge storage region is small) due to progress of erasure. is there. It is a circuit diagram which shows a detailed example of a memory array and a write / erase decoder. It is a logic circuit diagram which shows the specific example of a selection timing control circuit (TCNT). 10 is a timing chart showing waveforms of selection signals count0 to count3 when the pulse width PW1 of the erase pulse EPLS is set to one cycle of the shift clock SCLK. 10 is a timing chart showing waveforms of selection signals count0 to count3 when the pulse width PW2 of the erase pulse EPLS is set to four periods of the shift clock SCLK. 7 is a timing chart of an erase operation when the erase pulse width and the erase pulse shift amount are made equal in the erase block EBLK0 having the circuit configuration of FIG. 7 is a timing chart of an erase operation when an erase pulse width is longer than an erase pulse shift amount in the erase block EBLK0 having the circuit configuration of FIG. It is a flowchart which shows an example of an erasure | elimination flow. 1 is a block diagram showing an overall configuration of a microcomputer on-chip a flash memory.

Explanation of symbols

1 Nonvolatile memory cell 2 Channel formation region 3 One source / drain region (source)
4 The other source / drain region (drain)
6 charge storage region 8 memory gate 10 selection gate 20 flash memory 21 memory array CG selection gate line MG memory gate line SL source line BL bit line 24 selection gate driver 25 write erase decoder 27 driver circuit MM00 to MMxy nonvolatile memory cells CG0 to CG0 CGy selection gate line SL0 to SLy Source line BL0 to BLx Bit line 47 Selection timing control circuit (TCNT)
count0 to count3 selection signal 50 counter circuit (COUNT)
51 Counter control circuit (CUCNT)
SCLK Shift clock 50A-50D D flip-flop (FF)
52 Oscillator (OSC)
53 Divider (DIV)
54 Erase pulse width selector signal 55 Erase pulse width selector (EPWS)
EPLS Erase Pulse 56 Pulse Generation Circuit (PGEN)
57 Erase pulse shift amount selector signal 58 Erase pulse shift amount selector (EPSS)
60 Microcomputer 61 CPU

  FIG. 2 illustrates a vertical cross-sectional structure of a split gate type nonvolatile memory cell. The nonvolatile memory cell 1 has a channel formation region 2 in a p-type well region 16 provided on a silicon substrate, and a pair of source / drain regions 3 and 4 are formed with the channel formation region 2 interposed therebetween. For convenience, one is called a source 3 and the other is called a drain 4. The source / drain regions 3 and 4 are constituted by n-type diffusion layers (n-type impurity regions). On the channel formation region 2, a charge storage region (for example, silicon nitride film) 6, an insulating film 7, and a memory gate (for example, n-type polysilicon layer) 8 are disposed near the source 3 via a gate oxide film 5. A selection gate (for example, an n-type polysilicon layer) 10 is formed on the channel formation region 2 via the gate oxide film 9 near the drain 4. The charge storage region 6, the memory gate 8 and the selection gate 10 are insulated from each other by an insulating film 11. For convenience, the vicinity of the channel formation region 2 near the source 3, the charge storage region 6 and the memory gate 8 is referred to as a memory transistor portion, and the vicinity of the channel formation region 2 near the drain 4 and the selection gate 10 is referred to as a selection transistor portion.

  The film thickness of the charge storage region 6 combined with the insulating film 5 and the insulating film 7 disposed on the front and back (referred to as a memory gate insulating layer) is tm, and the film thickness of the gate insulating film 9 of the select gate 10 is When the thickness of the insulating film 11 between the selection gate 10 and the memory gate 8 is ti, the relationship of tc <tm ≦ ti is realized. Due to the difference in film thickness (layer thickness), the gate withstand voltage of the selection transistor portion is made lower than the gate withstand voltage of the memory transistor portion. Note that the drain 4 assigned to the source / drain region for convenience means that it functions as a drain electrode of the MOS transistor in the data read operation, and the source 3 means that it functions as a source electrode of the MOS transistor in the data read operation. In the erasing / writing operation, the drain 4 and the source 3 do not necessarily function as the names indicate, and vice versa.

  The threshold voltage of the nonvolatile memory cell is increased by injection of electrons into the charge storage region 6 (for example, referred to as writing), and the threshold voltage is decreased by injection of hot holes into the charge storage region 6 (for example, referred to as erasure). . In the write operation, for example, the voltage (Vmg) of the memory gate 8 is 8 V, the voltage (Vs) of the source 3 is 5 V, the voltage (Vcg) of the selection gate 10 is 1.8 V, and the voltage of the drain 4 of the write selection memory cell. By setting (Vd) to 0 V (the ground potential of the circuit) and the voltage (Vd) of the drain 4 of the write non-selected memory cell to 1.8 V, a current flows from the source 3 to the drain 4, and the channel immediately below the insulating layer 11. A high electric field is formed in the region 2, and hot electrons generated thereby are injected into the charge storage region 6.

  In the erase operation, as shown in FIG. 2, Vmg = −5V, Vs = 5V, the substrate is set to 0V, a high electric field from the end of the source 3 toward the memory gate 8 is formed, and a current flows from the source 3 to the substrate. Shed. As a result, ionizing collision occurs in the vicinity of the end of the source 3 to generate electron and hole pairs. Of the generated holes, holes having sufficient energy to exceed the potential barrier of the gate oxide film 5 become hot holes and are injected into the charge storage region 6. When hot holes are injected into the charge storage region 6, they act in a direction to neutralize the electrons already injected therein, thereby changing the threshold voltage of the nonvolatile memory cell 1 in a lower direction.

  In the above write and erase operations for the nonvolatile memory cell 1, it is not necessary to apply a high voltage to the select gate 10 and the drain. This guarantees that the gate breakdown voltage of the selection transistor portion may be relatively low.

  In FIG. 2, 12 to 14 are equipotential lines near the source at the time of erasing. The equipotential line 12 is, for example, 3V, the equipotential line 13 is, for example, 1V, and the equipotential line 14 is, for example, 0V. The state shown in FIG. 2 is a state immediately after the erase operation is started from a state in which many electrons are accumulated in the charge accumulation region 6, and relatively many free electrons are not neutralized in the charge accumulation region 6. Since it is trapped, it acts to strengthen the electric field between the source end portion 15 and the potential of the portion 15 becomes lower, so that the equipotential lines become dense, in other words, the slope of the voltage drop of the portion 15. As shown by the arrows, the current flowing from the source 3 to the p-type well region 16 is relatively large.

  FIG. 3 shows a case where erasing is performed from a state where the threshold voltage of the nonvolatile memory cell 1 has decreased to some extent (that is, a state where the number of trapped electrons in the charge storage region 6 has decreased to some extent). . The influence of the electrons stored in the charge storage region 6 is small, and the potential of the substrate immediately below the charge storage region 6 is higher than that in FIG. Therefore, the interval between the equipotential lines 12 to 14 is wider in the vicinity of the source end portion 15 than in FIG. That is, the slope of the voltage drop is reduced in the vicinity of the source end portion 15, and the current flowing from the source 3 to the p-type well region 16 is smaller than that in FIG.

  FIG. 4 shows the relationship between time and erase current when hot holes are gradually injected into the nonvolatile memory cell 1 in a state where many electrons are injected as shown in FIG. In this case, the peak current is large. Further, since erasing proceeds with time, the erasing current gradually decreases. On the other hand, in FIG. 5, the erasing progresses, and the time and erasing when erasing is started from the state where the threshold voltage of the nonvolatile memory cell 1 is low to some extent (that is, the state where the electrons accumulated in the charge accumulation region 6 are small). The relationship with current is shown. Since the influence of the electrons accumulated in the charge accumulation region 6 is small, the peak current is smaller than that in FIG. Since erasing proceeds with time, the erasing current gradually decreases as in FIG.

  FIG. 1 illustrates the configuration of a flash memory. The flash memory 20 has a memory array (ARY) 21 in which a plurality of nonvolatile memory cells 1 of FIG. FIG. 1 representatively shows two pieces. In the plurality of nonvolatile memory cells 1 arranged in matrix, the selection gate 10 is connected to the selection gate line CG, the memory gate 8 is connected to the memory gate line MG, the source 3 is connected to the source line SL, and the drain 4 is connected to the bit line BL. The The X address decoder (XDEC) 22 decodes the X address signal input to the address buffer (ADB) 23. The selection gate driver circuit (CGDRV) 24 selectively drives the selection gate line CG according to the decoding result. In the read operation and the verify operation, the nonvolatile memory cell 1 is selected by selective driving with respect to the selection gate line CG. A write / erase decoder (PEDEC) 25 selects a memory gate line MG and a source line SL in writing and erasing. The selection at the time of the write operation uses the result of decoding by the X address decoder 22 via the selection gate line CG. Selection during the erase operation is performed based on the instruction information of the erase block to be erased. The driver circuit (PEDRV) 27 drives the memory gate line MG and the source line SL based on the selection signal output from the write / erase decoder 25.

  A sense latch (SL) and a data register circuit (DREG) 30 are connected to the bit line BL. The sense latch (SL) detects and holds the storage information read from the nonvolatile memory cell 1 to the bit line BL. The data register (DREG) is used to hold externally supplied write data and memory cell storage information to be saved before erasure, and the held data is used to control the bit line BL level in a write operation. The The sense latch and data register circuit 30 is connected to a data input / output buffer (DTB) 32 via a Y selection circuit (YG) 31 and can interface with a data bus 33D included in an external bus 33. In the read operation, the Y selection circuit 31 selects the read data latched in the sense latch (SL) according to the address decode signal output from the Y address decoder (YDEC) 34. The selected read data can be output to the outside via the data input / output buffer 32. In the write operation, the Y address decoder 34 controls which bit line BL the write data supplied from the data input / output buffer 32 is associated with and latched in the data register (DREG).

  The address signal is supplied from the address bus 33A of the external bus to the address buffer 23, and is supplied from the address buffer 23 to the X address decoder 22 and the Y address decoder 34. The booster circuit (VPG) 35 generates high voltages VPP1, VPP2,..., VPPi such as 5V, −5V, 8V, etc. necessary for reading, erasing and writing based on the external power sources Vdd and Vss.

  The control circuit (CONT) 36 performs a control sequence of a read operation, an erase operation, a write operation, and a switching control of an operation power source according to control information set in the control register (CREG) 37. The operation power supply switching control is control that appropriately switches the operation power supply of the driver circuits 24 and 27 according to the operation mode in accordance with the read operation, the erase operation, and the write operation.

  FIG. 6 shows a detailed example of the memory array and the write / erase decoder. In the figure, the memory array includes a plurality of nonvolatile memory cells MM00 to MMxy arranged in a matrix. The nonvolatile memory cells MM00 to MMxy have the same device structure as the nonvolatile memory cell 1. The selection gates 10 of the nonvolatile memory cells MM00 to MMxy are connected to the corresponding selection gate lines CG0 to CGy in units of rows, and the sources 3 of the nonvolatile memory cells MM00 to MMxy are connected to the corresponding source lines SL0 to SLy in units of rows. The drains 4 of the nonvolatile memory cells MM00 to MMxy are connected to the corresponding bit lines BL0 to BLx in units of columns. One row of nonvolatile memory cells is called a sector. For the nonvolatile memory cells MM00 to MMxy, an erase block having an erase unit of nonvolatile memory cells for 4 sectors and an erase block having an erase unit of nonvolatile memory cells for 1 sector are allocated. The memory gate 8 of the nonvolatile memory cell is commonly connected to the memory gate line MG in units. The erase blocks EBLK0 for four sectors, which are representatively shown in FIG. 6, are commonly connected to the memory gate line MG0, and the erase blocks EBLKm for one sector are commonly connected to the memory gate line MGm.

  The driver circuit (PEDRV) 27 includes an output inverter 40 and a level conversion circuit (LVSFT) 41 corresponding to each of the source lines SL0 to SLy and the memory gate lines MG0 to MGm. The output power of the output inverter 40 is switched according to the operation mode of erasing, writing, and reading. A level conversion circuit (LVSFT) 41 converts the input signal from the previous stage into a signal level corresponding to the operating power supply of the output inverter 40. The driver circuit (PEDRV) 27 uses a high voltage MOS transistor in relation to its operating power supply.

  The write / erase decoder (PEDEC) 25 includes an output inverter 42 whose output is coupled to the level conversion circuit 41, a selector 46 including three NAND gates (NANDs) 43 to 45, and a selection timing control circuit (TCNT) 47. And a decoding logic (DECLCG) 48. mgsel0 to mgselm are selection signals for the memory gate lines MG0 to MGm, and those corresponding to the selection signals transmitted through the selection gate lines CG0 to CGy are set to the selection level. prog is an instruction signal for the write operation, and slsel0 to slsely are selection signals for the source lines SL0 to SLy in the write operation. In the write operation, the corresponding source line is set to the selection level based on the selection signal transmitted through the selection gate lines CG0 to CGy, and the write operation can be performed in units of sectors.

  erase is an instruction signal for the erase operation, and eraseblock 0 to eraseblockm are selection signals for the erase blocks EBLK0 to EBLKm. Erase block selection signals eraseblock 0 to eraseblockm are set to a selection level in accordance with erase block designation information supplied from CREG 37 to DECLCG 48. Count0 to count3 are selection signals for the source lines SL4i, SL4i + 1, SL4i + 2, and SL4i + 3 (i = 0 to n) in the erase block during the erase operation.

  For example, in the erase operation, the memory gate control line selection signal mgsel0 is set to high level (H), the memory gate line MG0 is set to -5V, the erase block selection signal eraseblock0 is set to high level (H), and the erase operation instruction signal erase is set to high level. (H) When the source line selection signal count0 in the erase block is set to the high level (H), as illustrated in FIG. 6, the memory gate line MG0 of the memory array 21 is set to −5V, and the source line SL0 Is set to 5 V, and an erase pulse is applied to the nonvolatile memory cells MM00 to MMx0 in the sector SCT0. As the selection signal sequentially activated is changed to count0, count1, count2, and count3, the sector to which the erase pulse is applied is sequentially switched to SCT0, SCT1, SCT2, and SCT3. In this way, it is possible to apply a high voltage pulse for hot hole injection by shifting the timing in units of sectors in the erase block.

  FIG. 7 shows a specific example of the selection timing control circuit (TCNT) 47. The selection timing control circuit 47 includes a counter circuit (COUNT) 50 that forms the selection signals count0 to count3, and a counter control circuit (CUCNT) 51 that controls change timings of the plurality of selection signals count0 to count3. The counter circuit 50 includes a plurality of storage stages, for example, D-type flip-flops (FF) 50A to 50D that perform a shift operation in synchronization with the change of the shift clock SCLK, and outputs the flip-flops 50A to 50D. Are the plurality of selection signals count0 to count3.

  The counter control circuit 51 includes an oscillator (OSC) 52, a frequency divider (DIV) 53 that divides the output of the oscillator 52 to form a plurality of frequency-divided clock signals, and a plurality of frequency dividers output from the frequency divider circuit. An erase pulse width selector (EPWS) 55 for selecting one of the clock signals by the erase pulse width selector signal 54 and the first stage flip-flop of the counter circuit 50 based on the divided clock signal selected by the erase pulse width selector 55 A pulse generation circuit (PGEN) 56 for generating an erase pulse EPLS to be supplied to the group 50A and one of a plurality of frequency-divided clock signals output from the frequency divider 53 are selected by an erase pulse shift amount selector signal 57. And an erase pulse shift amount selector (EPSS) 58 for selecting the cycle of the shift clock SCLK.

  8 and 9 illustrate waveforms of the selection signals count0 to count3 that are formed in accordance with the cycle of the shift clock SCLK and the pulse width of the erase pulse EPLS. In each figure, the erase pulse shift amount SFT is one cycle of the shift clock SCLK. To change the shift amount SFT, the cycle of the shift clock may be changed. In FIG. 8, the pulse width PW1 of the erase pulse EPLS is one cycle of the shift clock SCLK. As a result, the selection signals count0 to count3 are sequentially pulse-changed in a non-overlapping manner. In FIG. 9, the pulse width PW2 of the erase pulse EPLS is four periods of the shift clock SCLK. As a result, the selection signals count0 to count3 are sequentially pulse-changed by four periods of the shift clock SCLK with an overlap shifted by one period of the shift clock SCLK.

  As described above, depending on the erase pulse width selected by the erase pulse width selector 55 and the erase pulse shift amount selected by the erase pulse shift amount selector 58, the selection signals count0 to count3 are set to be non-overlapping or overlapping. Along with the selection, the overlap amount can be variably selected.

  10 and 11 show timing charts of the erase operation in the erase block EBLK0 having the circuit configuration of FIG. In order to erase the nonvolatile memory cells MM00, MMx0, MM01, MMx1, MM02, MMx2, MM03, MMx3 of the erase block EBLK0, for example, 0V is applied to the selection gate lines CG0, CG1, CG2, CG3, and the bit lines BL0, For example, BLx is set to open. Next, the erase signal erase is set to high level (H), and then the selection signal eraseblock0 is set to high level (H) to select the erase block EBLK0. Next, the selection signal mgsel0 is set to a high level (H), and, for example, −5 V is applied to the memory gate line MG0. Thereafter, the signal count0 is set to the high level (H), for example, 5V is applied to the source line SL0, and the nonvolatile memory cells in the erase sector SCT0 are erased. After a certain time, the signal count0 is set to low level (L), and the voltage of the source line SL0 is set to 0V. Next, the signal count1 is set to a high level (H), for example, 5 V is applied to the source line SL1, and the nonvolatile memory cell in the erase sector SCT1 is erased. Similarly, the signals count2 and count3 are pulse-changed to sequentially erase the nonvolatile memory cells in the erase sector SCT2 and the erase sector SCT3. The time of the high level (H) period of the signals count0 to count3 is the erase pulse width, and the time difference between the rise of the signal count and the rise of the next signal count + 1 signal, for example, the time difference between the rise time of count0 and the rise time of count1 is erased. It is defined as the amount of pulse shift. The total sum of erase currents flowing through the source lines SL0, SL1, SL2, SL3, and Sly during erasing is defined as the total source current.

  FIG. 10 shows a timing chart when the erase pulse width and the erase pulse shift amount are equal. In this case, a period in which the voltages of the source lines SL0, SL1, SL2, and SL3 are 5V, that is, a selection period does not overlap. Therefore, as shown in the figure, the peak current of the total source current is equal to the peak current of each source line.

  FIG. 11 shows a timing chart when the erase pulse width is longer than the erase pulse shift amount. In this case, there is an overlapping period among the selection periods of the source lines SL0, SL1, SL2, and SL3. Therefore, the peak current of the total source current becomes the largest during the period when all the source lines SL0, SL1, SL2, and SL3 are selected. However, since the selection periods of the source lines SL0, SL1, SL2, and SL3 are overlapped, the erase time can be shortened. In FIG. 11, the ratio between the erase pulse width and the erase pulse shift amount is 4: 1, but the present invention is not limited to this.

  FIG. 12 shows an example of the erase flow. In this erase flow, the first erase is performed according to the timing chart of FIG. 10, that is, the erase pulse width and the erase pulse shift amount are set equal (S1, S2). Next, it is verified whether all the areas to be erased have been erased (S3). If the erasing is not completed, the second erasing is performed according to the timing chart of FIG. 11, that is, the erasing pulse width is set longer than the erasing pulse shift amount (S4, S5). Next, it is verified whether all the areas to be erased have been erased (S6). The third and subsequent times are the same as the second time.

  In the first erase in steps S1 and S2, many electrons are injected into the charge storage region 6 as shown in FIG. Accordingly, since a large current flows from the source 3 to the substrate 16 in the erase operation, the timing chart of FIG. 10 is applied to suppress the peak current of the total source current. By suppressing the peak current of the source total current, the current supply capability of the power supply circuit 35 that supplies the source current can be suppressed. Since the current supply capability of the power supply circuit that supplies the source current can be suppressed, the area of the power supply circuit can be reduced, which can contribute to the miniaturization of the chip.

  In the second and subsequent erases, the number of electrons held in the charge storage region 6 is reduced as shown in FIG. Accordingly, since the current flowing from the source 3 to the substrate 16 is small, the peak current of the total source current can be suppressed even when the timing chart of FIG. 11 is applied. Furthermore, since the source line selection timing (erase pulse application timing) is overlapped, the erase time can be shortened.

  FIG. 13 shows an overall configuration of a microcomputer in which the flash memory 20 is on-chip. The microcomputer 60 is not particularly limited, but is formed on a single semiconductor substrate (semiconductor chip) such as single crystal silicon by a CMOS integrated circuit manufacturing technique. The microcomputer 60 includes a central processing unit (CPU) 61, a RAM 62 as a volatile memory, a flash memory (FLASH) 20 as a nonvolatile memory, a bus state controller (BSC) 63, and an input / output such as an input / output port circuit. A circuit (I / O) 64 is provided, and these circuit modules are connected to an internal bus 66. The internal bus 66 includes signal lines for address, data, and control signals. The CPU 61 includes an instruction control unit and an execution unit, decodes the fetched instruction, and performs arithmetic processing according to the decoding result. The flash memory 20 stores an operation program and data for the CPU 61. The RAM 62 is a work area or a temporary data storage area for the CPU 61. The operation of the flash memory 20 is controlled based on the control data set in the control register 37 by the CPU 61. The bus state controller 63 controls access via the internal bus 66, the number of access cycles for external bus access, wait state insertion, bus width, and the like.

  In FIG. 13, a circuit other than the region 69 surrounded by a two-dot chain line means a circuit portion constituted by a MOS transistor having a relatively thin gate oxide film. The circuit in the region 69 is a circuit portion constituted by a high voltage MOS transistor having a relatively thick gate oxide film. For example, a region where the PEDRV 27 or the like is formed in the flash memory 20 is a high voltage MOS transistor circuit portion, and a region where the CGDRV 24 or the like is formed in the flash memory 20 is a MOS transistor circuit portion having a thin gate oxide film.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, in FIG. 7, the erase pulse shift amount is one cycle of the shift clock SCLK, but is not limited to one cycle. In this case, in FIG. 7, a flip-flop may be added before the flip-flop 50A, or another flip-flop may be inserted between each of the flip-flops 50A to 50D.

  In the erase flow of FIG. 12, the erase pulse width and the erase pulse shift amount are set equal only for the first erase, but such setting is not limited to the first. Erasing may be performed several times with the erasing pulse width and the erasing pulse shift amount set equal, and subsequent erasing may be performed by setting the erasing pulse width longer than the erasing pulse shift amount. Further, the erase pulse width, erase pulse shift amount, memory gate voltage, and source voltage may be arbitrarily changed according to the number of times of erase.

  Further, the nonvolatile memory cell is not limited to the split gate structure. The charge storage region is not limited to an insulating trap region such as silicon nitride, and may be a floating nonvolatile memory cell including a conductive charge storage region such as polysilicon. .

  The present invention can be widely applied to flash memories and microcomputers equipped with flash memories.

Claims (9)

A plurality of nonvolatile memory cells in which a threshold voltage is increased by injection of electrons into the charge storage region and a threshold voltage is decreased by injection of hot holes into the charge storage region;
In the operation of lowering the threshold voltage of the non-volatile memory cell, hot holes generated by applying a first high voltage to the source region of the non-volatile memory cell and causing a current to flow to the well region are formed in the non-volatile memory. Injecting into the charge storage region by applying a second high voltage to the gate electrode of the cell;
In a state where the second high voltage is applied to the gate electrodes of the plurality of nonvolatile memory cells selected as the hot hole injection targets, the first high voltage is applied to each of the source electrodes. a high voltage, a control circuit that can be repeated a plurality of times until the process of indicia pressurized by shifting the application timing reaches a desired threshold voltage,
Wherein the control circuit, the timing of applying the first high voltage to each part of the plurality of nonvolatile memory Roh after in emission overlap, if erasing is not completed partially Nonvolatile semiconductor memory that performs overlapping control . The nonvolatile semiconductor memory according to claim 1 , wherein the control circuit is capable of selecting a degree of partial overlap of the first high voltage .   A semiconductor device having a nonvolatile semiconductor memory,
  The nonvolatile semiconductor memory includes an array of nonvolatile memory cells each having a charge storage region and a memory gate region insulated on a channel formation region sandwiched between source / drain regions, and
  A first wiring in which one source / drain region of the nonvolatile memory cell is coupled;
  A second wiring in which the other source / drain region of the nonvolatile memory cell is coupled;
  A third wiring to which a memory gate region of the nonvolatile memory cell is coupled;
  A control circuit that performs control for injecting electrons into the charge storage region of the nonvolatile memory cell to increase the threshold voltage, and performs control for injecting hot holes into the charge storage region to lower the threshold voltage. ,
  In the control for lowering the threshold voltage, hot holes generated by applying a high voltage pulse for hot hole injection to the first wiring and causing a current to flow to the channel formation region are formed in the third wiring. Injecting into the charge storage region by applying a high voltage of 2;
  The control circuit is configured to apply a portion of each of the control circuits in a state where the second high voltage is applied to the third wiring connected to the plurality of nonvolatile memory cells selected as the hot hole injection target. The process of applying the high voltage pulse for injecting the hot holes by shifting the timing to the first wiring connected to the nonvolatile memory cell can be repeated a plurality of times until the desired threshold voltage is reached. Then, after applying the timing in a non-overlapping manner, a semiconductor device that performs control to partially overlap if erasing is not completed. 4. The semiconductor device according to claim 3 , wherein the control circuit is capable of selecting a degree of partial overlap of the high voltage pulse . The array includes a plurality of non-volatile memory cells arranged in a matrix.
The plurality of non-volatile memory cells arranged in a matrix share the first wiring in row units, share the second wiring in column units, share the third wiring in multiple row units,
The control circuit applies a first high voltage pulse to the selected third wiring, and the first wiring is connected to the first wiring connected to the plurality of nonvolatile memory cells sharing the selected third wiring. The semiconductor device according to claim 3, wherein the second high voltage pulse is applied while shifting the timing between the wirings . The control circuit includes: a counter circuit that forms a plurality of selection signals for selecting a plurality of first wirings related to a plurality of rows of nonvolatile memory cells sharing the third wiring; and a plurality of the selection signals A counter control circuit for controlling the change timing,
The counter circuit includes a plurality of storage stages that perform a shift operation in synchronization with a change of a shift clock in series, and outputs of the plurality of storage stages serve as the plurality of selection signals,
The counter control circuit includes a pulse generation circuit that generates a pulse to be supplied to the first stage of the counter circuit, a pulse width selection circuit that enables selection of a width of a pulse generated by the pulse generation circuit, and a cycle selection of the shift clock 6. A semiconductor device according to claim 5 , further comprising: a shift amount selection circuit that makes the shift amount of the pulse variable . In the nonvolatile memory cell, a selection gate region is formed on the channel formation region on the source / drain region side to which the second wiring is connected via an insulating film, and the selection gate region and the memory gate region are separated. 6. The semiconductor device according to claim 5 , having a split gate structure . 8. The semiconductor device according to claim 7, wherein a gate breakdown voltage viewed from the select gate region is lower than a gate breakdown voltage viewed from the memory gate region . 9. The semiconductor according to claim 8, further comprising a controller for controlling access to the nonvolatile semiconductor memory, wherein a gate breakdown voltage viewed from the selection gate region is the same as a gate breakdown voltage of a gate insulating field effect transistor constituting the controller. apparatus.

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