WO2006068636A1 - Ecran plasma grande surface - Google Patents

Ecran plasma grande surface Download PDF

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Publication number
WO2006068636A1
WO2006068636A1 PCT/US2004/042466 US2004042466W WO2006068636A1 WO 2006068636 A1 WO2006068636 A1 WO 2006068636A1 US 2004042466 W US2004042466 W US 2004042466W WO 2006068636 A1 WO2006068636 A1 WO 2006068636A1
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WO
WIPO (PCT)
Prior art keywords
plasma
large area
plasma display
sustain electrodes
pixels
Prior art date
Application number
PCT/US2004/042466
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English (en)
Inventor
Munisamy Anandan
Original Assignee
Munisamy Anandan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Munisamy Anandan filed Critical Munisamy Anandan
Priority to PCT/US2004/042466 priority Critical patent/WO2006068636A1/fr
Publication of WO2006068636A1 publication Critical patent/WO2006068636A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J11/00—Gas-filled discharge tubes with alternating current induction of the discharge, e.g. alternating current plasma display panels [AC-PDP]; Gas-filled discharge tubes without any main electrode inside the vessel; Gas-filled discharge tubes with at least one main electrode outside the vessel
    • H01J11/10—AC-PDPs with at least one main electrode being out of contact with the plasma
    • H01J11/18—AC-PDPs with at least one main electrode being out of contact with the plasma containing a plurality of independent closed structures for containing the gas, e.g. plasma tube array [PTA] display panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/313—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being gas discharge devices

Definitions

  • the present invention relates to a very large area display for use in outdoor and stadium environment employing plasma display technology. More particularly, the present invention utilizes sub-blocks of tiles of plasma pixels that are specially designed to have high luminous efficiency.
  • Tsutae Shinoda Manabu Ishimoto, Hitoshi Yamada, Akira Tokai and Kenji Awamoto- "New approach for wall display with fine plasma tube array technology"- SID 02 Digest of Technical papers, pp. 1072-1075, SID 2002 International Symposium vol.XXXIII, No.2, May 2002
  • Tsutae et.al described a large stack of linear plasma tubes as light generating pixel elements for very large area out door and indoor stadium type application. Electrodes were placed external to the plasma tubes and plasma was confined through the positioning of electrodes. In this configuration plasma diffused out of the confined region and further discrete tubes were bulky.
  • the thickness of the display was high and the display was bulky with discrete components. In some of them, the tiled concept was only at the final surface with increased thickness and bulkiness behind the tiles.
  • a large area plasma display incorporating planar plasma pixels with a novel design for increasing the luminous efficiency of the large area plasma display, coupled with ease of manufacturing of pixels sizes ranging from 6 mm x 6 mm to 100 mm x 100 mm and large area display sizes, comprising the large pixels sizes, ranging from 13' x 10' to 210' x 160' can be accomplished.
  • the novel plasma pixels can be manufactured in large volume and individually assembled to derive a large area plasma display or multi-pixels can be volume manufactured in 'tiles' and 'tiles' can be assembled to generate very large area displays.
  • Luminance in the range of 1000 to 5000 nits can be obtained incorporating these pixels in the display and thus 'sunlight readable' displays for outdoor application can be realized.
  • the current invention of the large area display, incorporating the plasma pixels employs a hybrid technology that combines the plasma display technology and the fluorescent lamp technology but with a major new design to increase the luminous efficiency of the display.
  • the pixel comprises two plasma sustain electrodes, herein after called sustain electrodes, buried in a dielectric layer, on one substrate and an address electrode, also buried in a dielectric layer, on another substrate with phosphor coating on the substrate containing the address electrode. Between the sustain discharge electrodes is disposed a 'dielectric barrier' that creates a long positive column of plasma that is responsible for increasing the efficiency of the light out put.
  • the pixel is filled with mercury and Argon gas or mixtures of Ar and Krypton or Argon and Helium.
  • the inert gas and mercury When suitable amplitude of voltage with appropriate frequency is applied between sustain electrodes, the inert gas and mercury will pass an electric current as a result of electrical breakdown and creation of plasma, causing the mercury to give off ultraviolet rays (253.7 nm and 185 nm).
  • the plasma length is elongated by the presence of 'dielectric barrier', thus increasing the yield of ultraviolet rays.
  • the ultraviolet rays cause excitation of phosphor resulting in light output from the pixel.
  • Each pixel is fabricated as a device of dimension of the order of an inch and sealed with a frit seal. Hence the manufacturing becomes easy with simple machineries.
  • Large area plasma display is generated by assembling these pixels in rows and columns. Alternately a group of pixels can also be fabricated on single panel in a 'tiled' configuration and the 'tiles' can be assembled to generate a large area display. Addressing of the display is by using the same scheme as employed in AC plasma displays.
  • the novel pixel design enhances the luminous efficiency and readily manufacturable together with the large area plasma display derived from these pixels.
  • a further object of this invention is to provide a 'dielectric barrier' to the sustain discharge between sustain electrodes to augment the luminous efficiency of plasma pixels.
  • Yet another object of this invention is to incorporate dielectric reflective layer under the phosphor layer within a pixel to reduce visible and UV light losses.
  • Another object of this invention is to provide group of pixels in a single sealed panel called, 'tile' and assemble plurality of 'tiles' to fabricate large area plasma display for indoor and outdoor display system.
  • a further object of this invention is to eliminate the huge investment costs on process equipment required for handling large area substrates, using conventional method to manufacture large area plasma displays.
  • Fig. 1 is the plan view of a large area display of a prior art incorporating in every pixel three cold cathode discrete fluorescent lamps of red, blue and green color;
  • Fig. 2 is an isometric view of a coaxial cylindrical fluorescent lamp, according to a prior art, that forms part of the fraction of a pixel of a large area display;
  • Fig. 3 is the plan view of a large area display employing plurality of end-on position of fluorescent lamp as depicted in Fig. 2;
  • Fig. 4 is an exploded view of a medium sized (60" diagonal) plasma display of prior art showing the pixels processed on two substrates;
  • Fig. 1 is the plan view of a large area display of a prior art incorporating in every pixel three cold cathode discrete fluorescent lamps of red, blue and green color;
  • Fig. 2 is an isometric view of a coaxial cylindrical fluorescent lamp, according to a prior art, that forms part of the fraction of a pixel of a large area display;
  • FIG. 5 is the side-view of discrete cylindrical plasma tube with plasma sustain- electrodes and address electrode defining a pixel on the tube;
  • Fig. 6 is the front view of a large area plasma display containing plurality of plasma tubes depicted in Fig. 5;
  • Fig. 7 is the isometric view of one of the substrates of a pixel, containing two sustain electrodes, according to a prior art, covered by a dielectric layer;
  • Fig. 8 is the isometric view of plasma path between two sustain electrodes shown in Fig. 7;
  • Fig. 9 is the isometric view of one of the substrates of a pixel, according to the present invention, where there is a dielectric barrier between the sustain electrodes;
  • Fig. 6 is the front view of a large area plasma display containing plurality of plasma tubes depicted in Fig. 5;
  • Fig. 7 is the isometric view of one of the substrates of a pixel, containing two sustain electrodes, according to a prior art,
  • Fig. 10 is the isometric view of one of the substrates of a pixel, with an alternate split structure of sustain electrodes;
  • Fig. 11 is the isometric view of one of the substrates of a pixel with an alternate dielectric barrier, between two sustain electrodes, integral to the substrate;
  • Fig. 12 is the isometric view of plasma path between two sustain electrodes contained on the substrate depicted in Fig. 9;
  • Fig. 13 is the isometric view of one of the substrates of a pixel, according to the present invention, containing address electrode covered by a dielectric layer followed by a dielectric reflective layer followed by a phosphor layer and finally a peripheral seal layer;
  • Fig. 11 is the isometric view of one of the substrates of a pixel with an alternate split structure of sustain electrodes
  • Fig. 11 is the isometric view of one of the substrates of a pixel with an alternate dielectric barrier, between two sustain electrodes, integral to the substrate
  • Fig. 12 is the isometric
  • Fig. 14 is the exploded view of two substrates forming a pixel, according to the present invention, depicting the sustain electrodes with a dielectric barrier on one substrate and address electrode on the other substrate;
  • Fig. 15 is the cross sectional view of a sealed pixel, comprising the two substrates depicted in Fig. 14, with a mercury dispensing arrangement;
  • Fig. 16 is the cross sectional view of a processed pixel cell, according to the present invention, showing various parts of the pixel, including the path of plasma;
  • Fig. 17 is the isometric view of one of the substrates of a pixel with alternate design, according to the present invention, of sustain electrodes and dielectric barrier between two sustain electrodes;
  • Fig. 18 is the isometric view of one of the sustain electrodes depicted in Fig.
  • Fig. 19 is the isometric view of one of the substrates of a pixel with another alternate design of dielectric barrier between two sustain electrodes;
  • Fig. 20 is the cross sectional view of plurality of pixels sealed between two substrates, according to the present invention, with mercury dispensing arrangement;
  • Fig. 21 is the plan view of plurality of pixels sealed between two substrates, according to the present invention;
  • Fig. 22 is the isometric view of the assembly of single pixel, according to the present invention, with lead out for electrical connection;
  • Fig. 23 is the isometric view of the assembly of discrete pixels, fabricated according to the present invention, on a frame body to form a large area plasma display;
  • Fig. 20 is the cross sectional view of plurality of pixels sealed between two substrates, according to the present invention, with mercury dispensing arrangement;
  • Fig. 21 is the plan view of plurality of pixels sealed between two substrates, according to the present invention;
  • Fig. 22 is the isometric view of the assembly of single
  • Fig. 24 is the isometric view of an assembly frame showing the relief holes for connecting leads on the discrete pixel assembly
  • Fig. 25 is the isometric view of the assembly of two frames depicted in Fig. 23 and Fig. 24 with top electrical connections of discrete pixel assembly
  • Fig. 26 is the exploded view of the final assembly of the sub-assembly as depicted in Fig. 25 with a protective cover assembly
  • Fig. 27 is the isometric upside-down view of assembly of plurality of 'tiles' containing plurality of pixels processed in each 'tile', according to the present invention, with top tip-off tabulation.
  • Fig. 1 shows the plan view of a large area display 01 incorporating discrete cold cathode fluorescent lamps, according to a prior art (US Patent 6,452,326), of red 1 , blue 2 and green 3 color, assembled in one pixel in the format of matrix 4 with 3 x 3 pixels, as an illustration.
  • the pixels can be as many as 640 x 480.
  • the cold cathode fluorescent lamps are U-type for accommodating inside the pixel. The construction is bulky and the pixel luminance will not be uniform for three colors because the three color lamps have different fill factors.
  • Fig. 2 shows a discrete cylindrical fluorescent lamp 02, according to a prior art (US Patent 5,668,443) with its external outer electrode 22 and inner electrode 21 operated through an alternating voltage source 28.
  • the outer electrode 22 has an insulation layer 23 followed by a phosphor layer 24.
  • a similar insulation layer and phosphor layer (not shown in Fig. 2) are formed on the coaxial inner electrode 25.
  • the plasma formed in the coaxial region produces UV that excites the phosphor layer.
  • the resulting visible light 26 escapes through an optical lens 27.
  • Fig. 3 is the plan view of a large area display 03 formed by the plurality of discrete lamps shown in 2 x 2 matrix 34, as an illustration.
  • the number of pixels can be as many as 640 x 480. Every pixel in the illustration has nine of the lamps 31 and they are connected in parallel with outer electrodes 32 bussed together and inner electrodes 33 bussed together.
  • the display derived from the use of discrete lamps as shown in Fig. 2 is bulky and the depth of the display is increased due to the height of the discrete lamp. The lamp itself is inefficient due to the light loss as a result of multiple reflections inside the coaxial geometry.
  • 0016 Fig. 4 illustrates another prior art in which a large area display 04 is built on two large substrates through integral processing.
  • the bottom substrate 41 contains plurality of address electrodes 44 buried under a dielectric layer 43 followed by phosphor layer 46 between the ribs 45 that isolate pixels from 'cross talk'.
  • the top substrate 42 contains sets of sustain electrodes 49 buried in a dielectric layer 48 followed by an electron secondary emission enhancement layer 47.
  • sustain electrodes 49 In a regular display there is a momentary gas discharge established between address electrode 44 and one of the sustain electrodes 49 and the gas discharge is sustained by sustain electrodes 49.
  • the UV from the discharge excites the phosphor and the resulting visible light output enables the display.
  • This art suffers from the fact that large area displays, ranging to several tens of feet in diagonal, are difficult to make because of handling of very large substrate sizes and the expensive special purpose machinery needed to handle these substrate sizes.
  • Fig. 5 illustrates a plasma tube 05, the basic light emitting element, of a large area plasma display (Tsutae Shinoda et.al, SID' 02 Digest of Technical papers) that has plurality of sustain electrodes 53 vertical to the tube axis along its length, outside the tube, and an address electrode 52, outside the tube, parallel to the axis of the tube.
  • Plasma 55 is formed between sustain electrodes 53 when suitable voltage is applied between the sustain electrodes.
  • the plasma diffuses 54 laterally along the axis of the tube thus not confining to the region between the sustain electrodes and resulting in cross-talk and low resolution. This is the drawback in this art.
  • Fig. 8 shows the substrate 08 depicting the curved path of plasma 82 between the sustain electrodes 81 when sufficient voltage is applied between the sustain electrodes to create a gas discharge.
  • Fig. 10 presents substrate 010 with an alternate sustain electrodes 103 with split structure formed on glass plate 101 on either side of a dielectric barrier 102. Both the sustain electrodes and dielectric barrier are coated with a thin layer 104 consisting of a thin dielectric layer followed by a secondary electron emissive layer.
  • the split sustain electrode arrangement will give the advantage of well spread out uniform plasma.
  • Fig. 11 presents an alternate substrate 011 with a corrugation 112, according to the present invention, that is integral to the glass plate 111.
  • the corrugation creates a 'bump' for the discharge path between sustain electrodes 113 which are coated with a dielectric layer 115 followed by electron secondary emission enhancement layer 116.
  • Fig. 12 shows the substrate 012 with a plasma path 124 created as a result of application of suitable momentary plasma initiation voltage between address electrode and one of the plasma sustain electrodes and then maintaining an alternating voltage between the sustain electrodes 122 which are covered by a layer 123 consisting of a dielectric layer and an electron secondary emission enhancement layer.
  • the presence of dielectric barrier 125, laid on glass plate 121, makes the plasma path more curved upwards compare to the plasma path in Fig. 8.
  • the increase in the path length of plasma increases the luminous efficiency of the plasma pixel and consequently the luminous efficiency of large area plasma display that comprises the plurality of these plasma pixels.
  • Fig. 13 presents various processed parts of substrate 013, according to the present invention, that contains starting from the glass plate 131, an address electrode 132 followed by multi-layer 133 comprising a thin dielectric layer 137 followed by a dielectric reflective layer 136 followed by a final phosphor layer 135. There is an evacuation and gas filling-hole 138 and the substrate is finally applied with a peripheral sealing frit layer 134.
  • the address electrode 132 can be made by screen printing 'Dupont's' silver paste 7713 or 'Dupont's' Fodel DC201 and firing to a temperature of 550 C.
  • An alternate material is a thin film stack of Cr-Cu-Cr or Cr-Al-Cr through vacuum deposition.
  • the thickness of silver electrode is in the range of 12 micron to 25 micron and if formed by thin film deposition the thickness of the electrode is in the range of 1000 nm to 2000 nm and the width being in the range of several mm.
  • a thin dielectric layer 137 is printed over the address electrode and processed in the manner described before for the dielectric layer on sustain electrodes.
  • the reflective dielectric layer 136 can be obtained through the process of screen printing Aluminum Oxide paste or spraying the suspension containing Aluminum Oxide and firing to a temperature of 550 C.
  • An alternate method is by printing a low melting glass paste mixed with Titanium dioxide or Aluminum Oxide or SrTiO3 or ZrO2 and firing to a temperature of 550 C.
  • Still another alternative method is to screen print the reflective Titanium Dioxide or Aluminum Oxide or SrTiO3 or ZrO2 mixed glass paste as a single layer to replace layer 136 and 137 and firing to a temperature of 550 C to obtain a thickness in the range of 25 to 40 microns.
  • the final phosphor layer is obtained by employing phosphor pastes of desired color and screen printing and firing to a temperature of 500 C to result in a thickness range of 12 - 18 microns.
  • the phosphor material is Zn2 SiO4 : Mn for green, BaMgAMO 017 :Eu for blue and Y2 03 :Eu for red. To derive green, blue and red pixels these phosphor materials can be used.
  • Alternate materials for green are YB03 :Tb and BaAH 2 019 :Mn and for red (Y, Gd)BO3 :EU and YB03 :Eu.
  • An alternate method for phosphor deposition is by spraying a suspension of phosphor.
  • the peripheral seal layer can be deposited employing a rectangular glass frame, coating the frame with low melting glass frit paste and placing the coated frame on the glass plate 131 and pre-glazing to a temperature of 450 C.
  • Fig. 14 depicts the assembly 014 of bottom substrate 141 with top substrate 148 for alignment prior to sealing the two substrates.
  • the sustain electrodes 146 are orthogonal to the address electrode 142.
  • Within the seal frame 144 are the phosphor layer 143 with its backing layers of dielectric and reflective dielectric layer (not shown in Fig. 14).
  • the key dielectric barrier 147 with the transparent dielectric over-layer 145, including the electron secondary emission enhancement layer (not shown in Fig. 14) are contained on the top substrate 148.
  • Fig. 15 shows the cross section 015 of a single pixel in sealed configuration with a mercury reservoir 153 appended to the bottom of the single pixel panel.
  • the top substrate 151 is sealed to the bottom substrate 157 through the frit seal 152.
  • the frit seal is made employing a low melting glass frit and sealing it around 500 C.
  • the mercury reservoir 153 with its mercury dispensing getter 154 can be obtained form 'Saes' getters corporation, containing Zirconium and mercury.
  • the mercury reservoir is attached by flame sealing, after frit sealing the single pixel panel.
  • the whole panel is evacuated through the exhaust tabulation 156 (not closed at this time, but shown as closed in Fig.
  • the panel assembly 015 is placed in a slotted oven to immerse only the mercury reservoir portion of the panel inside the oven slot and the temperature of the reservoir is raised to 300 C for driving the mercury droplets formed during the induction heating process to the space between the substrates 151 and 157. At the end of this process, the mercury reservoir is detached from the panel.
  • Fig. 16 is the cross section of the single pixel panel 016 after vacuum processing, gas filling and mercury filling. For the sake of simplicity several layers are omitted in this Fig. 16. For example, above the address electrode 161 , the dielectric layer, dielectric reflective layer and phosphor layer are combined and shown as a single layer 162. Similarly, over the sustain electrodes 164 and the dielectric barrier 165, thin film dielectric layer and MgO layer are combined and shown as a single layer 166. The bottom substrate 160 and top substrate 163 are sealed through a frit seal 168 and the exhaust tabulation 169 is tipped off. The path of Ar-Hg plasma 167 is formed when a sufficient magnitude of voltage is applied between the sustain electrodes 164. As can be seen the path of plasma is sufficiently curved downwards due to the presence of dielectric barrier and the substantial UV generated due to increased path length of plasma excites the phosphor that results in visible light escaping the panel upwards.
  • Fig. 17 illustrates an alternate design 017 for the sustain electrodes and dielectric barrier.
  • the substrate171 through which the visible light escapes contains rectangular hollow electrodes 172 as sustain electrodes and the dielectric barrier 174 is fixed to the substrate 171 through a glass frit 173.
  • 0030 Fig. 18 shows the details of the hollow electrodes that are used as sustain electrodes.
  • the rectangular hollow electrode 183 has two portions of external surface. One surface 181 below which is situated the hollow geometry and another surface 182 which is pinched to be flat for compatibility for peripheral seal of the single pixel panel.
  • the material of the electrodes can be an alloy of Nickel-Iron alloy called 'Alloy 42' (52% Ni and balance Fe with traces of Cr, carbon etc,) or 'Alloy 52', (52% Ni and balance Fe with traces of Cr.carbon etc.,) that are good for frit- sealing to the soft glasses.
  • External surface of the hollow electrode 181 and 182 is applied with a coating of vitreous glass frit by spraying and thermally pre-glazing to a temperature of 400 C to form a continuous layer of frit glass.
  • the horizontal axis of the hollow structure is tilted to make a small angle with the plane of the plate (172 of Fig. 17). This angle can range between 10 degrees to 45 degrees.
  • the inside of the hollow electrode can also be coated with a low work function material such as Barium oxide, or cerium oxide or lithium fluoride or mixtures of Ba, Sr and Ca oxides in the ratio of 50:40:10.
  • Fig. 19 illustrates an alternate design 019 of the dielectric barrier with plurality of dielectric rods 193 sealed in the glass plate 191 through glass frit layer 194 between hollow sustain electrodes 192.
  • This type of barrier will further increase the path length of plasma resulting in enhanced luminous efficiency of large area display.
  • An alternate design for the dielectric barrier can be the 'corrugated bump' structure shown in Fig. 10.
  • Fig. 20 depicts plurality of plasma pixels 020 formed between two substrates 201 and 202 with the frit seal 203 separating them to prevent cross-talk but still connecting them for the purpose of evacuation and gas filling (better seen in Fig. 21 ).
  • the mercury reservoir 204 with its mercury dispensing getter 205 with its support 207 and the evacuation tube 206 play the same role as in Fig. 15. In this configuration, the multiple plasma pixels between two substrates act like tiles for the large area display but the panel is still small enough for simplicity in handling.
  • Fig. 21 is the plan view 021 of Fig. 20 with the mercury reservoir detached.
  • the glass frit seal 211 is all the way around for the entire panel except for the individual pixels.
  • the glass frit seal 212 is not closed but with an opening 213 in the form of a barrier. This opening links all the pixels during evacuation and gas filling through a common hole 214.
  • the restricted opening 213 prevents crosstalk between pixels.
  • Fig. 22 illustrates the assembly 022 of a single pixel plasma panel prior to its main frame assembly.
  • the sustain electrode terminations 223 on the larger glass plate 220 are conducted to the external surface of the smaller glass plate 221 through a conductive silver epoxy 225 that contains pins 226 herein after called sustain electrode pins.
  • the address electrode termination (not shown in Fig. 22) is similarly brought to the address electrode pin 228.
  • the sealed off evacuation hole is protected by a plastic cover 224 is seen on the external surface of glass plate 221.
  • the side through which the light escapes is the bottom side of glass plate 220.
  • the dielectric barrier described in the present invention can be modified in geometry from cylindrical to oval or semi-circular or any combination and plurality of these shapes and sizes.
  • the profile of 'corrugated bump' in the substrate to make the dielectric barrier integral to the substrate can be changed and number of 'bumps' can be changed.
  • the hollow electrode described in the present invention has one electrode on each side. This can be split in to several on each side operating in parallel.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Gas-Filled Discharge Tubes (AREA)

Abstract

La présente invention à trait à un écran plasma à très grande surface pour une utilisation à l'intérieur ou à l'extérieur présentant une taille en diagonal de plusieurs pieds, incorporant une pluralité 'pavés' de pixels plasma (016) comprenant des électrodes de maintien de plasma (164) et une barrière diélectrique (165) sur un substrat (163) et une électrode d'adressage (161) sur l'autre substrat (160), les substrats étant maintenus alignés pour être en regard l'un de l'autre et orienter les électrodes de maintien de plasma, avec la barrière diélectrique, orthogonales aux électrodes d'adressage. La présence de la barrière diélectrique améliore la longueur de trajet du gaz plasma inerte au mercure (167) entraînant une génération accrue d'ultraviolet et donc de la lumière visible qui améliore l'efficacité lumineuse de l'écran plasma grande surface. Une pluralité de pixels plasma sont fabriqués dans un panneau unique, dit 'pavé', scellés hermétiquement. Les 'pavés' sont assemblés pour créer un écran plasma grande surface éliminant ainsi la nécessité d'équipements de traitement coûteux et des procédures laborieuses pour manipuler des substrats à grande surface.
PCT/US2004/042466 2004-12-20 2004-12-20 Ecran plasma grande surface WO2006068636A1 (fr)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5909083A (en) * 1996-02-16 1999-06-01 Dai Nippon Printing Co., Ltd. Process for producing plasma display panel
US6635992B1 (en) * 1998-12-01 2003-10-21 Toray Industries, Inc. Board for plasma display with ribs, plasma display and production process therefor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5909083A (en) * 1996-02-16 1999-06-01 Dai Nippon Printing Co., Ltd. Process for producing plasma display panel
US6635992B1 (en) * 1998-12-01 2003-10-21 Toray Industries, Inc. Board for plasma display with ribs, plasma display and production process therefor

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