WO2006060015A1 - Method for forming a photoresist pattern - Google Patents
Method for forming a photoresist pattern Download PDFInfo
- Publication number
- WO2006060015A1 WO2006060015A1 PCT/US2004/040237 US2004040237W WO2006060015A1 WO 2006060015 A1 WO2006060015 A1 WO 2006060015A1 US 2004040237 W US2004040237 W US 2004040237W WO 2006060015 A1 WO2006060015 A1 WO 2006060015A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor wafer
- photoresist
- heating
- desorbing
- approximately
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/16—Coating processes; Apparatus therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
Definitions
- This invention relates generally to forming a photoresist pattern, and more specifically, to removing condensable species to form a photoresist pattern.
- One common method for forming features of semiconductor devices is to form a photoresist pattern on the semiconductor device and to reproduce the pattern in underlying layers. Any defects in the photoresist pattern will be transferred to the underlying layers and may cause reduced yield. Thus, it is important that the photoresist pattern includes the desired pattern with minimal defects.
- One defect that may occur is the absence of a via or a partial via in a large dense array of vias, which undesirably reduce yield.
- Figure illustrates a process flow of forming a photoresist pattern in accordance with an embodiment of the present invention.
- SMIF Pod Standard Mechanical Interface
- a semiconductor wafer 12 is exposed to a plasma environment, which in one embodiment is an ash process 14.
- the semiconductor wafer 12 can be a wafer of any dimension (e.g., 200 or 300 millimeter wafers) and may be any type of wafer, such as monocrystalline silicon, gallium germanium, silicon-on-insulator (SOI), the like, and combinations of the above.
- the semiconductor wafer 12 can be at any stage in the manufacturing flow of semiconductor devices where a photoresist layer is used.
- the semiconductor wafer 12 can be at a stage where a photoresist layer is needed to form vias or gates.
- the semiconductor wafer 12 may have many layers and potentially even semiconductor devices formed on and within it.
- an oxygen plasma is used to remove organic and condensable species.
- This process protected against molecular airborne contamination, however, the inventors have discovered that condensable species appear to redeposit on the semiconductor wafer when the semiconductor wafer is being transported to a photolithography tool. Furthermore, even if the ash tool is part of the photolithography tool, condensable species may still be formed on the semiconductor wafer and hence it may still be desirable to desorb such species.
- the time period between the ash stage 14 and the subsequent first heating process 16 is too great (e.g., greater than approximately six hours or greater than approximately four hours) it may be desirable to repeat the ash stage 14 as too many contaminants may form on the semiconductor wafer 12 during the time the semiconductor wafer 12 is waiting after the ash stage 14.
- condensable species can be any airborne molecule that chemically interferes with the photolithography process. Condensable species can be distinguished from what is herein referred to as particles. Particles are matter than mechanically interferes with the photolithography process. Often, particles are on a semiconductor wafer because they fall from a tool or another apparatus in the manufacturing environment onto the semiconductor wafer. Condensable species include dioctyl phthalate (DOP) whose chemical formula is C 6 H 4 (COOC 8 Hn) 2 and t whose structure can be illustrated as shown below.
- DOP dioctyl phthalate
- the condensable species can include amines, such as ammonia, which has a chemical formula Of NH 3 , or n-methyl-2-pyrrolidone (NMP), which has the chemical formula C 5 H 9 NO and can be illustrate by the structure shown below.
- amines such as ammonia, which has a chemical formula Of NH 3
- NMP n-methyl-2-pyrrolidone
- condensable species can include other chemicals such as siloxanes, which have a backbone of alternating silicon and oxygen atoms.
- Organic groups such as methyl, phenyl or vinyl, may be attached to the silicon.
- Poly Di-Ethyl Siloxane is a siloxane.
- the semiconductor wafer is placed in a chemically filtered environment 10, which in one embodiment is a photolithography tool that chemically filters the air within the tool so that is purer than the environment outside the photolithography tool.
- a chemically filtered environment 10 which in one embodiment is a photolithography tool that chemically filters the air within the tool so that is purer than the environment outside the photolithography tool.
- the semiconductor wafer 12 is exposed to a first heating process 16, which can be termed a pre-bake.
- the heating process 16 occurs at a temperature greater than or equal to approximately 150 degrees Celsius or more specifically, greater than or equal to approximately 170 degrees Celsius, or even more specifically, greater than or equal to approximately 180 degrees Celsius.
- the temperature for heating is between approximately 150 to 180 degrees Celsius or more specifically, between approximately 170 and 180 degrees Celsius.
- all the heating stages herein heat the semiconductor wafer 12 using a hot plate and the prescribed temperatures are the temperatures measured at or near the hot plate.
- the length of the time for heating can be chosen based on the timing of the other stages in the process. For example, approximately 60 seconds may be desirable if the other semiconductor wafers are transported to another stage in the process after approximately 60 seconds.
- this 60 seconds is the time at which the chamber is at approximately a constant temperature; in other words, the 60 seconds does not include a ramping up and ramping down of temperature. Timing the heating process to be approximately equal to the other process stages, if possible, prevents the semiconductor wafer 12 from having to wait for the next stage after the heating stage and also prevents the heating process from slowing down the overall process by being the bottle neck (i.e., the slowest stage) in the process.
- a cooling stage 17 may be needed.
- the photolithography tool used may have a robotic arm that can be used to remove or place the semiconductor wafer 12 in a hot chamber (a "hot robotic arm") and another robotic arm that can be used to remove or place the semiconductor wafer 12 in a cool chamber (a "cool robot arm”).
- the hot robotic arm can enter the chamber for the heating stage 16
- the photolithography tool may prevent the hot robotic arm from entering the chamber for the adhesion stage 18 because it may be a safety hazard to have hot semiconductor wafer 12 in the chamber for the adhesion stage 18.
- the adhesion layer may be volatile when deposited on a hot semiconductor wafer.
- a cooling stage 17 may be used to cool the semiconductor wafer 12.
- the hot robotic arm should be able to transfer the semiconductor wafer 12 from the chamber for the heating stage 16 to the chamber for the cooling stage 17. Afterwards, the cool robotic arm can transfer the cooled semiconductor wafer to the adhesion stage 18. In one embodiment, the cooled semiconductor wafer is cooled until it reaches approximately room temperature (approximately 21 degrees Celsius.) In one embodiment, the semiconductor wafer 12 is cooled for approximately 45 seconds. In one embodiment, all cooling stages are herein performed by using a cool or chill plate. However, like the heating stage 16, the time can be chosen to suit the specific overall photolithographic process.
- the semiconductor wafer 12 is transported, in one embodiment, by a robotic arm, which is most likely the cool robotic arm, to the adhesion stage 18.
- a pre-resist coating or adhesion layer is deposited on the semiconductor wafer 12 to improve adhesion.
- the adhesion layer is a silylating priming agent, such as hexamethyldisilazane (HMDS).
- HMDS chemically reacts to remove any surface OH groups. Due to the presence of heat, the HMDS reacts with oxygen to form a trimethylsilyl (Si[CHs] 3 ) that bonds to the semiconductor wafer 12.
- the temperature of the adhesion stage 18 is approximately 100 degrees Celsius or greater, such as approximately 120 degrees Celsius.
- the adhesion stage is approximately 50 to 70 seconds, or preferably approximately 60 seconds.
- the semiconductor wafer 12 may be cooled to prevent bubbling and melting of the subsequently applied photoresist. Hence, the semiconductor wafer 12 may be transported, in one embodiment, by the cooling robotic arm, to a chamber for a second cooling stage 20. In one embodiment, the semiconductor wafer 12 is cooled to approximately room temperature for approximately 45 seconds.
- the semiconductor wafer 12 After being cooled, the semiconductor wafer 12 is transported to the resist application stage 22, for example, by one of the robotic arms. In one embodiment, at the resist application stage 22, the resist is spin-coated onto the semiconductor wafer 12. After the resist solution is applied to the semiconductor wafer 12 from the dispenser 23, the semiconductor wafer 12 is spun or rotated to uniformly apply the resist to the entire semiconductor wafer 12. The spinning may continue until the photoresist is substantially dry. If a bead of dried photoresist occurs along the circumference of the semiconductor wafer 12, the dried photoresist should be removed to avoid the bead from flaking off and creating particles that may cause contamination problems.
- a chemically amplified photoresist such as a deep ultra-violet (DUV) resist may be used.
- a ESCAP environmentally safe/stable chemically altered photoresist
- any photoresist material can be used.
- the semiconductor wafer 12 is transported, for example, by a robotic arm to a second heating stage 24, which may be termed a soft-bake or post-apply bake.
- the soft bake is performed to cross-link the molecules in the photoresist.
- the soft-bake may also remove any solvent from the photoresist and may improve adhesion of the photoresist by decreasing stress in the photoresist.
- the soft bake occurs at a temperature of approximately 130 degrees Celsius for approximately 60 seconds; however, other temperature and times may be used.
- the semiconductor wafer 12 may be cooled so that it is not at too high a temperature during subsequent process for various reasons, such as for ease of handling. Hence, the semiconductor wafer 12 may be transported to a chamber for a third cooling stage 26. In one embodiment, the semiconductor wafer 12 is cooled to approximately room temperature for approximately 45 seconds.
- the stepper or scanner is used to align and expose the semiconductor wafer 12 one area at a time. For instance, the semiconductor wafer 12 will be aligned and exposed in a particular area (usually called a reticle field) and then the stepper stage or scanner stage will move the semiconductor wafer 12 to the appropriate portions of the tool so that a different area is aligned and exposed. Thus, once the stepper has aligned the semiconductor wafer 12 , the semiconductor wafer 12 will be subsequently exposed.
- a mask 31 is placed above the semiconductor wafer 12 and radiation is used to expose the photoresist based on the pattern of the mask 31.
- the radiation creates a photochemical reaction or transformation in the photoresist. If resist poisoning has occurred the amplification of the reaction will be decreased.
- the radiation can be any desirable radiation, such as light with a wavelength of 248 orl93 nanometers.
- a third heating stage 32 which may be termed a post exposure bake, is performed after the all desirable areas of the semiconductor wafer 12 are exposed.
- the post exposure bake excites acid catalysts to form the latent image within the photoresist.
- the post bake exposure occurs at a temperature of approximately 130 degrees Celsius for approximately 60 seconds.
- the semiconductor wafer 12 may be cooled. Hence, the semiconductor wafer 12 may be transported to a chamber for a fourth cooling stage 34. In one embodiment, the semiconductor wafer 12 is cooled to approximately room temperature for approximately 45 seconds.
- the semiconductor wafer 12 undergoes a development stage 36 after being cooled in the fourth cooling stage 34.
- the development stage 36 is performed using a spray development system where a nozzle 37 sprays developer 39 onto the semiconductor wafer 12, which is spinning.
- a subsequent rinse, dry, and heating processes may be performed after the development stage 36 to remove the developer.
- the semiconductor wafer 12 may leave the chemically filtered environment 10.
- an after develop inspection (ADI) 40 is performed.
- ADI 40 a tool, such as an optical microscope, scanning electron microscope (SEM), or laser system, may be used to inspect the photoresist pattern. Characteristics of the photoresist that are likely to be determined during inspection include the quality of the film, image quality, and defects. For example, dense arrays of vias can be inspected to determine if any vias or portions of vias are missing.
- the semiconductor wafer 12 is sent on for subsequent processing where the photoresist pattern will be used to etch underlying layers. If instead, the pattern is not acceptable, the photoresist layer can be removed (stripped) and the photolithography process can be repeated.
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007543009A JP2008522403A (en) | 2004-11-30 | 2004-11-30 | Method for forming photoresist pattern |
PCT/US2004/040237 WO2006060015A1 (en) | 2004-11-30 | 2004-11-30 | Method for forming a photoresist pattern |
CNB2004800442533A CN100468642C (en) | 2004-11-30 | 2004-11-30 | Method for forming a photoresist pattern |
TW094140267A TWI383431B (en) | 2004-11-30 | 2005-11-16 | Method of forming a photoresist pattern |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2004/040237 WO2006060015A1 (en) | 2004-11-30 | 2004-11-30 | Method for forming a photoresist pattern |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2006060015A1 true WO2006060015A1 (en) | 2006-06-08 |
Family
ID=36565341
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2004/040237 WO2006060015A1 (en) | 2004-11-30 | 2004-11-30 | Method for forming a photoresist pattern |
Country Status (4)
Country | Link |
---|---|
JP (1) | JP2008522403A (en) |
CN (1) | CN100468642C (en) |
TW (1) | TWI383431B (en) |
WO (1) | WO2006060015A1 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6518206B1 (en) * | 1997-10-22 | 2003-02-11 | Applied Materials Inc. | Method for etching an anti-reflective coating |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0822945A (en) * | 1994-07-07 | 1996-01-23 | Fujitsu Ltd | Manufacture of semiconductor device |
JPH08339950A (en) * | 1995-06-09 | 1996-12-24 | Sony Corp | Photoresist pattern formation and photoresist treatment device |
JPH10261624A (en) * | 1997-03-19 | 1998-09-29 | Nec Corp | Etching and multilayered interconnection structure |
JPH1145845A (en) * | 1997-07-24 | 1999-02-16 | Fujitsu Ltd | Manufacture of semiconductor device and fan filter unit |
JPH11177080A (en) * | 1997-12-11 | 1999-07-02 | Ricoh Co Ltd | Manufacture of semiconductor device |
US6316168B1 (en) * | 1999-04-12 | 2001-11-13 | Siemens Aktiengesellschaft | Top layer imaging lithography for semiconductor processing |
JP4678665B2 (en) * | 2001-11-15 | 2011-04-27 | 東京エレクトロン株式会社 | Substrate processing method and substrate processing apparatus |
US6936551B2 (en) * | 2002-05-08 | 2005-08-30 | Applied Materials Inc. | Methods and apparatus for E-beam treatment used to fabricate integrated circuit devices |
TWI299535B (en) * | 2002-09-24 | 2008-08-01 | Extraction Systems Inc | System and method for monitoring contamination |
JP2004207590A (en) * | 2002-12-26 | 2004-07-22 | Fasl Japan 株式会社 | Method of manufacturing semiconductor device |
JP4050631B2 (en) * | 2003-02-21 | 2008-02-20 | 株式会社ルネサステクノロジ | Manufacturing method of electronic device |
TWI240302B (en) * | 2003-04-08 | 2005-09-21 | Nanya Technology Corp | Method for increasing adhesion of rework photoresist on oxynitride film |
-
2004
- 2004-11-30 JP JP2007543009A patent/JP2008522403A/en active Pending
- 2004-11-30 WO PCT/US2004/040237 patent/WO2006060015A1/en active Application Filing
- 2004-11-30 CN CNB2004800442533A patent/CN100468642C/en not_active Expired - Fee Related
-
2005
- 2005-11-16 TW TW094140267A patent/TWI383431B/en not_active IP Right Cessation
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6518206B1 (en) * | 1997-10-22 | 2003-02-11 | Applied Materials Inc. | Method for etching an anti-reflective coating |
Also Published As
Publication number | Publication date |
---|---|
JP2008522403A (en) | 2008-06-26 |
TW200625405A (en) | 2006-07-16 |
TWI383431B (en) | 2013-01-21 |
CN101044599A (en) | 2007-09-26 |
CN100468642C (en) | 2009-03-11 |
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