WO2006053938A1

WO2006053938A1 - Modified semiconductor drift detector

Info

Publication number: WO2006053938A1
Application number: PCT/FI2005/000488
Authority: WO
Inventors: Artto Aurola
Original assignee: Artto Aurola
Priority date: 2004-11-17
Filing date: 2005-11-16
Publication date: 2006-05-26
Also published as: BRPI0514449A; FI20041479A0; FI20041479A; BRPI0514449B1

Abstract

A semiconductor radiation detector device comprises a transport layer (120, 330) of semiconductor material of a first conductivity type and a radiation entry window of a second conductivity type (110) on one side thereof. A collector electrode (160, 1525) is coupled to the transport layer (120, 330) for collecting radiation-induced signal charge. On one side of the transport layer opposite to the radiation entry window (110) there are electrode means (151 - 154, 351 - 359, 751 - 753, 1251 - 1253, 1451 - 1456) coupled to different potentials for creating a charge-directing electric field inside the transport layer. Between said electrode means and the transport layer, an essentially continuous doping layer (140) of the second conductivity type extends across a number of said electrode means. The radiation entry window, the collector electrode and the electrode means are biased such, that the transport layer in the active area is depleted and that on a straight line between the radiation entry window (110) and the large area doping (140), a potential energy minimum for majority carriers of the first conductivity type is formed inside the transport layer.

Description

MODIFIED SEMICONDUCTOR DRIFT DETECTOR

FIELD OF INVENTION

This innovation relates to arranging differently doped areas in a semiconductor radiation detector detecting electromagnetic or particle radiation, in order to achieve most optimal detector properties and operation.

BACKGROUND OF THE INVENTION

The operation principle of semiconductor radiation detectors is based on a depleted volume of semiconductor material, created preferably by a reverse biased junction of n and p doped areas inside the semiconductor. The n and p doped areas correspond to areas where the electrons in the conduction band and holes, i.e. missing electrons in the valence band are the majority carriers. Radiation entering the depleted volume and having enough of energy to lift electrons from the valence band to the conduction band creates electron hole pairs, which are separated by the electric field present in the depleted volume. The amount of energy released by the radiation inside the depleted semiconductor volume and close to its border can be measured by counting the number of created electrons or holes. The measured charge type is hereinafter referred to as the signal charge.

The simplest possible semiconductor detector structure is a reverse biased diode, which is made for instance on a high resistivity n type semiconductor wafer and has a maskless n+ implant (anode) on the other side of the wafer and a large area structured p+ implant (cathode) on the opposite side of the wafer. During the operation the diode is reverse biased so that the substrate between the n+ and ρ+ areas is completely depleted. This arrangement has, however, an inherent weakness. The capacitance of such a device is proportional to the area of the p+ doping. In order to achieve a large effective area for the detection of radiation (from now on referred to as the active area) the diode has to be large in size, but due to the large capacitance the response to the radiation is degraded. One way to circumvent this problem is to divide the p+ area in smaller subareas, i.e. as pixels or strips which have smaller capacitances. The additional benefit of pixels is, that 2D position information can be obtained. A disadvantage of the pixel structure is, that a large number of read out channels are required. A problem concerning all the atructures, the large area diode, the strip structure and the pixel structure is that large amounts of interface current is generated at depleted semiconductor borders and at depleted semiconductor isolator interfaces.

A large active area detector having only one or a few readout channels is presented in U. S. patent 4,688,067. This structure, also known as semiconductor drift detector (SDD) or semiconductor drift chamber, comprises a high resistivity n type substrate having p+ strips on both surfaces and one or a few possibly point size n+ anodes on one surface. The p+ strips are biased respectively to the n+ anodes in such a manner that the substrate is completely depleted and that inside the substrate, on a plane parallel to the wafer surfaces, a monotonously decreasing potential energy function for electrons is created leading towards the n+ contact. The capacitance of this structure is very small due to the nearly point size anode. The device's energy resolution for low energy X-rays and other shallow penetrating radiation is, however, hampered due to a non-uniform radiation entry window, i.e. due to the strip structure on the radiation entry side of the detector. If silicon is used as the semiconductor material, which is usually the case, a thin layer of silicon dioxide (from now on referred to as oxide) is formed on top of silicon even at room temperature. The areas between the p+ strips are thus covered with an oxide layer, which is always positively charged. The positive oxide charge creates local electron potential energy minima in the silicon substrate under the oxide in the areas between the strips. The border between these local potential wells and the main potential well in the substrate is far deeper than the depth of the dead layer in the p+ area. The dead layer refers to the depth after which radiation induced electrons are transferred to the main potential well in the substrate. Thus the response of the radiation depends on the point of incidence. This effect can be at least partially eliminated for shallow penetrating radiation by covering the areas between the strips for instance with a metal layer. This will, however, reduce the effective area (or the fill factor) of the detector for shallow penetrating radiation and result in the aforementioned effect for deeper penetrating radiation. A more sophisticated way to remove the problem is presented in US 4,837,607, where the radiation entry window of the detector is made of a single large area p+ implant and the strip structure is only present on the opposite side of the detector. The same idea is also used in the patent application US 2004/0149919 Al.

The effect of the positive oxide charge causing local potential wells in an n type silicon substrate between close enough spaced p+ strips can also be used as an advantage on the surface opposite to the radiation entry side of the SDD due to a following reason. The silicon oxide interface has a large number of defects compared to a high quality silicon substrate. Thus the amount of thermally generated dark current arising from a depleted silicon oxide interface can be 50 times larger than the dark current generated in a 300 μm thick depleted substrate. If this interface current (from now on referred to as the surface current) is not drained away, it will fill the local potential wells, from where it will run to the main potential well causing excess noise. In a detector where the p+ strips are formed of concentric rings surrounding a single n+ anode or an integrated amplifier, small gaps can be made to the p+ rings except the innermost ring. Through these gaps at least the major part of the surface current can run to the local well under the oxide surrounding the innermost ring, where it can be collected by an additional n+ contact. In a detector having a plurality of n+ readout channels or integrated amplifiers arranged on a straight line next to a plurality of straight p+ strips (like in US 4,688,067), at least the major part of the surface current can be drained outside the active area by guiding the surface current in the local potential wells situated under the oxide between p+ strips.

In order to obtain beside the energy, also two dimensional (2D) position information of the radiation, one can use a fully depleted charge coupled device (CCD) arrangement based on the SDD principle, the major difference being that the signal charge cannot freely drift. This structure is also called as the pn-CCD and the principle is presented in US 4,688,067 and variations of it are also discussed in US 4,885,620 and US 4,982,253. A later version of it is described in reference Monika Rose, Master Thesis 2002, University of Regensburg — Department of physics II. Faculty of the Institute of Experimental and Applied Physics (http://www.hll.mpg.de/publications/2002/dipl_rose.pdf see figure 2.3 on page 7). The substrate of the pn-CCD comprises an n- wafer and an n type layer on top of it. Parallel p+ strips are provided on the n type layer side of the wafer and a large area p+ radiation entry window is situated on the opposite side of the wafer. The function of the n type layer is to confine the signal charge close to the substrate surface oppositely to the radiation entry side of the detector, so that potential wells can be created for the signal charge. The barriers of the potential wells in the charge transfer direction are formed by biasing the p+ strips like the gates in a conventional CCD: in the integration mode the p+ strips are connected for instance to two different constant potentials and in the transfer phase the potentials are altered in a periodic manner. The barriers in the direction perpendicular to the transfer direction on a plane parallel to the surface are created by deep n implants under which the transfer channels are formed and by deep p implants forming the channel stops. A problem associated with the pn-CCD is the lack of an antiblooming structure. The design and manufacture of the pn-CCD are also problematic. First of all due to the deep p implants forming the channel stops the surface current is leaking to the transfer channels and cannot be guided at the oxide interface between the p+ strips to the edge of the active area. This problem can be avoided by discontinuous deep p implants, however, the full well capacity of the individual wells would likely to be reduced, i.e. the blooming tendency would be enhanced. Secondly the p+ strips and the deep p implants have to be isolated from each others to prevent large currents from running through the deep p implants between differently biased p+ strips. This problem can be avoided by an intermediately deep n implant for instance at the location of the p+ strips. Thirdly the electron potential energy in the substrate close to the surface is always less in locations between the p+ strips than in the p+ strips itself. This potential difference is likely to cause traps, i.e. unwanted potential minima in the transfer channel during the charge transport phase. This problem can be at least partially removed by the afore described intermediately deep n implant at the location of the p+ strips.

The dose and the implantation energy of the additional n implant at the location of the p+ strips should be carefully selected. The electric fields in the substrate should be kept under the avalanche breakdown limit. While removing the traps under the oxide, new traps should not be formed under the p+ strips. Sufficient isolation between the p+ and deep p strips should also be achieved. The proper dose and energy of the additional n implant depends for instance on the depth of the deep p implant, on the distance between adjacent p+ strips, on the n type layer doping concentration and on the amount of the positive oxide charge. The amount of oxide charge is a crucial parameter, because it is difficult to control. There are also two more problems related to the oxide charge. The effective amount of the oxide charge is affected by changes in the air humidity, a phenomenon that can be avoided by covering the oxide with metal. The other problem is that the oxide charge and the surface current increase proportional to the radiation dose. The increased amount of oxide charge can lead to the formation of unwanted potential minima which reduces the lifetime of the device.

The preferred embodiment of the US 4,688,067 can also be used (beside the pn- CCD) for 2D position sensing of the radiation, if a trigger signal can be provided. One coordinate is automatically obtained by the readout channel collecting the radiation generated signal charge (in this case electrons) and the other coordinate can be determined by the time difference between the trigger signal and the time when the signal charge is collected. The velocity of the signal charge is the product of mobility and drift field, and the velocity multiplied by the time difference gives the second coordinate. An external trigger signal can, however, not be used, if X- rays or Gamma-rays are detected. A solution to this problem is presented in US 4,885,620, where the minority carriers (holes in a n type substrate) generated by radiation and collected by the p+ electrodes are used for an internal trigger signal. The structure of US 4,688,067 has still one additional disadvantage, which is the lack of confinement of the signal charge in the direction parallel to the surface and perpendicular to the drift path. This problem is resolved by a SDD structure presented in Nuclear Instruments and Methods in Physics Research, 377 (1996) 375 (later on referred to as NIM 377/375). The structure resembles the pn-CCD: it has an n type layer on top of an n- substrate, deep p implants are used as channel stops and a large area p+ implant introduced in US 4,837,607 is used as the radiation entry window. In order for the device to function properly the deep p implants have to be discontinuous and intermediately deep n implants should be used below the p+ strips. Unlike in the pn-CCD, the p+ strips are biased in a monotonically decreasing manner, i.e. like in a conventional SDD.

The use of the internal trigger signal for the 2D position sensing in the afore described detector (NIM 377/375) has, however, a drawback: it complicates the design of the detector and associated electronics. A biasing scheme for the detector structure in NIM 377/375 based on a principle introduced in IEEE Journal of Solid- State Circuits, 13 (1978) 61, is presented in US 6,249,033. In this scheme either the potentials of the p+ strips are altered in a periodic manner for instance with the help of two or three different integrated voltage dividers or the potential of the large area p+ implant is altered, in order to create periodic potential wells during an integration period. In the read out period the periodic potential wells are removed and the structure is functioning like a conventional SDD. The coordinate along the drift direction is calculated according to the time difference between the arrival of the charge packet and the beginning of the read out phase. In the latest version the active area of the device has been increased by dividing the radiation entry window into large p+ strips biased in a monotonously decreasing manner. An exact timing of the radiation is achieved by monitoring minority carrier signals induced in these strips. A structure is also presented in US 6,249,033, where separate pixel and transfer channel areas exist causing the fill factor to be less than one. The energy resolution of this structure is, however, severely affected by split events taking place at the pixel - transfer channel border. Later on the structures introduced in US 6,249,033 are referred to as the controlled drift detector (CDD). The CDD structure suffers from the same problems as the pn-CCD. First of all the design is vulnerable to changes in the amount of positive oxide charge Secondly deep enough potential wells and the mixing of the interface current with the signal charge is extremely hard to achieve at the same time. Both the CDD and the pn- CCD have also relatively low potential barriers separating adjacent pixels leading to a relatively low full well capacity and thus to a low dynamic range. This is especially true if one takes the relatively large pixel size of the afore mentioned detectors into account.

The previously introduced detectors being capable of both energy and 2D position sensing (except the pixelated diode structure) are all charge transfer devices (CTD). Beside them there exists also an active pixel sensor (APS) based on the SDD principle introduced in US 4,688,067, which is presented in US 5,786,609. In this structure no means are presented for the collection of the surface current. In later versions, however, between the p type source doping and the oxide layer covering the wafer, an n channel is fabricated connecting the areas surrounding the p source and a reset contact. The reset contact is thus assumed to have an additional function besides resetting an internal gate structure; it is supposed to collect at least the major part of the surface current. The structure in US 5,786,609, later on referred to as the DEPFET detector, has the same previously listed problems. Unwanted potential minima should not be formed below areas covered by oxide and surrounding the source. As little of the surface current as possible should run to the internal gate structure. The structure is also vulnerable to changes in the amount of the positive oxide charge.

Silicon has been a popular material for radiation detection for at least four reasons. The first reason is that relatively cheap high resistivity and high quality wafers reaching lifetime values of 10 ms are available. The second reason is that although the silicon oxide interface has a large amount of defects compared to bulk, it has still relatively little defects compared to other semiconductor isolator interfaces. The third reason is the ease to dope silicon. The fourth reason are the well established methods to process silicon developed by the integrated circuit industry. Silicon has, however, a relatively low stopping power for high energy X-rays compared to semiconductor materials having a higher density of electrons like Ge, GaAs, CdTe and CdZnTe. In commonly used silicon detectors the upper detection limit for X- ray energies is usually around 10 to 15 keV, but with detectors made of the aforementioned materials one could measure much higher energies. There is also an additional benefit of these materials, namely a greater carrier mobility enhancing the drift speed and thus the speed of operation of CTDs. In Ge the electron mobility is around 3 times, in GaAs around 6 times and in CdTe around 7 times higher than in silicon. The surface properties of these materials are, however, worse than in silicon which is one factor limiting their performance as radiation detector semiconductor materials.

SUMMARY OF THE INVENTION

It is the objective of this innovation to provide a semiconductor radiation detector that is not influenced by the surface and interface properties of the semiconductor material. It is also an object of the invention to isolate the signal charge from the surface generated charge.. It is another objective of the invention to facilitate the use of radiation detectors based on other semiconductor materials than silicon. Another objective of the invention is to provide simple means to form potential wells associated with pixels and to remove or shift the potential wells. Another objective of the invention is to provide an antiblooming structure to the pixels. Yet another objective is to provide deeper potential wells associated with pixels in order to increase the full well capacity of the pixels and thus to improve the dynamic range of the detector.

The objectives of the invention are achieved by introducing a large area doping of second conductivity type on a surface of a semiconductor substrate , and by introducing, inside at least one such large area doping, dopings of first conductivity type functioning as biasing electrodes, the substrate further including a charge transport layer of first conductivity type next to the said large area doping and on an opposite side of the substrate than the said large area doping another large area doping of the second type.

A semiconductor radiation detector according to the invention is characterised by the features recited in the characterising part of the independent claim directed to a semiconductor radiation detector.

A method for detecting radiation according to the invention is characterised by the features recited in the characterising part of the independent claim directed to such a method.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a cross section of an embodiment of the innovation, FIG. 2 illustrates electron potentials of the structure in FIG. 1,

FIG. 3 illustrates a cross section of a CCD structure according to the innovation,

FIG. 4 illustrates a front view of the structure in FIG. 3,

FIG. SA illustrates a cross section of FIG. 4,

FIG. 5B illustrates an other cross section of FIG. 4,

FIG. 6 illustrates electron potentials on different cut lines in FIG. 3,

FIG. 7 illustrates a front view of an embodiment of the innovation,

FIG. 8 illustrates a cross section of the structure in FIG. 7,

FIG. 9 A illustrates a cross section of the structure in FIG. 7,

FIG. 9B illustrates a cross section of the structure in FIG. 7,

FIG. 10 illustrates electron potentials on different cut lines in FIGS 8, 9 A and 9B according to the readout phase,

FIG. 11 illustrates electron potentials on different cut lines in FIGS 8, 9A and 9B according to the integration phase,

FIG. 12 illustrates a front view of an other embodiment of the structure in FIG. 7,

FIG. 13 A illustrates a cross section of the structure in FIG. 12,

FIG. 13B illustrates a cross section of the structure in FIG. 12,

FIG. 14 illustrates a pixel detector embodiment of the innovation,

FIG. 15A illustrates a signal charge detection means corresponding to FIGS. 1, 3, 8 and 14,

FIG. 15B illustrates a signal charge detection means corresponding to FIGS. 1, 3, 8 and 14,

FIG. 15C illustrates a signal charge detection means corresponding to FIGS. 1, 3, 8 and 14. DETAILED DESCRIPTION OF THE DRAWINGS

A structure according to one embodiment of the invention is presented in FIG. 1. In this structure there is a thin highly doped radiation entry window 110 of second type of conductivity, having preferably a low square resistance, on the back side 101 of a high resistivity substrate 120 of a first type of conductivity. The backside 101 may be covered with additional layers, e.g. with an antireflection coating or with a thin metal layer. On the front side 102 of the substrate there is a large area doping 140 of the second type of conductivity and a multitude of heavily doped biasing electrodes

151, 152, 153 and 154 of the first type of conductivity formed inside the doping 140. In reality there are far more than four biasing electrodes and the dimensions of the FIG. 1 are different. The biasing electrodes can have for instance the form of concentric rings surrounding a heavily doped collecting electrode 160 of the first type of conductivity or an internal amplifier structure, which would be situated inside the area of the box 103. The internal amplifier structures are dealt with later on (FIGS 15A, 15B and 15C). The area 170 represents a collecting electrode of the second type of conductivity. Preferably, the areas doped to first type conductivity are n type and the areas exhibiting the second type of conductivity are p type. From now on reference is made to this situation, but the doping types could also be interchanged.

When the structure presented in FIG. 1 is in operation the n+ electrodes 151 - 154 and 160, and the p+ back layer 110 are biased such, that the n- substrate 120 corresponding to the active area is essentially completely depleted. In addition to that the n+ electrodes are biased in a monotonously decreasing voltage the further they are from the n+ electrode 160 enabling the collection of the radiation generated electrons by the electrode 160. The line 106 is formed of points presenting the electron potential energy minimum on imaginary straight lines drawn perpendicular to the back and front surfaces. The potential energy minima decrease monotonously towards the electrode 160. The line 106 thus represents the electron drift path.

The electron potential energy on cut lines 104 and 105 is presented in FIG. 2, where the electron potential on the cut line 104 cutting the large area doping 140 is marked with a discontinuous line 204 and the electron potential on the cut line 105 cutting a biasing electrode 152 is marked with a continuous line 205. The straight horizontal parts of the curves 204 and 205 represent neutral areas and the curved parts represent depleted areas in the semiconductor. The curve 205 has two neutral areas corresponding to the p+ radiation entry window 110 and to the n+ biasing electrode

152. The point 214 is a local electron potential maximum of 205 in the completely depleted p doped area between the n+ biasing electrode 152 and the n- substrate 120. The curve 204 has also two neutral areas corresponding to the layer 110 and to the part 211 of the layer 140. An electron potential maximum is equal to a hole potential minimum, and thus the electron potential difference 212 at the location 214 functions as a hole potential barrier. The height of this barrier is ideally determined by two factors, which are the temperature and the density of the hole current running inside the layer 140 over the barrier 212 at the location 214. This hole current is composed of holes generated at the surface, and of holes generated between locations 102 and 106 either spontaneously or by radiation, and it is collected by the electrode 170. The holes generated spontaneously or by radiation between locations 101 and 106 are collected by the layer 110.

In case the semiconductor material is silicon, the positive oxide charge causes a depletion region and thus a potential difference 213 in the large area doping 140 next to the surface 102. The surface generated electrons flow in this channel to the adjacent biasing electrodes. The size of the potential difference 213 can be reduced by a shallow p implant or enhanced by a shallow n implant between the n+ biasing electrodes, if necessary. In case of any semiconductor material, including silicon, one can add between n+ electrodes CIS-structures and bias them so that the interface of the layer 140 at the surface 102 is either depleted or inverted.

The curves 208 and 209 in FIG. 2 represent the electron potentials on the cut lines 108 and 109 in FIG. 1. The voltage V₃ connected to the electrode 153 is lower than the voltage V₂ connected to 152 and thus the electron potential curves 208 and 209 are above the curves 204 and 205. For the aforementioned reason the electron potential minimum in the drift channel 106 under the electrode 153 is higher than under the electrode 152, i.e. electrons in the drift channel under the electrode 153 will flow towards a location under the electrode 152. The hole current in the layer 140 runs into the opposite direction; from the p type area between the electrodes 151 and 152, i.e. from the area 211, through the channel 214 to the p type area between the electrodes 152 and 153. The other electrodes are biased in a similar fashion: V₀ > V₁ > V₂ > V₃ > V₄ > V_D, where V₀ is connected to 160, V₁ to 151, V₄ to 154 and V_D to 170. This biasing scheme assures that the electrons in the drift channel 106 are collected by the electrode 160 and that the holes in the layer 140 are collected by the electrode 170.

In reality, the net doping density in the layer 140 between the n+ electrodes and the n- substrates has fluctuations and this causes the local electron potential maximum

214 in the curve 205 to vary at different locations of the electrode 152. The electron potential maximum corresponding to area 211 in the curve 204 is everywhere the same and it is determined by the location 214 having the highest local potential maximum. However, if the p type doped layer 140 is carefully manufactured by diffusion, implantation or by epitaxial growth, the potential difference 212 anywhere on the electrode 152 should be less than the potential difference between p+ strips and the n area between the strips in a conventional SDD.

The structure described in FIGS 1 and 2 has many benefits compared to a conventional SDD. First of all, outside the region 103 none of the surface generated electrons will mix with the signal electrons. A non-depleted, i.e. a neutral area (211 or 152) between the surface 102 and drift channel 106 isolates the positive oxide charge completely from the drift channel, so that changes or variations in the amount of the oxide charge will not affect the drift channel and nor the operation of the device. There is no need for design and manufacture of complicated and vulnerable structures aimed to collect at least the major part of the surface current.

FIG. 3 represents a CCD structure based on the SDD principle and having large area p dopings (110 and 140) on both sides (101 and 102) of the structure. Inside the p doping 140 on the front side of the structure there is a multitude of n+ electrodes 351 - 359 functioning as CCD transfer electrodes. The n+ doping 160 is the signal charge collecting eletrode, but it could also be replaced by an internal amplifier structure inside the box 103. The p+ electrode 370 collects the hole current created between the front surface 102 and the line 306 representing the potential minimum inside the semiconductor in a direction perpendicular to the surfaces 101 and 102. The layer 110 is a p+ radiation entry window, which could be covered by an antireflection coating. The layer 330 is an n layer introduced to confine the signal charge electrons close to the surface 102 without causing a hole current to run from 370 to 110, to enhance the full well capacity of the pixels and to facilitate the control of the signal charge by the transfer electrodes. The substrate 320 is preferably n type, but it could also be p type. The areas 307 and 315 are optional deep p and n dopings. The front side 102 of the CCD structure in FIG. 3 is presented in FIG. 4, where the cut line 416 presents the plane of FIG. 3 and the cut lines 417 and 418 present FIGS 5A and 5B. The box 421 represents the area of one pixel.

The principle of operation of the CCD structure presented in FIGS 3, 4, 5A and 5B can be explained with the help of FIG. 6. Three transfer electrodes of one pixel are connected in a cyclical manner to two different bias voltages Vp₁ and Vp₂ during the integration and transfer periods, just like in a conventional CCD. The electron potential function along the line 305 in FIG. 3 is represented by the curve 605 in FIG. 6. This curve represents the electron potential along perpendicular lines running through transfer electrodes (352, 353, 355, 356, 358, 359) connected to the more positive pixel voltage Vp₁. This voltage is used to deplete the p layer 140 between the transfer electrode and the layer 330, in order to create a potential well for the signal electrons in the layer 330 (location 306 of curve 605). The curve 605 has thus only two flat parts representing neutral areas corresponding to the transfer electrode and the radiation entry window. The electron potential energy along the line 309 in FIG. 3 is presented by the curve 609 in FIG. 6. The curve 609 represents the electron potential energy on perpendicular lines penetrating through transfer electrodes (351, 354, 357) connected to the more negative pixel voltage Vp₂. This voltage is such that there exists a neutral area in the layer 140 between the transfer electrode and the layer 330. In addition to this part there are two more neutral areas in the curve 609, corresponding to the transfer electrode and the radiation entry window.

The electron potential energy along a line running perpendicular to the surface between two adjacent transfer electrodes biased at Vp₂ (this bias configuration corresponds to one phase of the biasing cycle and is not shown in FIG. 3) and represented by the curve 619 is only partly shown, because the major part of it is coincident with the curve 609. This is due to the fact that the electric potential of the neutral part in 330 is determined everywhere solely by the bias voltage of 370. The benefit of this fact is that no unwanted potential minima are formed in the transfer channel 306 between adjacent transfer electrodes biased at Vp₂. This applies also for the case presented by the graph 608, which presents electron potential energy along the line 308 in FIG. 3 drawn at a location between two transfer electrodes biased at different pixel potentials V_Pj and Vp₂. The electron potential of 608 at the location 306 is always between the potentials of 605 and 609 at the same location, and thus no unwanted potential minima are formed at this location either. The electron potential on the line 304 in FIG. 3 running between transfer electrodes biased at the same electric potential Vpi, is presented by the curve 604. In this case there is a potential barrier in the transfer channel between the two electrodes. However, this is not crucial for the operation of the device; when the electric potential of either of these transfer electrodes is changed from Vp₁ to Vp₂ this barrier vanishes. One can also bias the aforementioned transfer electrode first to an intermediate potential and then to V_P2 in order to guarantee efficient charge transport. The potential barrier formed by the curve 604 at the location 306 can be decreased by reducing the distance between adjacent transfer electrodes and by increasing the depth of the transfer channel.

It is important to note that holes collected by the location 614 will immediately flow to the location 611, and thus these holes will not interfere the signal charge transfer process. To reduce band bending in p type material next to the oxide interface a shallow p spray implant, i.e. a maskless p implant can be used on the surface 102.

The CCD structure presented in FIGS 3 — 6 has many benefits compared to the pn- CCD structure: the surface generated charge can not mix with the signal charge, no unwanted potential wells are formed in the transfer channel, the positive oxide charge is isolated from the transfer channel by neutral areas in the bulk and the detector design is facilitated. An additional benefit of the afore described CCD structure is that the transfer electrodes can be used as antiblooming structures, if the device is properly designed and biased. The necessary requirement is that the potential maximum 614 corresponding to a full well must be less than the potential minimum 306 of the curve 609. The result of this is that instead of blooming to the adjacent pixels the excess signal electrons will be drained by the transfer electrodes.

In FIG. 7 is presented a SDD structure according to the innovation, which can be biased using the principle introduced in IEEE Journal of Solid-State Circuits, 13 (1978) 61. The areas 751, 752 and 753 are n+ biasing electrodes, which are connected to monotonously decreasing voltages the further they are from the signal charge collecting electrodes (160). The p+ electrode 770 collects the secondary charges, i.e. the holes. The areas 741, 742 and 743 represent conductor layers covering an isolator layer. The areas 707 and 715 are additional p and n dopings and the box 721 represents the area of one pixel. The cut lines 716, 717 and 718 and represent the image planes of FIGS 8, 9A and 9B. In FIG. 8 isolator layers 831, 832 and 833 are situated between the conductor layers and the semiconductor material.

The operation principle of the device in FIGS 7, 8, 9A and 9B can be explained with the help of FIGS 10 and 11. The electron potential curves along lines 804, 805, 908 and 909 in the readout phase are presented in FIG. 10 by the curves 1004, 1005, 1008 and 1009. The potential of the flat, neutral p area between the n+ strips is determined by locations under the n+ strips having the additional p doping 707 and thus the highest local potential maxima in the layer 140 (curve 1005 corresponds to this location). The drift channel, i.e. the local potential minimum of layer 330 in curves 1004 and 1005 is formed by an additional n doping 715 coinciding with the p doping 707. Due to this arrangement the curves 1005 and 1004 are coincident in layers 330 and 320, i.e. no potential bumps are formed in the drift channel, if good control of the dopant fluctuations is achieved. This is unlike in the CDD structure (see fig. 5 in US 6,249,033) where the bumps are inherent. The electron potential curves under the n+ strip and between the n+ strips corresponding to areas not having the additional n and p dopings are represented by curves 1009 and 1008. These areas form the potential barriers for the transfer channels.

During the integration phase more negative voltages than in the readout phase are applied to the conductor layers 741, 742 and 743. As a result the curves 1004 and 1008 in FIG. 10 are lifted to positions 1104 and 1108 in FIG. 11. Potential barriers are thus formed under the CIS structures. When the voltages of the conductor layers are connected back to the values according to the read out phase these potential barriers disappear. At the same time a hole current, composed mainly of holes generated at the surface during the integration phase, starts to run in the p layer 140 and is collected by the p+ electrode 770. The conductor layer voltages in FIGS 10 and 11 are both small enough to create an accumulation layer at the interface of the p layer 140 and the isolator layer. This fact causes the bands, i.e. the curves 1004, 1008, 1104 and 1108 to bend upwards at the interface, which is a beneficial but not a mandatory condition.

The structure presented in FIGS 7 - 9B offers many benefits compared to the CDD structure, e.g. the charge transfer characteristics is not affected by variations or changes in the amount of oxide charge, no complicated arrangements to collect the surface current are needed and the surface generated charges can not mix with the signal charge. The structure in FIGS 7 - 9B is, however, not the only possible realization of the innovation. In FIGS. 12, 13A and 13B for instance, is presented another embodiment of the innovation. The dopings 1207 and 1215 are drawn in

FIG. 12 with discontinuous lines because they are below the surface 102. The function of the n type dopings (1215 and alike) is to form potential wells for the signal charges; the p dopings (1207 and alike) are channel stop dopings. The n+ strips 1251, 1252 and 1253 are the biasing electrodes and the areas 1241, 1242 and 1243 are conductor layers of CIS structures. The cut lines 1217 and 1218 represent the image planes of FIGS 13 A and 13B.

One could use two different biasing schemes to operate the device in FIGS 12 - 13B. In the first one a monotonously decreasing voltage is applied to the biasing electrodes the further they are from the collecting electrodes. If the device is properly designed, e.g. if the n+ biasing strips are wide enough, potential wells form under the conductor layers at the locations of the n dopings (1215 and alike). In this biasing scheme the hole current in layer 140 is running during the integration phase. During the readout phase the voltages applied to the conductor layers are more negative than during the integration phase. The disadvantage of this arrangement is that these voltages need to be carefully selected; the electron potential minimum in the layer 330 under the n dopings (1215 and alike) must be between the potential minima under the two neighbouring n+ strips, otherwise unwanted potential wells or barriers are formed. However, if the electron potential minimum in the layer 330 under the n dopings (1215 and alike) is higher during the second phase (read out phase) than the potential minima under the two neighbouring n+ strips, the device can still be operated like a two phase CCD.

In the other biasing scheme, during the readout phase both the n+ strips and the conductor layers are connected to monotonously decreasing potentials the further they are from the collecting electrodes. If the device is properly designed, e.g. if the n+ biasing strips are narrow enough, no potential wells are formed under the conductor layers. In the integration phase the bias voltage of every second biasing electrode (1251, 1253) is not altered. The rest of the biasing electrodes (1252) are connected to voltages corresponding to the more negative voltage of the two adjacent biasing electrodes. The voltages of the conductor layers (1242) between two equally biased electrodes are not altered and more negative voltages are applied to the conductor layers (1241, 1243) between two differently biased n+ strips. Thus potential wells are formed under n dopings between equally biased electrodes (1253, 1252) and potential barriers are formed under the conductor electrodes biased at more negative voltages (1241, 1243). This second biasing scheme does not suffer from the afore mentioned problem related to the first biasing scheme. A difference is also that in the second scheme the hole current is running in the layer 140 during the readout phase.

Instead of having a rectangular shape and several readout electrodes, the devices in FIGS 7 and 12 can be reshaped as spirals having only one readout electrode. In the spiral detector configuration the biasing electrodes and the CIS structures surround the readout electrode and the dopings 707 and 715 or the dopings 1207 and 1215 are arranged in a spiral fashion to obtain a spiral drift channel ending at the readout electrode. The spiral detector allows two dimensional position resolution with only a single readout electrode.

A pixel detector structure according to an embodiment of the innovation is presented in FIG. 14. The readout electrodes 160 are each surrounded by concentric biasing electrodes having for instance a ring or hexagonal shape. The left readout electrode is surrounded by the n+ biasing electrodes 1451, 1452 and 1453, and the right one is surrounded by biasing electrodes 1454, 1455 and 1456. The line 1406 is the signal charge drift path. The p+ doping 1470 is an electrode collecting the hole current running in the layer 140. One should note that the n layer 330 is not mandatory.

The collecting electrode 160 can be connected to the gate of an integrated or external amplifying transistor. The arrangement inside the box 103 in FIGS 1, 3, 8 and 14 can, however, be replaced by a variety of different structures. In FIGS 15A - 15C three different structures are presented, but they are not the only possible ones. In FIG. 15A is presented a floating gate arrangement, where the p+ electrode 1522 is connected to the gate of an integrated or external transistor. The electrodes 1523 and 1524 are possible additional ρ+ electrodes used to transfer the signal charge (there could be of course only one or more than two of them). 1527, 1528 and 1529 are possible n dopings associated with the afore said electrodes. The n+ doping 1525 is a reset contact in addition to which also a reset gate could be used. The possible n doping 1526 is used to enable the reset contact to collect at least part of the surface generated electrons in silicon based detectors. The layer 1580 can be either 120, 315, 330, 715 or 1215. In FIG. 15B the n+ contact 1561 can function as a floating gate of an integrated or external transistor. The n+ areas 1562 and 1563 are possible contacts used to transfer the signal charge. Any one of the electrodes 1561, 1562 and 1563 can be used as a resetting contact or alternatively the signal charge can be reset with an additional reset structure. A p type JFET having an internal gate is presented in FIG. 15C. The ρ+ contacts 1591 and 1592 are the JFET source and drain or vice versa. The n+ area 1564 is the JFET gate and the possible n doping 1565 is associated to the internal gate structure. The JFET can also be operated in a condition where either one of the contacts 1591 and 1592 are floating. The gate contact 1564 can be used as the resetting contact or an additional resetting contact can be added to the structure. One should note that the p+ contact 1591 is not mandatory; if 1592 functions as the source the hole current can be drained by electrodes 170, 370, 770 or 1470. Instead of the structures in FIGS 15A - 15C, one can also use the modified internal gate structure presented in co-pending application PCT/FI2004/000492. The benefit of the modified internal gate structure and the structures in FIGS 15B and 15C is, that charges generated at the surface inside the box 103 can not mix with the signal charge.

The biasing of the structures in FIGS 1 - 15C can be done for instance by one or several integrated voltage dividers (being for instance formed of diffusions or thin film resistors). The dimensions of the figures are not to scale and in reality far more biasing electrodes should be used for example. A contact should be made to the neutral bulk on the borders of the device to prevent current flow from the neutral areas of the substrate to the transfer channel. Guard structures on both sides of the detector surrounding the large area p dopings can be made to improve the voltage breakdown characteristics of the device. The guard structures can be for instance in the form of structured p implants or diffusions around a large area p implant or diffusion. If the layers 110 and 140 are made by epitaxial growth, one can for instance make the guard structures by etching grooves deeper than the layers 140 or 110. This same applies also for unstructured implantations or diffusions of 110 and 140. One attractive way is also to use epilayers or maskless (unstructured) implants or diffusions and to form the guard structures of the same elements than already presented, i.e. of areas of the first type of conductivity inside the layers 110 and 140. Areas of first type of conductivity inside the layer 110 can also be used in the active area to divide the active area of 110 in parts having different voltages. In this manner the size of the active area can be increased.

The presented embodiments of the innovation should not be taken as limiting. There are numerous ways to alter or combine them. Like already stated before the layer 140 can be made by implantation, diffusion or by different epitaxial growth techniques, including molecular beam epitaxy (MBE). The layer 330 could also be made by implantation or by diffusion. It is also possible to use heterostructures instead of homostructures, i.e. one or more of the layers 110, 120, 320, 330 and 140 can be made of different semiconductor material. Dopings like 307, 315, 715, 1215, 1207, 1527, 1528, 1529 and 1565 could be made also at the interface of layers 140 and 330 or inside the layer 330. Additional dopings like this could be applied in any of the figures. In FIGS 12, 13A and 13B either one of the dopings 1207 or 1215 could be removed. The CIS structures in FIGS 7, 8, 9B, 12 and 13B could be replaced with electrodes that are connected directly to the layer 140. One could also add p+ electrodes or CIS structures between the guard structures and the biasing and transfer electrodes, and inside the innermost biasing electrode ring in any of the structures. Additional n+ areas could also be added between the n+ biasing electrodes. The biasing and transfer electrodes (151 - 154, 351 - 359, 751 - 753, 1251 - 1253, 1451 - 1456, 1525, 1561 - 1563, 1564) and guard structures could also be made of Schottky junctions. Some biasing electrodes (152 - 154, 752, 753, 1252, 1253, 1452, 1453, 1455, 1456) and guard structures could also be replaced by CIS structures. The secondary current running inside the layer 140 could be collected by the layer 110, or the secondary current running inside the layer 110 could be collected by the layer 140. One can also interchange the areas of p and n dopings, meaning that the signal charges would be holes instead of electrons.

A device that includes a detector according to an embodiment of the invention may also include other semiconductor chips, some of which may have bonded connections to the detector. This enables building very compact structures that include detection, amplification, reading and in some cases even storage in very small space, like a multi-chip module (MCM).

In the claims the layers 120 330 are referred to as the signal charge transport layer of the first conductivity type or as simply the transport layer. The collecting electrode and the reset contacts are referred to as the collector electrode and the biasing and transfer electrodes are referred to as the electrode means.

Claims

1. A semiconductor radiation detector device, comprising:

- a transport layer (120, 330) of semiconductor material of a first conductivity type,

- a radiation entry window of a second conductivity type (110) on one side of the transport layer (120, 330),

and

- a collector electrode (160, 1525) coupled to the transport layer (120, 330) for collecting radiation-induced signal charge continuously or discontinuously,

characterised in that it comprises, on a side of the transport layer opposite to the radiation entry window (110):

- electrode means (151 - 154, 351 - 359, 751 - 753, 1251 - 1253, 1451 - 1456) adapted to be coupled to different potentials for creating a charge-directing electric field inside the transport layer and

- between said electrode means and the transport layer, an essentially continuous doping layer (140) of the second conductivity type extending across a number of said electrode means,

of which the radiation entry window, the collector electrode and the electrode means are adapted to be biased such, that the transport layer in the active area is substantially completely depleted and that on a straight line between the radiation entry window (110) and the large area doping (140), a potential energy minimum for majority carriers of the first conductivity type is formed inside the transport layer.

2. A semiconductor radiation detector device according to claim 1, wherein an electrode (170, 370, 770, 1470) for collecting the secondary charges is connected to the doping layer (140) of the second conductivity type.

3. A semiconductor radiation detector device according to claim 1, wherein additional electrode means are also connected to the radiation entry window (110).

4. A semiconductor radiation detector device according to any of claims 1 or 3, wherein the electrode means are doped areas of the first conductivity type inside doped areas of the second type of conductivity.

5. A semiconductor radiation detector device according to any of claims 1 or 3, wherein the electrode means are formed of Schottky contacts.

6. A semiconductor radiation detector device according to any of claims 1 or 3, wherein at least part of the electrode means are formed of conductor-insulator- semiconductor structures.

7. A semiconductor radiation detector device according to claim 1, wherein the transport layer is formed of a high resistivity substrate (120) of the first conductivity type.

8. A semiconductor radiation detector device according to claim 1, wherein the transport layer is formed of a low resistivity layer (330) of the first conductivity type which is between a high resistivity substrate (320) and the doping layer (140) of the second conductivity type.

9. A semiconductor radiation detector device according to claim 8, wherein the low resistivity layer (330) is a layer formed onto a high resistivity substrate (320) by epitaxial growth.

10. A semiconductor radiation detector device according to claim 8, wherein the low resistivity layer (330) is a layer formed into a high resistivity substrate (320) by diffusion or implantation.

11. A semiconductor radiation detector device according to claim 1, wherein the doping layer (140) of the second conductivity type is a layer formed by one of: epitaxial growth, diffusion, implantation.

12. A semiconductor radiation detector device according to claim 1, wherein the radiation entry window (110) of the second type of conductivity is a layer formed by one of: epitaxial growth, diffusion, implantation.

13. A semiconductor radiation detector device according to any of claims 1 or 3, comprising conductor-insulator-semiconductor structures next to the electrode means.

14. A semiconductor radiation detector device according to any of claims 1 or 3, comprising electrodes consisting of doped areas of the second conductivity type next to the electrode means.

15. A semiconductor radiation detector device according to any of claims 1 or 3, comprising electrodes consisting of doped areas of the first conductivity type next to the electrode means.

16. A semiconductor radiation detector device according, to claim 1, comprising additional dopants of the first conductivity type in at least one of the doping layer

(140) of the second conductivity type and the transport layer (120, 330).

17. A semiconductor radiation detector device according to claim 1, comprising additional dopants of the second conductivity type in at least one of doping layer (140) of the second conductivity type and the transport layer (120, 330).

18. A semiconductor radiation detector device according to any of claims 1 or 3, comprising guard structures surrounding the large area doping (140).

19. A semiconductor radiation detector device according to any of claims 1 or 3, comprising guard structures surrounding the radiation entry window (110).

20. A semiconductor radiation detector device according to any of claims 18 or 19, wherein the guard structures are formed of the electrode means.

21. A semiconductor radiation detector device according to claims 18 and 19, wherein the guard structures comprise any of the following: dopings of the second conductivity type, dopings of the first conductivity type, conductor-insulator- semiconductor structures, Schottky contacts, etched grooves.

22. A semiconductor radiation detector device according to claim 1, wherein a contact is made to a neutral area at the border of a detector chip that comprises said transport layer (120, 330), said collector electrode (160, 1525), said doping layer (140) of the second conductivity type and said electrode means (151 - 154, 351 - 359, 751 - 753, 1251 - 1253, 1451 - 1456).

23. A semiconductor radiation detector device according to claim 1, wherein an antireflection coating or a thin metal layer exists on top of the radiation entry window (110).

24. A method for detecting radiation, comprising:

- illuminating a semiconductor radiation detector with radiation, causing mobile charge carriers to appear in a transport layer (120, 330) that exhibits a first conductivity type, - coupling electrode means (151 - 154, 351 - 359, 751 - 753, 1251 - 1253, 1451 -

1456) on a surface of the transport layer (120, 330) selectively to voltages in order to control the flow of the mobile charge carriers in the transport layer (120, 330) and

- collecting mobile charge carriers from the transport layer (120, 330) to a collector electrode (160, 1525) continuously or discontinuously;

characterized in that the method comprises:

- collecting of surface generated first type charges by the coupling electrode means (151 - 154, 351 - 359, 751 - 753, 1251 - 1253, 1451 - 1456), in order to prevent the said surface generated first type charges from mixing with the mobile primary charge carriers present in the transport layer (120, 330).

25. A method according to claim 24, characterized in that it comprises collecting surface generated secondary charges from said doping layer (140) of the second conductivity type to an electrode (170) connected to said doping layer (140) of the second conductivity type.