WO2006005803A1

WO2006005803A1 - Semiconductor radiation detector

Info

Publication number: WO2006005803A1
Application number: PCT/FI2005/050242
Authority: WO
Inventors: Artto Aurola
Original assignee: Artto Aurola
Priority date: 2004-07-09
Filing date: 2005-06-28
Publication date: 2006-01-19
Also published as: FI20040966A0; FI20040966A

Abstract

The detector comprises a substrate (300) of a first semiconductor material. At least one pixel (312-315) and a surface contact (310) have been formed on the first surface (301) and a layer (320) of a second semiconductor material has been formed on the second surface (302) of the substrate (300). A reverse bias voltage (350) is connected between the surface contact (310) and the at least one pixel (312-315) in order to create a depletion region (332) in the substrate (300). The work function of an n-type layer (320) must be smaller than the work function of the substrate (300) and the electron affinity of said layer (320) must be smaller than the electron affinity of the substrate (300). The work function of a p-type layer (320) must be bigger than the work function of the substrate (300) and the sum of the electron affinity and the band gap potential of said layer (320) must be bigger than the sum of the electron affinity and a band gap potential of the substrate (300).

Description

SEMICONDUCTOR RADIATION DETECTOR

FIELD OF THE INVENTION

The present invention relates to a semiconductor radiation detector according to the preamble of claim 1.

BACKGROUND OF THE INVENTION

The operation principle of semiconductor radiation detectors is based on a depleted volume of semiconductor material. Radiation entering the semiconductor and having energy greater than the band gap lifts electrons from the valence band to the conduction band. The missing electrons in the valence band, from now on referred to as holes, and the excess conduction band electrons will soon recombine in areas where the semiconductor material is neutral. Inside a depleted, non-neutral volume, the situation is different: the electron hole pairs are separated by an electric field and there are no free carriers, i.e. holes or conduction band electrons to recombine with. The radiation dose, absorbed in the depleted volume and in regions close to the borders of the depleted volume, can be measured by counting the amount of the electrons or holes induced by the radiation. The measured charge type is later on referred to as the signal charge. Further on the signal charge is referred to as the primary charge and the opposite charge type is referred to as the secondary charge unless otherwise noted. The depleted volume is typically created by a reverse biased junction of a p-type and an n-type semiconductor material. Instead of a reverse biased p-n junction a forward biased p-n junction can also be used, which is the case in solar cells. The p-type semiconductor material is doped with impurity atoms adding excess holes in the valence band, and the n-type semiconductor material is doped with impurity atoms adding excess electrons in the conduction band. The excess charges of either type are also called majority carriers and areas doped with n-type or p-type dopants are referred to as areas having n-type or p-type conductivity. Semiconductor radiation detectors having a thin homogenous radiation entry window on the back side of the detector are used to optimize the response to shallow penetrating radiation like blue light, ultra violet (UV) radiation, low energy X-rays and low energy particles. Response to the shallow penetrating radiation is later on referred to as the blue response.

Such back illuminated semiconductor radiation detectors can be divided into two different groups. In the first group the secondary charges are collected between the pixels inside the active area (the active area refers to the area containing the pixels). The advantage of this is that the collection of the secondary charges does not limit the detector size. The disadvantage is that a neutral area is present on the backside of the detector. The signal charges move by diffusion in the neutral area, which degrades the spatial resolution of the detector. Another problem is that a part of the signal charges recombine in the neutral area before reaching the depletion region boundary on the front side of the detector. For these reasons the semiconductor substrate has to be thinned down to not more than a few tens of micrometers. The response to deeply penetrating radiation is, however, poor in such thin detectors. Another issue is radiation that has slightly higher energy than the band gap of the semiconductor material like near infrared light in silicon. Such deeply penetrating radiation may reflect many times between the interfaces of a thin detector before being absorbed causing unwanted interference patterns in the images.

Almost all back illuminated charge coupled devices (CCDs) belong to the first group of semiconductor radiation detectors, i.e. the secondary charges are collected inside the active area by channel stop structures surrounding the buried channels which collect and transport the signal charges. These devices are typically produced on a p-type silicon substrate. A thin non-conducting oxide layer is formed on the backside of such a device even at room temperature. The oxide layer is always positively charged, which results in a backside depletion region or well. The backside well acts as a trap for the primary charges, which degrades the blue response of the device. This problem is avoided in US 4,798,958, US 5,005,063 (CON of US 4,760,031) and US 4,963,925 by the formation of a 2D charge gas layer at the silicon - silicon oxide interface. The 2D charge gas layer refers here to a thin sheet of holes (or electrons) and not to a physical layer. In US 4,798,958 the 2D charge gas layer is achieved by a technique called UV flooding where positively charged defects in the thin backside oxide layer are filled with UV exited electrons. In US 5,005,063 the 2D charge layer is formed by introducing a very thin layer of metal having a higher work function than silicon on top of the thin backside oxide layer. In US 4,963,925 the 2D charge gas layer is achieved by using a thin biased metal layer on top of the thin backside oxide layer. On the front side of the device a 2D charge gas layer is formed during the signal integration phase between the silicon - silicon oxide interface at the locations of the buried channels, which is referred to as the multi pinned-phase (MPP) operation.

The 2D charge gas layer prevents the interface generation current from forming which can be easily deduced from the Shockley Read Hall (SRH) equation. An interface has a high density of defects and thus it is typical that the interface generation current is the major source of leakage current. If the interface generation current is removed the noise level of the detector can be reduced considerably.

The second group of back illuminated detectors has a thin conducting layer on the backside of the detector. The neutral area on the backside of the semiconductor substrate can be removed by applying a suitable bias to the conducting backside layer. In this manner the substrate in the active area of the detector can be fully depleted. An electric field exists through out the fully depleted substrate transporting the signal charges towards the front side of the detector. This drifting process offers improved spatial resolution compared to the diffusion process present in the neutral backside area of the detectors belonging to the first group. Secondly the semiconductor substrate can be much thicker than in the detectors belonging to the first group. A thick substrate enables a good response to deeply penetrating radiation beside a good blue response and it reduces the unwanted interference patterns caused for instance by near infrared radiation in thin silicon detectors. A thick enough substrate is also self-supporting, i.e. a thinning process where the front side of the substrate is mounted on a support substrate and the backside of the substrate is thinned is not necessary.

The conducting backside layer should be thin enough to enable good blue response. On the other hand the sheet resistance of the conducting backside layer should be low enough so that large secondary charge currents produced by bright images would not cause big voltage differences in the conducting backside layer. A thicker conducting backside layer results in a lower sheet resistance and vice versa. A thin conducting backside layer may thus limit the size of the detector. The thin conducting backside layer is also prone to scratches and contamination during the manufacturing process. It is thus obvious that the conducting backside layer should be manufactured carefully preferably at the end of the process. The front side of the detector contains usually metal layers having a low melting point like aluminum. A low temperature process is thus usually required to manufacture the conducting backside layer.

In US 6,025,585 the conducting backside layer is formed of a thin silicon layer. A heavily doped poly silicon layer is deposited in low temperature on the backside of a back illuminated detector in the end of the manufacturing process. This solution has, however, the drawback that the interface between the single crystalline silicon and the poly silicon layer is depleted when the device is in operation. A lot of leakage current can thus be expected to occur at the interface, which has a high density of defects. The same problem concerns also the 3D radiation detectors presented in US 6,204,087 (CIP of US 5,889,313).

In US 6,504,178 the conducting backside layer is formed inside the semiconductor substrate. More precisely said backside of the detector substrate is implanted with a dopant being of the same type as the substrate and a high temperature annealing step is done before the metal wirings are made on the front side of the device. The high temperature annealing step removes lattice defects formed during the implantation process. However, the high temperature of the annealing step thickens the doped area of the conducting backside layer. In addition to that some defects acting as traps or generation centers still remain at the most densily doped regions of the conducting backside layer. To improve the blue response the conducting backside layer is thinned as the last process step. The drawback is that the thinning process is not easy to perform. If too much of the conducting backside layer is removed a too high sheet resistance is the result. If too little is removed a poor blue response is the result. Another drawback is that a self-supporting substrate is for many purposes too thick and the substrate has to be thinned from the backside after the front side of the device is finished. In such case the afore described method is not possible unless all the materials on the front side of the detector can withstand the high annealing temperature or laser annealing of the conducting backside layer is performed. Either of the too condition will complicate the manufacturing process of the detector.

One can also use molecular beam epitaxy (MBE) to create the conducting backside layer without forming an additional interface between the substrate and the conducting backside layer. The MBE process is, however, very expensive and involves vacuum chambers. If any air is left between the substrate and a support substrate the devices are easily damaged in the vacuum. A low enough process temperature is also hard to achieve.

BRIEF DESCRIPTION OF THE INVENTION

It is an object of the present invention to provide a semiconductor radiation detector, which solves or minimizes said problems of prior art detectors. This object is achieved by means of the features of the characterizing portion of claim 1.

The main idea is to provide an interface between a second semiconductor material and a substrate of a first semiconductor material. The work function, the electron affinity and the band gap potential of the second semiconductor material compared to the corresponding values of the substrate must be such that a 2D charge gas layer is formed at the interface between the second semiconductor material and the substrate. The 2D charge gas layer prevents the generation of an interface current at the interface between the second semiconductor material and the substrate. The interface may thus have a lot of defects, which enables a variety of manufacturing processes including low temperature processes to be used to produce the structure of the second semiconductor material. Both the structure of the second semiconductor material and the 2D charge gas layer are used to transport current, which results in a low sheet resistance. The 2D charge gas layer can withstand high reverse bias voltages between a substrate contact and an oppositely doped contact.

The construction according to the invention can be used in 2D and 3D detectors. 2D detectors are detectors where the electrodes do not penetrate deeper into the substrate. The electrodes are formed on the surface of the substrate or penetrate only very little into the substrate. 3D detectors are detectors where the electrodes (3D electrodes) penetrate deeper into the substrate.

It is further advantageous that the sheet resistance of the second semiconductor material is smaller than the sheet resistance of the 2D charge gas layer formed in the interface between the second semiconductor material and the substrate. The result of this will be that a greater part of the current caused by the secondary charges will flow in the second semiconductor material than in the 2D charge gas layer. BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 shows a prior art back illuminated semiconductor detector having a conducting layer on the backside of the detector.

Fig. 2 shows a prior art back illuminated semiconductor detector having a non¬ conducting silicon oxide layer on the backside of the detector.

Fig. 3 shows a first embodiment of a 2D semiconductor detector according to the invention.

Fig. 4 shows a second embodiment of a 2D semiconductor detector according to the invention.

Fig. 5 shows a front view of the 2D semiconductor detector shown in Fig. 3.

Fig. 6 shows a junction according to the invention between two different types of n-type semiconductor layers.

Fig. 7 shows a junction according to the invention between two different types of p-type semiconductor layers.

Fig. 8 shows a cross-section of a semiconductor detector according to the invention and corresponding to the junction shown in Fig. 6.

Fig. 9 shows a cross-section of a semiconductor detector according to the invention and corresponding to the junction shown in Fig. 7.

Fig. 10 shows a first embodiment of a 3D semiconductor detector according to the invention. Fig. 11 shows a second embodiment of a 3D semiconductor detector according to the invention.

Fig. 12 shows a third embodiment of a 3D semiconductor detector according to the invention.

Fig. 13 shows a fourth embodiment of a 3D semiconductor detector according to the invention.

Fig. 14 shows an embodiment of a planar semiconductor detector according to the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Fig. 1 shows a prior art back illuminated semiconductor detector of said second group having a conducting layer on the backside of the detector. The semiconductor substrate 100 is of a first conductivity type (n-type or p-type semiconductor material) and has a front surface 101 and a back surface 102 opposite to the front surface 101. The front surface 101 comprises a doped semiconductor region 110 of the first conductivity type acting as the substrate contact. The substrate contact 110 surrounds a biased guard ring 111, which in turn surrounds doped semiconductor regions 112 - 115 of a second conductivity type acting as pixels. The area covering the pixels is the active area of the detector. The substrate 100 has a conducting layer 120 on the back surface, which is formed of doped semiconductor region of the first conductivity type. A suitable reverse bias voltage is applied between the substrate contact 110 and the pixels 112 - 115 in order to create a depletion region 132 in the substrate 100. The applied reverse bias voltage is preferably such that the border 130 of the depletion region 132 reaches the conducting layer 120 on the back surface of the detector. A neutral area 131 surrounds the depletion region 132. Radiation entering the depletion region 132 in the substrate 100 creates electron hole pairs, which are separated by the electric field present in the depletion region 132. The primary charges are collected by the pixels 112 - 115. The secondary charges drift to the conducting layer 120 on the back surface of the substrate 100 and are transported inside said conducting layer 120 to the borders of the substrate 100. At the boarders of the substrate 100 the secondary charges flow through the neutral area 131 of the substrate 100 and are collected by the substrate contact 110.

Fig. 2 shows a prior art back illuminated semiconductor detector having a non¬ conducting silicon oxide layer on the back surface of the detector. The only difference between the detector shown in Fig. 1 and the detector shown in Fig. 2 is in the layer 121 at the back surface 102 of the detector. A silicon oxide non¬ conducting layer 121 on the back surface 102 of the substrate 100 is used in the detector shown in Fig. 2 instead of the conducting layer 120 on the back surface 102 of the substrate 100 used in the detector shown Fig. 1. It is now assumed that the first conductivity type is n-type, that the second conductivity type is p-type and that the substrate 100 is silicon. Due to the positive oxide charge in the silicon oxide layer 121 a 2D electron gas layer is created inside the n-type substrate 100 at the silicon - silicon oxide interface. This 2D electron gas layer is also sometimes called an accumulation layer. The 2D electron gas layer does not refer to a physical layer but to a two-dimensional electron gas layer. In operation a suitable reverse bias is applied between the substrate contact 110 and the pixels 112 - 115 in order to fully deplete the substrate 100 in the active area 132. However, the potential of the 2D electron gas layer will not change, i.e. the potential of the 2D electron gas layer is the same as the potential of the substrate contact 110 as long as no secondary current is running. This holds until the reverse bias between the substrate contact 110 and the pixels 112 - 115 is high enough to remove the 2D electron gas layer. In operation the secondary charges i.e. electrons drift to the 2D electron gas layer and are transported inside said 2D electron gas layer to the borders of the substrate 100. At the borders of the substrate 100 the secondary charges flow through the neutral area 131 of the substrate 100 and are collected by the substrate contact 110. An estimate of said 2D charge (hole or electron) gas layer removal can be easily calculated. If the detector is made of an n-type silicon wafer having a high resistance, a thickness of 300 μm and a doping concentration of 10¹² dopant atoms/cm³, the substrate 100 can be depleted with 70 V. If the backside oxide layer 121 has a concentration of 10¹² positive oxide charge defects/cm², a 2D charge gas layer having approximately the same amount of electrons is formed in thermal equilibrium. To remove all these electrons one needs an additional voltage of 4600 V. In this case the voltage needed to deplete the 2D charge gas layer is almost 70 times bigger than the voltage needed to fully deplete the substrate 100.

US 5,424,565 shows a detector in accordance with Fig. 1. If the substrate of the detector presented in this US patent is not attached to a read out chip and if the detector is illuminated from the back, the detector corresponds to the detector presented in Fig. 2, i.e. the detector substrate has only the non-conducting oxide layer on the backside of the device. The detector in Fig. 2 has the advantage due to the 2D charge gas layer that no interface current is generated at the interface between the silicon oxide layer 121 and the silicon substrate 100. The disadvantage is, however, that the sheet resistance of the 2D charge gas layer is relatively high resulting in an undesirably high voltage drop in the 2D charge gas layer in case of a bright image. Another problem is that negatively charged water ions easily contaminate the surface of the silicon oxide layer 121. This can be avoided by depositing a layer of suitable material on top of the backside silicon oxide layer 121, which, however, reduces the blue response of the device.

Fig. 3 shows a first embodiment of a 2D semiconductor detector according to the invention. This embodiment is based on an n-type substrate 300 of a first semiconductor material having a first surface 301 and a second surface 302. This embodiment corresponds to the semiconductor detectors shown in Figs. 1 and 2 except for the layer 320 of the second semiconductor material on the second surface 302 of the substrate 300. The layer 320 of the second semiconductor material is of a heavily doped n-type semiconductor material. The first surface 301 contains doped p-type semiconductor regions 312-315 acting as pixels. The pixels 312-315 are surrounded by a biased semiconductor guard ring 311, which in turn is surrounded by a heavily doped n-type semiconductor region 310 forming the substrate contact. A reverse bias voltage 350 is connected between the pixels 312-315 and the substrate contact 310. Only the reverse bias voltage 350 between the pixel 315 and the substrate contact 310 is shown in the figure. The applied reverse bias voltage 350 is preferably such that the border 330 between the depletion region 332 and the neutral region 331 of the substrate 300 reaches the conducting layer 320 on the second surface 302 of the detector. Radiation entering the depletion region 332 in the substrate 300 will generate primary charges (holes in this case) and secondary charges (electrons in this case) in the depletion region 332. The primary charges (holes in this case) will be transported by the reverse bias voltage 350 towards the pixels 312-315 on the first surface 301 of the substrate 300. The primary charges (holes in this case) can then be collected from the pixels 312-315. The secondary charges (electrons in this case) will be transported by the reverse bias voltage 350 towards the layer 320 of the second semiconductor material on the second surface 302 of the substrate 300. The function of the layer 320 of the second semiconductor material will be described in connection with Fig. 6.

Fig. 4 shows a second embodiment of a 2D semiconductor detector according to the invention. This embodiment is based on a p-type substrate 400 of a first semiconductor material having a first surface 401 and a second surface 402. This embodiment corresponds to the semiconductor detectors shown in Figs. 1 and 2 except for the layer 420 of a second semiconductor material on the second surface 402 of the substrate 400. The layer 420 of the second semiconductor material is of a heavily doped p-type semiconductor material. The first surface 401 contains doped n-type semiconductor regions 412-415 acting as pixels. The pixels 412-415 are surrounded by an optional preferably floating p-type channel stop doped region 416. The active area containing the pixels 412-415 is surrounded by a biased semiconductor ring 411, which in turn is surrounded by a heavily doped p- type semiconductor region 410 forming the substrate contact. A reverse bias voltage 450 is connected between the pixels 412 - 415 and the substrate contact 410. Only the reverse bias voltage 450 between the pixel 415 and the substrate contact 410 is shown in the figure. The applied reverse bias voltage 450 is preferably such that the border 430 between the depletion region 432 and the neutral region 431 of the substrate 400 reaches the conducting layer 420 on the second surface 402 of the detector. Radiation entering the depletion region 432 in the substrate 400 will generate primary charges (electrons in this case) and secondary charges (holes in this case) in the depletion region 432. The primary charges (electrons in this case) will be transported by the reverse bias voltage 450 towards the pixels 412-415 on the first surface 401 of the substrate 400. The primary charges (electrons in this case) can then be collected from the pixels 412- 415. The secondary charges (holes in this case) will be transported by the reverse bias voltage 450 towards the layer 420 of the second semiconductor material on the second surface 402 of the substrate 400. The function of the layer 420 of the second semiconductor material will be described in connection with Fig. 7.

Fig. 5 shows a front view of the 2D semiconductor detector shown in Fig. 3. Rectangular pixels 312-315 are formed as doped regions in the first surface 301 of the substrate 300. The pixels 312-315 are surrounded by a rectangular biased guard-ring 311 formed as a doped region in the first surface 301 of the substrate 300. The biased guard-ring 311 is in turn surrounded by a rectangular substrate contact 310 formed as a doped region in the first surface 301 of the substrate 300.

A detector according to the invention could also comprise additional metal layers, isolator layers or possible support substrates, but these are not shown in Figs 3-5. The detector according to the invention can be an active pixel sensor (APS) having an integrated first amplifier stage in each pixel or it can be a charge transfer device (CTD) like the fully depleted back illuminated CCD presented in US 6,259,085 (CIP of US 6,025,585). In the latter device a conducting layer is added to the second surface of the CCD. This conductive layer is biased to fully deplete the substrate. If the device e.g. in Fig. 4 was a CCD the doped regions 412-415 would function as buried channels on top of which would be an isolation layer and the gates.

Fig. 6 shows a hetero junction according to the invention between two different semiconductor materials of n-type. This corresponds to the junction between the substrate 300 of the first semiconductor material and the layer 320 of the second semiconductor material on the second surface 302 of the substrate 300 in Fig. 3. A 2D electron gas layer 340 is formed inside the substrate 300 at the interface of the substrate 300 and the layer 320 of the second semiconductor material if the following criteria are fulfilled. The work function Φc of the layer 320 of the second semiconductor material must be smaller than the work function Φs of the substrate 300 and the electron affinities X_c of the layer 320 of the second semiconductor material must be smaller than the electron affinities of the substrate Xs.

Fig. 7 shows a hetero junction according to the invention between two different semiconductor materials of p-type. This corresponds to the junction between the substrate 400 of the first semiconductor material and the layer 420 of the second semiconductor material on the second surface 402 of the substrate 400 in Fig. 4. A 2D hole gas layer 440 is formed inside the substrate 400 at the interface of the substrate 400 and the layer 420 of the second semiconductor material if the following criteria are fulfilled. The work function Φc of the layer 420 of the second semiconductor material must be greater than the work function Φs of the substrate 400 and the sum of the electron affinities Xc and the band gap potential B_gC/q of the layer 320 of the second semiconductor material must be greater than the sum of the electron affinities Xs and the band gap potential B_gs/q of the substrate 400. E_g is the energy gap between the conduction and the valence band edges and q is the elementary charge. The energy gap E_g divided by the elementary charge q is referred to as the band gap potential.

When a detector according to the invention having the layer 320, 420 of the second semiconductor material is used in optical applications, it is beneficial that the inequality E_gs < E_gc is fulfilled in the embodiment shown in Fig. 3 (Fig. 6) and in the embodiment shown in Fig. 4 (Fig. 7).

In Figs 6 and 7 the n-type and p-type materials of the layers 320 (n+), 420 (p+) of the second semiconductor material are degenerated, i.e. the Fermi level 342 is inside the conduction band of the second semiconductor material 320 in Fig. 6 and the Fermi level 441 is inside the valence band of the second semiconductor material 420 in Fig. 7. A degenerated semiconductor material is very heavily doped. Such a heavy doping reduces the sheet resistance and allows the use of thin layers enabling good blue response. It is, however, not mandatory that the layers 320, 420 of the second semiconductor material are degenerated. It is only necessary that the layer 320 of the second semiconductor material in Fig. 6 is of n- type and that the layer 420 of the second semiconductor material in Fig. 7 is of p- type. The substrate 300, 400 material in Figs 6 and 7 has a high resistance which is, however, not mandatory. The substrate 300 in Fig. 6 can also be p-type and the substrate 400 in Fig. 8 can also be n-type; these situations will be dealt with later on.

The layers 320, 420 of the second semiconductor material used in the embodiments shown in Figs. 3 and 4 will now be explained more in detail. A suitable reverse bias voltage 350, 450 is applied between the substrate contact

310, 410 and the pixels 312 - 315, 412 - 415 to fully deplete the substrate 300,

400 in the active area 332, 432. The 2D charge gas layer is, however, affected only a little. This situation is similar to the situation in the prior art solution shown in Fig. 2. The primary charges (holes or electrons) are collected by the pixels 312

- 315, 412 - 415. The secondary charges (holes or electrons) drift to the 2D charge gas layer. The secondary charges (holes or electrons) are transported inside the 2D charge gas layer and inside the layer 320, 420 of the second semiconductor material to the borders of the substrate 300, 400. From the borders of the substrate 300, 400 the secondary charges (holes or electrons) flow through the neutral area 331, 431 to the substrate contact 310, 410 where they are collected.

Fig 8 presents an electron potential energy diagram on the vertical cross-section 333 of the semiconductor shown in Fig. 3. On the first surface 301 of the n-type substrate 300 is a p-type doped region 315, which forms a pixel. A 2D electron gas layer 340, i.e. a thin sheet of electrons is formed inside the substrate 300 at the interface between the substrate 300 and the n-type layer 320 of the second semiconductor material, which forms a semi conducting layer on the second surface 302 of the substrate 300. Both the 2D electron gas layer 340 and the layer 320 of the second semiconductor material transport the secondary charge electrons horizontally i.e. in the direction of the surfaces 301, 302 of the substrate 300 to the borders of the substrate 300. The reverse bias voltage 350 between the layer 320 of the second semiconductor material on the second surface 302 of the substrate 300 and the pixel 315 on the first surface 301 of the substrate 300 is the difference between the hole quasi Fermi level 341 and the electron quasi Fermi level 342.

Fig 9 present electron potential energy diagram on the vertical cross-section 433 of the semiconductor detector shown in Fig 4. On the first surface 401 of the p- type substrate 400 is an n-type doped region 415, which forms a pixel. A 2D hole gas layer 440, i.e. a thin sheet of holes is formed inside the substrate 400 at the interface between the substrate 400 and the p-type layer 420 of the second semiconductor material, which forms a semi conducting layer on the second surface 402 of the substrate 400. Both the 2D hole gas layer 440 and the layer 420 of the second semiconductor material transport the secondary charge holes horizontally to the borders of the substrate 400. The reverse bias voltage 450 between the conducting semiconductor layer 420 on the second surface 402 of the substrate 400 and the pixel 415 on the first surface 401 of the substrate 400 is the difference between the hole quasi Fermi level 441 and the electron quasi Fermi level 442.

In a case where the substrate 300, 400 and the layer 320, 420 of the second semiconductor material forming the semi conducting layer on the second surface 302, 402 of the substrate 300, 400 are semiconductor materials of the same conductivity type, the 2D charge (electron or hole) gas layer 340, 440 can resist high reverse bias voltages 350, 450 applied between the first surface 301, 401 and the second surface 302, 402 of the substrate 300, 400.

In a case where the substrate 300, 400 and the layer 320, 420 of the second semiconductor material forming the semi conducting layer on the second surface 302, 402 of the substrate 300, 400 are semiconductor materials of the opposite conductivity type, the 2D charge (electron or hole) gas layer can not resist high reverse bias voltages 350, 450 applied between the first surface 301, 401 and the second surface 401, 402 of the substrate 300, 400. This is not a problem if the substrate 300, 400 is thin as only a small reverse bias voltage 350, 450 is needed to deplete a thin substrate 300, 400.

Fig. 10 shows a first embodiment of a 3D semiconductor detector according to the invention. The substrate 500 is of a first semiconductor material having a first surface 501 and a second surface 502 opposite to the first surface 501. The 3D electrodes 551, 552, 553, 554, which are of the same conductivity type as the layer 520 of the second semiconductor material on the second surface 502 of the substrate 500, are short circuited through the layer 520 of the second semiconductor material. The pixels 512, 513, 514 on the first surface 501 of the substrate 500, which collect the primary charges, are of a different conductivity type compared to the layer 520 of the second semiconductor material. The pixels 512, 513, 514 may have additional 3D electrodes 512a, 513a, 514a attached to them, said additional electrodes 512a, 513a, 514a penetrating deeper into the substrate 500. A reverse bias voltage is applied between the short-circuited region 520, 551, 552, 553, 554 and the pixels 512, 513, 514. Depending on the semiconductor materials forming the 3D electrodes a 2D charge gas layer can be achieved at the interface between either or both types of the 3D electrodes and the substrate 500. Depending on the semiconductor material of the layer 520 a 2D charge gas layer can be formed at the interface between the layer 520 and the substrate 500. If the substrate 500 is of the same type of doping as the short- circuited region 520, 551, 552, 553, 554 the 3D electrodes 551, 552, 553, 554 belonging to the short-circuited region may have any form. If the short-circuited region 520, 551, 552, 553, 554 and the substrate 500 are oppositely doped the 3D electrodes 551, 554 at the borders of the substrate 500 preferably form a continuous 3D electrode structure surrounding the pixels 512, 513, 514 completely. The 3D electrodes may also form a single net like structure surrounding all the pixels 512, 513, 514. The substrate 500 inside the 3D electrodes 551 and 554 is fully depleted.

Fig. 11 shows a second embodiment of a 3D semiconductor detector according to the invention. The substrate 500 is of a first semiconductor material and has a first surface 501 and a second surface 502 opposite to the first surface 501. The only difference in the embodiment shown in Fig. 11 compared to the embodiment shown in Fig 10 is in the short-circuited electrodes 551, 554 at the border of the substrate 500. The short-circuited 3D electrodes 551, 554 at the border of the substrate 500 in the embodiment shown in Fig. 11 form a continuous structure surrounding the pixels 512, 513, 514. The other short-circuited 3D electrodes 552, 553 may also surround individual pixels 512, 513, 514. The substrate 500 inside the 3D electrodes 551 and 554 is fully depleted.

Fig. 12 shows a third embodiment of a 3D semiconductor detector according to the invention. The substrate 500 is of a first semiconductor material and has a first surface 501 and a second surface 502 opposite to the first surface 501. The embodiment shown in Fig. 12 differs from the embodiments shown in Figs. 3 and 4 only regarding the pixels 512 - 516. 3D elements 512a - 516a have been attached to the pixels 512 - 516. There can be a 2D charge gas layer at the first interface between the 3D electrodes 512a - 516a and the substrate 500 or at the second interface between the layer 520 of the second semiconductor material and the substrate 500 or at both interfaces. The substrate contact 510 is of the same conductivity type as the layer 520 of the second semiconductor material and the substrate 500. A reverse bias voltage is connected between the pixels 512 - 516 and the substrate contact 510. The depletion area in this embodiment corresponds to that of the embodiment shown in Figs. 3 and 4.

Fig. 13 shows a fourth embodiment of a 3D semiconductor detector according to the invention. The substrate 500 is of a first semiconductor material having a first surface 501 and a second surface 502 opposite to the first surface 501. There are 3D electrodes of a first conductivity type 520b, 520c and 3D electrodes of a second conductivity type 512a, 513a, 514a extending through the substrate 500 from the first surface 501 of the substrate 500 to the second surface 502 of the substrate 500. The 3D electrodes 512a, 513a, 514a, 520b, 520c are surrounded by an optional electrode 560. The electrodes of the first conductivity type 520b, 520c can be of a second semiconductor material forming a 2D charge gas layer at the interface between the electrodes 520b, 520c and the substrate 500. Also the 3D electrodes of the second conductivity type 512a, 513a, 514a can be of a different second semiconductor material forming a 2D charge gas layer at the interface between the electrode 512a, 513a, 514a and the substrate 500. Either conductivity type of 3D electrodes or both conductivity types of 3D electrodes can be used as pixels collecting the primary charges. A reverse bias voltage is applied between the different types of 3D electrodes. The substrate 500 inside the 3D electrodes 560 is fully depleted.

We could have a situation where the substrate 500 is of n-type conductivity, the 3D electrodes 520b, 520c are of n-type conductivity and the 3D electrodes 512a,

513a, 514a are of p-type conductivity. The electrons produced by radiation in the substrate 500 would move to the n-type electrodes 520b, 520c and the holes produced by radiation in the substrate 500 would move to the p-type electrodes 512a, 513a, 514a. In the case where both the n-type and the p-type electrodes are made of a different second semiconductor material a 2D electron gas layer will occur at the interface between the n-type 3D electrodes 520b, 520c and the substrate 500 and a 2D hole gas layer at the interface between the p-type 3D electrodes 512a, 513a, 514a and the substrate 500. When a reverse bias voltage is connected between the n-type 3D electrodes 520b, 520c and the p-type 3D electrodes 512a, 513a, 514a a depletion area is formed in the n-type substrate 500 around the p-type 3D electrodes 512a, 513a, 514a. When the reverse bias voltage is big enough the depletion area will reach the n-type 3D electrodes 520b, 520c. The 2D electron gas layer around the n-type 3D electrodes 520b, 520c can withstand a high reverse bias voltage in contrast to the 2D hole gas layer around the p-type 3D electrodes 512a, 513a, 514a. The electrons can be primary charges and the holes secondary charges or vice versa. The signal charges i.e. the charges used to measure the radiation can be electrons or holes. The electrons can be transported in the n-type 3D electrodes 520b, 520c and the 2D electron gas layer around the n-type 3D electrodes 520b, 520c to either surface 501, 502 of the substrate 500. The holes can be transported in the p-type 3D electrodes 512a, 513a, 514a and the 2D hole gas layer around the p-type 3D electrodes 512a, 513a, 514a to either surface 501, 502 of the substrate 500.

Fig. 14 shows an embodiment of a planar semiconductor detector according to the invention. The substrate 500 is of a first semiconductor material and has a first surface 501 and a second surface 502 opposite to the first surface 501. This embodiment shows a detector, which is illuminated from the first surface 501. The radiation enters through the layer 520a of the second semiconductor material, which is oppositely doped compared to the substrate 500. The secondary charges are collected by the layer 520a of the second semiconductor material and by the optional doped region 582 surrounding the layer 520a of the second semiconductor material. In this embodiment secondary charges instead of primary charges are signal charges, i.e. the secondary charges are measured. The doped region 590 forms a first region in the first surface 501 of the substrate 500. Said first region 590 forms a substrate contact and preferably surrounds the doped region 582 and the layer 520a of the second semiconductor material. The structure comprising the layer 520a of the second semiconductor material and the doped region 582 can be used as pixels. There can be any number of these structures inside the preferably ring like substrate contact 590 or each pixel can be surrounded by the substrate contact 590. There is a 2D charge gas layer at the interface between the layer 520a of the second semiconductor material and the substrate 500. A reverse bias voltage is applied between the substrate contact 590 and the layer 520a of the second semiconductor material, which results in a depletion region 531. The border between the depletion region 532 and the neutral semiconductor material 531 is marked with hatched line 530.

In 3D detectors having 3D electrodes of only one type of conductivity (p-type or n-type) the 3D electrodes are typically of an opposite type of conductivity compared to the type of conductivity of the first semiconductor material forming the substrate. These 3D electrodes of the same type of conductivity can be formed of the second semiconductor material, which means that a 2D charge gas layer exists at the interface between the 3D electrodes and the substrate surrounding the 3D electrodes. In 3D detectors having 3D electrodes of both conductivity types the 3D electrodes can be made of two different semiconductor materials. In case both semiconductor materials fulfill the requirements relating to the work functions, the electron affinity and the band gap potential in relation to the substrate a 2D charge gas layer exists at the interface between both types of 3D electrodes and the substrate surrounding the 3D electrodes. Alternatively the semiconductor material of 3D electrodes of only one conductivity type can be made of the second semiconductor material. In this case the 2D charge gas layer exists only at the interface between the 3D electrodes being of the second semiconductor material and the substrate surrounding the 3D electrodes and not between the 3D electrodes of the other semiconductor material and the substrate surrounding said electrodes.

In the case the first semiconductor material forming the substrate and the second semiconductor material forming the 3D electrodes have a different conductivity type the 2D charge layer at the interface between the 3D electrodes and the substrate surrounding the 3 D electrodes can not withstand a high bias voltage applied between these 3D electrodes and the substrate. This will not cause a problem if the 3D electrodes are spaced close enough as the substrate can be depleted before the 2D charge gas layer at the first interface ceases to exist. In the case the first semiconductor material forming the substrate and the second semiconductor material forming the 3D electrodes have the same conductivity type the 2D charge layer at the interface between the 3D electrodes and the substrate surrounding the 3 D electrodes can withstand a high bias voltage applied between these 3D electrodes and the substrate.

The second semiconductor material can be single crystalline, polycrystalline or amorphous. The same applies also for the substrate semiconductor material. There are no restrictions for the manufacturing process of the second semiconductor material (even MBE could be used). However, it is preferable to manufacture the layer of the second semiconductor material in low temperature for previously explained reasons. Sometimes a low temperature process is preferred to prevent the two materials from mixing at the interface. If mixing takes place a graded potential profile is formed at the interface instead of an abrupt one. This could decrease the sheet density of the charge gas layer or it might even prevent the formation of the charge gas layer. The latter is the goal in hetero junction bipolar transistors (HBTs). In high electron mobility transistors (HEMTs) the situation is the opposite, i.e. an abrupt junction is preferred. A high interface defect density will not result in increased leakage current because the charge gas layer eliminates the surface generation current. In optical applications it is desired to optimize the refractive index of the layer of the second semiconductor material with respect to the substrate in order to minimize the reflection losses. This might, however be hard to achieve. Instead, one can deposit on top of the layer of the second semiconductor material a one- layered or a multilayered anti reflection (AR) coating. In X ray and particle detectors a thin metal layer could be added on top of the layer of the second semiconductor material. The doped regions could also be replaced by suitable metal contacts forming ohmic or Scottky contacts between the substrate semiconductor material and the metal contact. Between the front and back surface of the detector device one can also introduce several subsequent n-type and p-type layers, which are fully depleted when the detector device is in operation.

The detector can be for instance an APS having an integrated first amplifier stage in each pixel or a CTD like a CCD. The secondary current can be collected from the second surface or from the first surface of the substrate outside the depletion region of the active area. Contacts on the first surface are, however, better suited for mass production. Contacts to the substrate on the first surface of the substrate can be composed of one or several point contacts or of a ring surrounding the active area. Inside this front contact ring there can be a biased ring also surrounding the active area, and between these two rings there can be floating guard rings. The biased ring and the floating guard rings being of different type of doping than the substrate. The detector is preferably back illuminated, but could also be a front illuminated device. The detector can have any amount of pixels. Especially the detector may have only one pixel corresponding thus to a pin diode.

A device that includes a detector according to an embodiment of the invention may also include other semiconductor chips, some of which may have bonded connections to the pixels of the detector. This enables building very compact structures that include detection, amplification, reading and in some cases even storage in a very small space, like a MCM (multi-chip module). The sheet resistance of the at least one second region is advantageously smaller than the sheet resistance of the 2D charge gas layer. The at least one second region will thus transport a greater part of the current compared to the 2D charge gas layer.

The substrate and the second semiconductor material used in the invention can be chosen e.g. from the group: Silicon, Germanium, Gallium Arsenide. Cadmium Telluride, Cadmium Zinc Telluride, Tallium Bromide, Lead Iodide, Mercuric Iodide, Selenium. These are suitable for detection of rδntgen radiation.

The substrate can be formed e.g. of a square having a side length from 100 micrometer to 30 cm. The thickness of the substrate can be from 5 micrometer to 5 cm. The thickness depends on which kind of radiation the detector is intended for. The depth of the doped regions on the first and second surface of the substrate can be less than 1 micrometer.

Claims

1. Semiconductor radiation detector comprising a substrate (300, 400, 500) of a first semiconductor material having a first surface (301, 401, 501) and a second surface (302, 402, 502) opposite to the first surface (301, 401, 501), said detector further comprising:

- at least one first region (312-315, 412-415, 512-516, 590) in connection with the first surface (301, 401, 501),

- at least one second region (320, 420, 520, 520a, 520b, 520c) of a second semiconductor material,

- a reverse bias voltage being applied between the at least one first region (312- 315, 412-415, 512-516, 590) and the at least one second region (320, 420, 520, 520a, 520b, 502c) creating a depletion region (332, 432, 532) in the semiconductor substrate (300, 400, 500), the rest of the semiconductor substrate (300, 400, 500) forming a neutral region (331, 431, 531), characterized in that:

- in the case the at least one second region (320, 420, 520, 520a, 520b, 520c) is an n-type semiconductor material, a work function (Φ_c) of the at least one second region (320, 420, 520, 520a, 520b, 520c) is smaller than a work function (Φ_s) of the substrate (300, 400, 500) and that an electron affinity (X_c) of the at least one second region (320, 420, 520, 520a, 520b, 520c) is smaller than an electron affinity (X_s) of the substrate (300, 400, 500),

- in the case the at least one second region (320, 420, 520, 520a, 520b, 520c) is a p-type semiconductor material, the work function (Φ_c) of the at least one second region (320, 420, 520, 520a, 520b, 520c) is bigger than the work function (Φ_s) of the substrate (300, 400, 500) and that the sum of the electron affinity (Xc) and a band gap potential (E_gC/q) of the at least one second region (320, 420, 520, 520a, 520b, 520c) is bigger than the sum of the electron affinity (Xs) and a band gap potential (E_gS/q) of the substrate (300, 400, 500), - a 2D charge gas layer (340, 440) being formed inside the substrate (300, 400, 500) at the interface of the at least one second region (320, 420, 520, 520a, 520b, 520c) and the substrate (300, 400, 500), said 2D charge gas layer (340, 440) preventing leakage current to be generated in the interface between the at least one second region (320, 420, 520, 520a, 520b, 520c) and the substrate

(300, 400, 500),

- whereas radiation entering the depletion region (332, 432, 532) in the semiconductor substrate (300, 400, 500) generate primary charges and secondary charges in the depletion region (332, 432, 532), said primary charges being transported by the reverse bias voltage towards the at least one first region (312-315, 412-415, 512-516, 590) where they are collected and said secondary charges being transported by the reverse bias voltage towards the at least one second region (320, 420, 520, 520a, 520b, 520c) and further inside the 2D charge gas layer (340, 440) and the at least one second region (320, 420, 520, 520a, 520b, 520c) to a secondary charge collecting area in the detector.

2. Semiconductor radiation detector according to claim 1, characterized in that the at least one second region (320, 420, 520) comprises a layer of the second semiconductor material applied on the second surface (302, 402, 502) of the substrate (300, 400, 500).

3. Semiconductor radiation detector according to claim 1 or 2, characterized in that the at least one first region (312-315, 412-415, 512-516) comprises a doped region in the first surface (301, 401, 501) of the substrate (300, 400, 500) and forms at least one pixel for collecting primary charges.

4. Semiconductor radiation detector according to any one of claims 1-3, characterized in that the secondary charges are collected from the at least one second region (320, 420, 520).

5. Semiconductor radiation detector according to claim 3, characterized in that the detector further comprises at least one third region (310, 410, 510) in connection with the first surface (301, 401, 501) of the substrate (300, 400, 500), the at least one third region (310, 410, 510) forming a contact to the neutral region (331, 431) of the substrate (300, 400, 500), the contact being used to collect the secondary charges from the neutral region (331, 431) of the substrate (300, 400, 500), said neutral region (331, 431) forming the secondary charge collecting area in the detector.

6. Semiconductor radiation detector according to claim 1, characterized in that the detector is illuminated from the second surface (302, 402, 502).

7. Semiconductor radiation detector according to claim 1, characterized in that the at least one second region (520b, 520c) forms 3D electrodes inside the semiconductor substrate (500).

8. Semiconductor radiation detector according to claim 1, characterized in that the at least one first region (512-516, 512a-516a) forms 3D electrodes inside the semiconductor substrate (500).

9. Semiconductor radiation detector according to claim 1, characterized in that the at least one second region (320, 420, 520, 520a, 520b, 520c) is of an amorphous, polycrystalline or single crystalline material.

10. Semiconductor radiation detector according to claim 1, characterized in that the substrate (300, 400, 500) is of an amorphous, polycrystalline of single crystalline material.

11. Semiconductor radiation detector according to claim 1, characterized in that the substrate (300, 400, 500) comprises multiple differently doped semiconductor layers.

12. Semiconductor radiation detector according to claim 1, characterized in that the primary charges are signal charges to be measured.

13. Semiconductor radiation detector according to claim 1, characterized in that the secondary charges are signal charges to be measured.

14. Semiconductor radiation detector according to claim 1, characterized in that the band gap potential (EgJq) of the at least one second region (320, 420, 520, 520a, 520b, 520c) of the second semiconductor material is larger than the band gap potential (E_gS/q) of the substrate (300, 400, 500).

15. Semiconductor radiation detector according to claim 1, characterized in that the sheet resistance of the at least one second region (320, 420, 520, 520a, 520b, 520c) is smaller than the sheet resistance of the 2D charge gas layer (340, 440).