WO2019123591A1

WO2019123591A1 - Semiconductor device

Info

Publication number: WO2019123591A1
Application number: PCT/JP2017/045852
Authority: WO
Inventors: 晴久齊藤; 良章竹本; 芳隆只木; 政康金沢
Original assignee: オリンパス株式会社
Priority date: 2017-12-21
Filing date: 2017-12-21
Publication date: 2019-06-27

Abstract

This semiconductor device comprises a semiconductor substrate, a first electrode, a second electrode, a conductive layer, and a connection layer. The semiconductor substrate has a first main surface and a second main surface facing opposite directions from one another. The first electrode and the second electrode are disposed on the first main surface. The conductive layer is disposed on the second main surface or is disposed within the semiconductor substrate in such a manner as to include the second main surface. The connection layer is disposed in a hole that is open on at least one among the first main surface and the second main surface in the semiconductor substrate, is connected electrically to the second electrode and the conductive layer, and is conductive.

Description

Semiconductor device

The present invention relates to a semiconductor device.

It is known that when a substance such as metal is irradiated with X-rays, the substance emits fluorescence of energy (wavelength) specific to the atoms of the substance. The wavelength band of fluorescence is approximately equal to the wavelength band of X-rays. The intensity of the fluorescence is very weak.

This phenomenon can be applied to the estimation of the type and amount of substances such as metals contained in an object. For this estimation, the object is irradiated with X-rays, and fluorescent X-rays emitted from the object are observed. The above estimation is performed on the basis of the energy intensity for each wavelength of light included in fluorescent X-rays, that is, on the basis of the spectrum of fluorescent X-rays.

A silicon drift detector (SDD) is disclosed that efficiently detects weak fluorescent x-rays. FIG. 12 shows the configuration of a detector 1010 configured similarly to the SDD disclosed in Patent Document 1. In FIG. 12, a cross section of detector 1010 is shown. As shown in FIG. 12, the detector 1010 includes a semiconductor substrate 1100, an insulating layer 1130, an anode electrode 1140, a cathode electrode 1150, and a plurality of gate electrodes 1180. In FIG. 12, reference numerals of two gate electrodes 1180 are shown as a representative of the plurality of gate electrodes 1180. The semiconductor substrate 1100 and the insulating layer 1130 are stacked in a direction Dr10 perpendicular to the surface 1100a of the semiconductor substrate 1100.

The semiconductor substrate 1100 includes a first semiconductor layer 1101, a second semiconductor layer 1102, a first impurity layer 1110, and a plurality of second impurity layers 1120. In FIG. 12, the symbol of one second impurity layer 1120 is shown as a representative of the plurality of second impurity layers 1120.

The first semiconductor layer 1101 and the second semiconductor layer 1102 are stacked in a direction Dr10 perpendicular to the surface 1100a of the semiconductor substrate 1100. The semiconductor substrate 1100 has a surface 1100 a and a surface 1100 b. The face 1100a and the face 1100b face in opposite directions.

The first semiconductor layer 1101 contains an N-type semiconductor. The second semiconductor layer 1102 contains a P-type semiconductor. The second semiconductor layer 1102 is configured as a layer from the surface 1100 b to a predetermined depth.

The first impurity layer 1110 and the plurality of second impurity layers 1120 are disposed in the first semiconductor layer 1101. The first impurity layer 1110 contains an N-type semiconductor. For example, the first impurity layer 1110 is formed of a semiconductor material having an impurity concentration different from that of the semiconductor material forming the first semiconductor layer 1101. The second impurity layer 1120 contains a P-type semiconductor. The surface of each of the first impurity layer 1110 and the plurality of second impurity layers 1120 constitutes a surface 1100 a. Each of the first impurity layer 1110 and the plurality of second impurity layers 1120 is configured as a layer from the surface 1100 a to a predetermined depth.

The insulating layer 1130 is stacked over the first semiconductor layer 1101. The anode electrode 1140, the cathode electrode 1150, and the plurality of gate electrodes 1180 are disposed on the surface of the insulating layer 1130. These electrodes are arranged at mutually different positions. The anode electrode 1140 is disposed at a position corresponding to the first impurity layer 1110. The cathode electrode 1150 and the plurality of gate electrodes 1180 are disposed at positions corresponding to the second impurity layer 1120.

In the insulating layer 1130, an opening is formed at a position corresponding to each of the first impurity layer 1110 and the plurality of second impurity layers 1120. The anode electrode 1140 is connected to the first impurity layer 1110 through an opening formed in the insulating layer 1130. The cathode electrode 1150 is connected to the second impurity layer 1120 through an opening formed in the insulating layer 1130. The gate electrode 1180 is connected to the second impurity layer 1120 through an opening formed in the insulating layer 1130. That is, the anode electrode 1140, the cathode electrode 1150, and the plurality of gate electrodes 1180 penetrate the insulating layer 1130. The gate electrode 1180 and the second impurity layer 1120 constitute an FET (Field Effect Transistor).

FIG. 13 is a plan view of detector 1010. In FIG. 13, each element is shown when the detector 1010 is viewed in the direction perpendicular to the surface 1100 a of the semiconductor substrate 1100. That is, in FIG. 13, each element when the detector 1010 is viewed from the front of the semiconductor substrate 1100 is shown. In FIG. 13, the insulating layer 1130 is omitted. In FIG. 13, reference numerals of one gate electrode 1180 are shown as a representative of the plurality of gate electrodes 1180.

The anode electrode 1140 is disposed at the center of the surface 1100 a of the semiconductor substrate 1100. The anode electrode 1140 is a circular electrode. The cathode electrode 1150 and the plurality of gate electrodes 1180 are ring-shaped electrodes. The cathode electrode 1150 and the plurality of gate electrodes 1180 are arranged concentrically. The cathode electrode 1150 and the plurality of gate electrodes 1180 are disposed to surround the anode electrode 1140. The cathode electrode 1150 is disposed at the outermost side. The plurality of gate electrodes 1180 are disposed between the anode electrode 1140 and the cathode electrode 1150. A cross section through line L10 shown in FIG. 13 is shown in FIG.

A voltage is applied to the anode electrode 1140, the cathode electrode 1150, and the plurality of gate electrodes 1180. The voltage applied to the anode electrode 1140 is higher than the voltage applied to the cathode electrode 1150. The voltage applied to the anode electrode 1140 is higher than any voltage applied to the plurality of gate electrodes 1180. A negative voltage is applied to the cathode electrode 1150 and the plurality of gate electrodes 1180. The voltage applied to the plurality of gate electrodes 1180 is higher than the voltage applied to the cathode electrode 1150. The voltage applied to the inner gate electrode 1180 is higher than the voltage applied to the outer gate electrode 1180. A voltage is applied to the anode electrode 1140, the cathode electrode 1150, and the plurality of gate electrodes 1180 such that the potential inside the semiconductor substrate 1100 increases from the outer periphery of the semiconductor substrate 1100 toward the center.

The electrodes are disposed on the surface 1100 b of the semiconductor substrate 1100. That is, the electrode is disposed on the second semiconductor layer 1102. A voltage lower than that applied to the anode electrode 1140 is applied to that electrode. Thus, a voltage is applied to the second semiconductor layer 1102. The second semiconductor layer 1102 functions as a cathode electrode. A voltage is applied to the second semiconductor layer 1102 such that the internal potential of the semiconductor substrate 1100 increases from the surface 1100b toward the surface 1100a.

A voltage as described above is applied to detector 1010. The potential in the semiconductor substrate 1100 increases from the outer periphery to the center of the semiconductor substrate 1100 and also increases from the surface 1100 b to the surface 1100 a. That is, a potential gradient is generated in the semiconductor substrate 1100. The potential acting on the electrons decreases from the outer periphery of the semiconductor substrate 1100 toward the center, and decreases from the surface 1100 b to the surface 1100 a. That is, a potential gradient is generated in the semiconductor substrate 1100. When X-rays enter the detector 1010, electrons are generated in the semiconductor substrate 1100. The electrons gather at the anode electrode 1140 according to the potential gradient. A signal based on the electrons is output from detector 1010.

FIG. 14 shows the configuration of a detector 1011 configured similarly to the other SDD disclosed in Patent Document 1. In FIG. 14 a cross section of the detector 1011 is shown. As shown in FIG. 14, the detector 1011 includes a semiconductor substrate 1100, an insulating layer 1130, an anode electrode 1140, and a cathode electrode 1150. Regarding the configuration shown in FIG. 14, points different from the configuration shown in FIG. 12 will be described.

The plurality of gate electrodes 1180 shown in FIG. 12 are not disposed in the detector 1011. Except for this point, the configuration shown in FIG. 14 is the same as the configuration shown in FIG.

As shown in FIG. 14, in the detector 1011, a plurality of gate electrodes 1180 constituting an FET are not disposed. Therefore, it is hard to produce the dielectric breakdown by the rapid change of the voltage applied to an electrode.

FIG. 15 shows the configuration of another prior art detector 1012. In FIG. 15, a cross section of the detector 1012 is shown. As shown in FIG. 15, the detector 1012 includes a semiconductor substrate 1103, an insulating layer 1130, an anode electrode 1140, and a plurality of gate electrodes 1190. In FIG. 15, reference numerals of two gate electrodes 1190 are shown as a representative of the plurality of gate electrodes 1190. The configuration shown in FIG. 15 will be described about differences from the configuration shown in FIG.

As shown in FIG. 15, in the detector 1012, the semiconductor substrate 1100 shown in FIG. 12 is changed to a semiconductor substrate 1103. In the semiconductor substrate 1103, the first semiconductor layer 1101 shown in FIG. 12 is changed to a first semiconductor layer 1104. In the first semiconductor layer 1104, the plurality of second impurity layers 1120 shown in FIG. 12 are not provided. A plurality of gate electrodes 1190 are disposed on the surface of the insulating layer 1130 instead of the cathode electrode 1150 and the plurality of gate electrodes 1180 shown in FIG. The voltage applied to the inner gate electrode 1190 is higher than the voltage applied to the outer gate electrode 1190.

Except for the points described above, the configuration shown in FIG. 15 is the same as the configuration shown in FIG.

In the detector 1012 shown in FIG. 15, the plurality of second impurity layers 1120 are not disposed. In addition, the plurality of gate electrodes 1190 do not penetrate through the insulating layer 1130. Therefore, the detector 1012 can be easily manufactured as compared with the detector 1010.

Japanese Patent Application Laid-Open No. 2008-258348

The configurations shown in FIGS. 12 to 15 require a structure for applying a voltage to both the electrode disposed on one surface of the semiconductor substrate and the electrode disposed on the other surface of the semiconductor substrate. For example, in the detector 1010 illustrated in FIG. 12, a structure for applying a voltage to the anode electrode 1140, the cathode electrode 1150, and the plurality of gate electrodes 1180 disposed on the surface 1100a is required. In addition, a structure for applying a voltage to an electrode connected to the second semiconductor layer 1102 included in the surface 1100 b is required. The structure for applying a voltage to the electrode includes a wire or the like connected to the electrode.

A structure is required to apply a voltage to the electrodes on both of the two sides of the semiconductor substrate. Therefore, it is difficult to reduce the size of the detector, and the yield of the detector is reduced.

An object of the present invention is to provide a semiconductor device which can be reduced in size and which can realize improvement in yield.

According to a first aspect of the present invention, a semiconductor device includes a semiconductor substrate, a first electrode, a second electrode, a conductive layer, and a connection layer. The semiconductor substrate has a first main surface and a second main surface facing in opposite directions. The first electrode and the second electrode are disposed on the first main surface. The conductive layer is disposed on the second main surface or disposed in the semiconductor substrate so as to include the second main surface. The connection layer is disposed in a hole opened in at least one of the first main surface and the second main surface in the semiconductor substrate, and is electrically connected to the second electrode and the conductive layer. And it has conductivity.

According to a second aspect of the present invention, in the first aspect, the connection layer may be connected to the second electrode on the first main surface.

According to a third aspect of the present invention, in the first aspect, the connection layer may be configured by a cylinder which passes through the first electrode and surrounds a virtual straight line perpendicular to the first major surface.

According to a fourth aspect of the present invention, in the first aspect, the semiconductor device includes a plurality of the semiconductor devices disposed through the first electrode and surrounding a virtual straight line perpendicular to the first major surface. It may have a connection layer.

According to a fifth aspect of the present invention, in the first aspect, in a virtual plane parallel to the first main surface and passing through the semiconductor substrate, the connection layer passes through the first electrode. It may be arranged on the circumference of a virtual circle or a virtual polygon centering on a virtual straight line perpendicular to the first main surface.

According to a sixth aspect of the present invention, in the first aspect, the semiconductor device may have a plurality of the first electrodes. In the first main surface, the second electrode may be disposed so as to surround each of the first electrodes constituting the plurality of first electrodes.

According to a seventh aspect of the present invention, in the sixth aspect, in a virtual plane which is parallel to the first main surface and passes through the semiconductor substrate, the connection layer includes the plurality of first elements. It may be arranged to pass through each of the first electrodes constituting the electrodes and to surround an imaginary straight line perpendicular to the first major surface.

According to an eighth aspect of the present invention, in the sixth aspect, the semiconductor device may have a plurality of the connection layers. The number of connection layers may be smaller than the number of first electrodes.

According to each of the above aspects, the semiconductor device can be reduced in size, and an improvement in yield can be realized.

FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. It is a top view of the semiconductor device of a 1st embodiment of the present invention. FIG. 6 is a plan view of a semiconductor device of a first modified example of the first embodiment of the present invention. FIG. 16 is a plan view of a semiconductor device of a second modified example of the first embodiment of the present invention. It is sectional drawing of the semiconductor device of the 2nd Embodiment of this invention. It is a top view of the semiconductor device of a 3rd embodiment of the present invention. FIG. 35 is a plan view of a semiconductor device of a first modified example of the third embodiment of the present invention. It is a top view of the semiconductor device of the 2nd modification of a 3rd embodiment of the present invention. It is a top view of the semiconductor device of the 3rd modification of a 3rd embodiment of the present invention. FIG. 1 is a cross-sectional view of a prior art detector. FIG. 1 is a plan view of a prior art detector. FIG. 1 is a cross-sectional view of a prior art detector. 1 is a cross-sectional view of a prior art detector.

Embodiments of the present invention will be described with reference to the drawings.

First Embodiment
FIG. 1 shows the configuration of a semiconductor device 10 according to a first embodiment of the present invention. In FIG. 1, a cross section of a semiconductor device 10 is shown. The semiconductor device 10 is configured as a silicon drift detector (SDD) that detects radiation, that is, fluorescent X-rays.

The dimensions of the parts constituting the semiconductor device 10 do not necessarily follow the dimensions shown in FIG. The dimensions of the parts constituting the semiconductor device 10 may be arbitrary. The same applies to the dimensions in other cross-sectional views.

The schematic configuration of the semiconductor device 10 will be described. The semiconductor device 10 includes a semiconductor substrate 100, a first electrode 140, a second electrode 150, a third electrode 160 (conductive layer), and a connection layer 170. The semiconductor substrate 100 has a surface 101a (first main surface) and a surface 101b (second main surface) facing in opposite directions. The first electrode 140 and the second electrode 150 are disposed on the surface 101 a. The third electrode 160 is disposed on the surface 101 b and has conductivity. The connection layer 170 is disposed in a hole opened in at least one of the surface 101 a and the surface 101 b in the semiconductor substrate 100. The connection layer 170 is electrically connected to the second electrode 150 and the third electrode 160, and has conductivity.

The detailed configuration of the semiconductor device 10 will be described. As shown in FIG. 1, the semiconductor device 10 includes a semiconductor substrate 100, an insulating layer 130, a first electrode 140, a second electrode 150, a third electrode 160, a connection layer 170, and a plurality of gate electrodes 180. In FIG. 1, reference numerals of two gate electrodes 180 are shown as a representative of the plurality of gate electrodes 180. The semiconductor substrate 100, the insulating layer 130, and the third electrode 160 are stacked in a direction Dr1 perpendicular to the surface 101a of the semiconductor substrate 100.

The semiconductor substrate 100 includes a first semiconductor layer 101, a first impurity layer 110, and a plurality of second impurity layers 120. In FIG. 1, the symbol of one second impurity layer 120 is shown as a representative of the plurality of second impurity layers 120. For example, the semiconductor material forming the semiconductor substrate 100 is silicon (Si).

The first semiconductor layer 101 contains an N-type semiconductor. The first semiconductor layer 101 has a surface 101 a and a surface 101 b. The face 101a and the face 101b face in opposite directions to each other. The surface 101 a and the surface 101 b constitute the main surface of the semiconductor substrate 100. The main surface is a relatively wide surface among a plurality of surfaces forming the surface of the semiconductor substrate 100.

The first impurity layer 110 and the plurality of second impurity layers 120 are disposed in the first semiconductor layer 101. The first impurity layer 110 contains an N-type semiconductor. For example, the first impurity layer 110 is formed of a semiconductor material having an impurity concentration different from that of the semiconductor material forming the first semiconductor layer 101. The second impurity layer 120 contains a P-type semiconductor. The surface of each of the first impurity layer 110 and the plurality of second impurity layers 120 constitutes a surface 101 a. Each of the first impurity layer 110 and the plurality of second impurity layers 120 is configured as a layer from the surface 101 a to a predetermined depth.

The insulating layer 130 is made of an insulating material. For example, the insulating material forming the insulating layer 130 is silicon dioxide (SiO 2). The insulating layer 130 is stacked on the first semiconductor layer 101. The insulating layer 130 is in contact with the surface 101 a of the first semiconductor layer 101.

The first electrode 140, the second electrode 150, the third electrode 160, and the plurality of gate electrodes 180 are made of a conductive material. For example, the conductive material constituting these electrodes is a metal such as copper (Cu), aluminum (Al), and gold (Au). The conductive material forming these electrodes may include a semiconductor such as polysilicon having a high impurity concentration. The first electrode 140, the second electrode 150, the third electrode 160, and the plurality of gate electrodes 180 may be made of different conductive materials.

The first electrode 140, the second electrode 150, and the plurality of gate electrodes 180 are disposed on the surface of the insulating layer 130. These electrodes are arranged at mutually different positions. The first electrode 140 is disposed at a position corresponding to the first impurity layer 110. The plurality of gate electrodes 180 are disposed at positions corresponding to the second impurity layer 120. The second electrode 150 is disposed at a position corresponding to the connection layer 170. In the example shown in FIG. 1, the impurity layer is not disposed at a position corresponding to the second electrode 150.

In the insulating layer 130, an opening is formed at a position corresponding to each of the first impurity layer 110 and the plurality of second impurity layers 120. The first electrode 140 is connected to the first impurity layer 110 through an opening formed in the insulating layer 130. The second electrode 150 is connected to the connection layer 170 through an opening formed in the insulating layer 130. The gate electrode 180 is connected to the second impurity layer 120 through an opening formed in the insulating layer 130. That is, the first electrode 140, the second electrode 150, and the plurality of gate electrodes 180 penetrate the insulating layer 130. The gate electrode 180 and the second impurity layer 120 constitute an FET.

The third electrode 160 is stacked on the first semiconductor layer 101. The third electrode 160 is in contact with the surface 101 b of the first semiconductor layer 101. The third electrode 160 has a surface 160a and a surface 160b. The face 160a and the face 160b face in opposite directions to each other. The surface 160a is in contact with the surface 101b. The third electrode 160 covers at least a part of the surface 101 b. In the example shown in FIG. 1, the third electrode 160 covers the entire surface 101 b. An opening may be formed in part of the third electrode 160.

The connection layer 170 is made of a conductive material similar to the conductive material constituting the first electrode 140, the second electrode 150, and the plurality of gate electrodes 180. The connection layer 170 penetrates the first semiconductor layer 101. The connection layer 170 is connected to the second electrode 150 at the surface 101 a and connected to the third electrode 160 at the surface 101 b. The connection layer 170 is configured by a cylinder (wall) which passes through the first electrode 140 and surrounds an imaginary straight line L1 perpendicular to the surface 101a.

The third electrode 160 is larger than the second electrode 150 when the semiconductor device 10 is viewed in the direction perpendicular to the surface 101 a. The third electrode 160 is larger than the connection layer 170 when the semiconductor device 10 is viewed in the direction perpendicular to the surface 101 a.

2 and 3 show the configuration around the connection layer 170. FIG. FIG. 2 shows a first example and FIG. 3 shows a second example.

The configuration shown in FIG. 2 will be described. In the manufacturing process of the semiconductor device 10, the third electrode 160 is formed on the surface 101 b of the first semiconductor layer 101. After the third electrode 160 is formed, the first semiconductor layer 101 is scraped from the surface 101 a side of the first semiconductor layer 101. Thus, a hole 190 penetrating the first semiconductor layer 101 is formed. The hole 190 opens in the surface 101 a and the surface 101 b. After the holes 190 are formed, the connection layer 170 is formed by filling the holes 190 with a conductive material. Thus, the connection layer 170 is disposed in the hole 190. After the connection layer 170 is formed, the insulating layer 130 is formed on the surface 101 a of the first semiconductor layer 101. After the insulating layer 130 is formed, a second electrode 150 is formed to penetrate the insulating layer 130.

The position of the boundary between the connection layer 170 and the second electrode 150 coincides with the surface 101 a. The position of the boundary between the connection layer 170 and the third electrode 160 coincides with the surface 101 b. The connection layer 170 and the second electrode 150 are defined on the basis of the position of the surface 101a. A portion above the surface 101 a is a second electrode 150. The portion below the surface 101 a is the connection layer 170. The distance between the connection layer 170 and the surface 101a is smaller than the distance d1 between the third electrode 160 and the surface 101a. In FIG. 2, the distance between the connection layer 170 and the surface 101 a is zero. An impurity layer may be disposed between the connection layer 170 and the third electrode 160. In that case, the connection layer 170 is electrically connected to the third electrode 160 through the impurity layer.

The configuration shown in FIG. 3 will be described. In the manufacturing process of the semiconductor device 10, an impurity is implanted from the surface 101a of the first semiconductor layer 101, and the impurity is diffused to form an impurity layer 200. After the impurity layer 200 is formed, the first semiconductor layer 101 is removed from the side of the surface 101 b of the first semiconductor layer 101. Thereby, the hole 191 connected to the impurity layer 200 is formed. The hole 191 opens only to the surface 101 b. After the hole 191 is formed, the connection layer 170 and the third electrode 160 are formed by filling the hole 191 with a conductive material and covering the surface 101b with a conductive material. Thereby, the connection layer 170 is disposed in the hole 191. After the connection layer 170 and the third electrode 160 are formed, the insulating layer 130 is formed on the surface 101 a of the first semiconductor layer 101. After the insulating layer 130 is formed, a second electrode 150 is formed to penetrate the insulating layer 130.

The position of the boundary between the connection layer 170 and the third electrode 160 coincides with the surface 101 b. The connection layer 170 and the third electrode 160 are integrated. The connection layer 170 and the third electrode 160 are defined based on the position of the surface 101 b. The portion above the surface 101 b is the connection layer 170. A portion below the surface 101 b is a third electrode 160. The distance d2 between the connection layer 170 and the surface 101a is smaller than the distance d1 between the third electrode 160 and the surface 101a. The connection layer 170 is electrically connected to the second electrode 150 through the impurity layer 200.

FIG. 4 is a plan view of the semiconductor device 10. In FIG. 4, each element when the semiconductor device 10 is viewed in the direction perpendicular to the surface 101 a of the first semiconductor layer 101 is shown. That is, in FIG. 4, each element when the semiconductor device 10 is viewed from the front of the semiconductor substrate 100 is shown. In FIG. 4, the insulating layer 130 is omitted. In FIG. 4, reference numerals of one gate electrode 180 are shown as a representative of the plurality of gate electrodes 180.

The outer shape of the semiconductor device 10 is rectangular. In the example shown in FIG. 4, the outline of the semiconductor device 10 is a square. The outer shape of the semiconductor device 10 is not limited to a rectangle. The first electrode 140 is disposed at the center of the surface 101a. The first electrode 140 is a circular electrode. The outer shape of the first electrode 140 may be rectangular or the like. A virtual straight line L1 shown in FIG. 1 passes through the center of the first electrode 140.

The second electrode 150 overlaps with the connection layer 170. For convenience of illustration, the second electrode 150 is omitted in FIG. The second electrode 150 and the plurality of gate electrodes 180 are ring-shaped electrodes. The second electrode 150 and the plurality of gate electrodes 180 are arranged concentrically. The second electrode 150 and the plurality of gate electrodes 180 are arranged to surround the first electrode 140. The second electrode 150 is disposed at the outermost side. The plurality of gate electrodes 180 are disposed between the first electrode 140 and the second electrode 150. A cross section through line L2 shown in FIG. 4 is shown in FIG.

The connection layer 170 is disposed so as to overlap with the outermost second electrode 150. When the semiconductor device 10 is viewed in the direction perpendicular to the surface 101a, the connection layer 170 is ring-shaped. The connection layer 170 is configured by a cylinder surrounding the virtual straight line L1. In FIG. 4, the imaginary straight line L1 is indicated by a point. For example, the central axis of the connection layer 170 coincides with the imaginary straight line L1.

In virtual plane S1 parallel to surface 101a and passing through semiconductor substrate 100, connection layer 170 is disposed on the circumference of virtual circle C1 centered on virtual straight line L1 passing through first electrode 140 and perpendicular to surface 101a. It is done. In FIG. 1, the virtual plane S1 is shown by a straight line. The virtual plane S1 is between the surface 101a and the surface 101b. In FIG. 1, a virtual circle C1 is indicated by a point. The shape of the cross section of the cylinder constituting the connection layer 170 shown in FIG. 4 is a circle. In virtual plane S1, connection layer 170 may be arranged on the circumference of a virtual polygon centered on virtual straight line L1. A virtual polygon has three or more vertices and three or more sides. Therefore, the shape of the cross section of the cylinder constituting the connection layer 170 may be polygonal.

A voltage is applied to the first electrode 140, the second electrode 150, and the plurality of gate electrodes 180. The voltage applied to the first electrode 140 is higher than the voltage applied to the second electrode 150. The first electrode 140 functions as an anode electrode, and the second electrode 150 functions as a cathode electrode. The voltage applied to the first electrode 140 is higher than any voltage applied to the plurality of gate electrodes 180. A negative voltage is applied to the second electrode 150 and the plurality of gate electrodes 180.

The voltage applied to the plurality of gate electrodes 180 is higher than the voltage applied to the second electrode 150. The voltage applied to the inner gate electrode 180 is higher than the voltage applied to the outer gate electrode 180. A voltage is applied to the first electrode 140, the second electrode 150, and the plurality of gate electrodes 180 such that the potential inside the semiconductor substrate 100 increases from the outer periphery of the semiconductor substrate 100 toward the center.

The voltage applied to the second electrode 150 is applied to the third electrode 160 through the connection layer 170. Thus, there is no need to apply a voltage directly to the third electrode 160. That is, a structure such as a wiring for directly applying a voltage to the third electrode 160 from the outside of the semiconductor device 10 is not necessary. A voltage lower than that applied to the first electrode 140 is applied to the third electrode 160. A voltage is applied to the third electrode 160 such that the internal potential of the semiconductor substrate 100 increases from the surface 101 b toward the surface 101 a.

The voltage as described above is applied to the semiconductor device 10. The potential acting on the electrons decreases from the outer periphery to the center of the semiconductor substrate 100 and decreases from the surface 101 b to the surface 101 a. That is, a potential gradient is generated in the semiconductor substrate 100. When X-rays enter the semiconductor device 10, electrons are generated in the semiconductor substrate 100. The electrons collect at the first electrode 140 according to the potential gradient. A signal based on the electrons is output from the semiconductor device 10.

The first semiconductor layer 101 and the first impurity layer 110 may be formed of a P-type semiconductor, and the plurality of second impurity layers 120 may be formed of an N-type semiconductor. The voltage applied to each electrode in that case will be described. The voltage applied to the first electrode 140 is lower than the voltage applied to the second electrode 150. The first electrode 140 functions as a cathode electrode, and the second electrode 150 functions as an anode electrode. The voltage applied to the first electrode 140 is lower than any voltage applied to the plurality of gate electrodes 180. A positive voltage is applied to the second electrode 150 and the plurality of gate electrodes 180.

The voltage applied to the plurality of gate electrodes 180 is lower than the voltage applied to the second electrode 150. The voltage applied to the inner gate electrode 180 is lower than the voltage applied to the outer gate electrode 180. A voltage is applied to the first electrode 140, the second electrode 150, and the plurality of gate electrodes 180 such that the potential inside the semiconductor substrate 100 decreases from the outer periphery of the semiconductor substrate 100 toward the center.

The voltage applied to the second electrode 150 is applied to the third electrode 160 through the connection layer 170. A voltage higher than that applied to the first electrode 140 is applied to the third electrode 160. A voltage is applied to the third electrode 160 such that the potential inside the semiconductor substrate 100 decreases from the surface 101 b toward the surface 101 a.

The first impurity layer 110, the plurality of second impurity layers 120, and the plurality of gate electrodes 180 are not essential in the semiconductor device of each aspect of the present invention. By arranging the plurality of second impurity layers 120 and controlling the voltage applied to the plurality of gate electrodes 180, a favorable potential gradient can be formed. Similar to the detector 1011 shown in FIG. 14, the plurality of second impurity layers 120 may be disposed, and the plurality of gate electrodes 180 may not be disposed. Similar to the detector 1012 shown in FIG. 15, the plurality of gate electrodes 180 may be disposed, and the plurality of second impurity layers 120 may not be disposed.

As described above, the connection layer 170 electrically connected to the second electrode 150 and the third electrode 160 is disposed. Therefore, a structure such as a wire for directly applying a voltage to the third electrode 160 from the outside of the semiconductor device 10 is not necessary. As a result, the size of the semiconductor device 10 can be reduced, and an improvement in yield can be realized.

The connection layer 170 is configured by a cylinder surrounding the virtual straight line L1. Thereby, the first semiconductor layer 101 is separated into portions inside and outside the connection layer 170. The light incident on the semiconductor substrate 100 from the side surface of the semiconductor substrate 100 is unnecessary. The light is less likely to move toward the center of the semiconductor substrate 100 due to the potential gradient formed by the voltage applied to the connection layer 170. Therefore, it is difficult to detect unnecessary charge based on the light.

First Modification of First Embodiment
FIG. 5 is a plan view of a semiconductor device 11 according to a first modification of the first embodiment of the present invention. In FIG. 5, each element when the semiconductor device 11 is seen in the direction perpendicular to the surface 101a of the first semiconductor layer 101 is shown. That is, in FIG. 5, each element when the semiconductor device 11 is viewed from the front of the semiconductor substrate 100 is shown.

The configuration shown in FIG. 5 will be described about differences from the configuration shown in FIG. For convenience of illustration, in FIG. 5, the portion of the second electrode 150 overlapping the connection layer 170 is omitted. A plurality of connection layers 170 are disposed so as to pass through the first electrode 140 and surround an imaginary straight line L1 perpendicular to the surface 101a. In FIG. 5, reference numerals of one connection layer 170 are shown as a representative of the plurality of connection layers 170. Each connection layer 170 constituting the plurality of connection layers 170 is formed of a pillar (bar). For example, the plurality of connection layers 170 are arranged at equal intervals. Each connection layer 170 constituting the plurality of connection layers 170 is electrically connected to the second electrode 150 and the third electrode 160. In virtual plane S1 (FIG. 1), a plurality of connection layers 170 are arranged on the circumference of virtual circle C1. At least one connection layer 170 need only be disposed.

Except for the points described above, the configuration shown in FIG. 5 is similar to the configuration shown in FIG.

In the semiconductor device 11, the connection layer 170 is formed of a plurality of pillars separated from one another. Therefore, compared to the semiconductor device 10 shown in FIG. 1, the material constituting the connection layer 170 is reduced. As a result, the manufacturing cost of the semiconductor device 11 is lower than that of the semiconductor device 10.

Second Modification of First Embodiment
FIG. 6 is a plan view of a semiconductor device 12 according to a second modification of the first embodiment of the present invention. In FIG. 6, each element when the semiconductor device 12 is seen in the direction perpendicular to the surface 101a of the first semiconductor layer 101 is shown. That is, in FIG. 6, each element when the semiconductor device 12 is viewed from the front of the semiconductor substrate 100 is shown.

The configuration shown in FIG. 6 will be described about differences from the configuration shown in FIG. The cross section of the connection layer 170 is a circle. The cross section of the connection layer 170 may be polygonal.

The configuration shown in FIG. 6 is the same as the configuration shown in FIG.

In the semiconductor device 12, the connection layer 170 is configured of a plurality of pillars separated from one another. Therefore, similar to the semiconductor device 11 shown in FIG. 5, the manufacturing cost of the semiconductor device 12 is lower than that of the semiconductor device 10 shown in FIG.

Second Embodiment
FIG. 7 shows the configuration of the semiconductor device 13 according to the second embodiment of the present invention. In FIG. 7, a cross section of the semiconductor device 13 is shown. The configuration shown in FIG. 7 will be described about differences from the configuration shown in FIG.

As shown in FIG. 7, the semiconductor device 13 includes a semiconductor substrate 103, an insulating layer 130, a first electrode 140, a second electrode 150, a connection layer 170, and a plurality of gate electrodes 180. In FIG. 7, reference numerals of two gate electrodes 180 are shown as a representative of the plurality of gate electrodes 180. The semiconductor substrate 103 has a surface 101a (first main surface) and a surface 102b (second main surface) facing in opposite directions. The semiconductor substrate 103 and the insulating layer 130 are stacked in the direction Dr1 perpendicular to the surface 101a.

The semiconductor substrate 103 includes a first semiconductor layer 101, a second semiconductor layer 102, a first impurity layer 110, and a plurality of second impurity layers 120. In FIG. 7, the symbol of one second impurity layer 120 is shown as a representative of the plurality of second impurity layers 120. For example, the semiconductor material forming the semiconductor substrate 103 is silicon (Si).

The first semiconductor layer 101 and the second semiconductor layer 102 are stacked in a direction Dr1 perpendicular to the surface 101a. The first semiconductor layer 101 is configured in the same manner as the first semiconductor layer 101 shown in FIG. The second semiconductor layer 102 contains a P-type semiconductor. The second semiconductor layer 102 has a surface 102 a and a surface 102 b. The surface 102a and the surface 102b face in the opposite direction to each other. The surface 102 a is in contact with the surface 101 b of the first semiconductor layer 101. The surface 102 b constitutes the main surface of the semiconductor substrate 103. The second semiconductor layer 102 is disposed in the semiconductor substrate 103 so as to include the surface 102 b.

The connection layer 170 is connected to the second semiconductor layer 102 at the surface 101 b. The voltage applied to the second electrode 150 is applied to the second semiconductor layer 102 through the connection layer 170. A voltage higher than the voltage applied to the first electrode 140 is applied to the second semiconductor layer 102. A voltage is applied to the second semiconductor layer 102 such that the internal potential of the first semiconductor layer 101 decreases from the surface 101 b toward the surface 101 a.

Except for the points described above, the configuration shown in FIG. 7 is the same as the configuration shown in FIG.

The structure of the connection layer 170 may be any of the structures shown in FIG. 4 to FIG. The first semiconductor layer 101 and the first impurity layer 110 may be formed of a P-type semiconductor, and the second semiconductor layer 102 and the plurality of second impurity layers 120 may be formed of an N-type semiconductor. Similar to the detector 1011 shown in FIG. 14, the plurality of second impurity layers 120 may be disposed, and the plurality of gate electrodes 180 may not be disposed. Similar to the detector 1012 shown in FIG. 15, the plurality of gate electrodes 180 may be disposed, and the plurality of second impurity layers 120 may not be disposed.

As described above, the connection layer 170 electrically connected to the second electrode 150 and the second semiconductor layer 102 is disposed. Therefore, a structure such as a wiring for directly applying a voltage to the second semiconductor layer 102 from the outside of the semiconductor device 13 is not necessary. As a result, the size of the semiconductor device 13 can be reduced, and an improvement in yield can be realized.

Third Embodiment
FIG. 8 is a plan view of a semiconductor device 14 according to a third embodiment of the present invention. In FIG. 8, each element when the semiconductor device 14 is viewed in the direction perpendicular to the surface 101a of the first semiconductor layer 101 is shown. That is, in FIG. 8, each element when the semiconductor device 14 is viewed from the front of the semiconductor substrate 100 is shown. The cross-sectional structure of the semiconductor device 14 is the same as that shown in FIG. In FIG. 8, the insulating layer 130 is omitted. The gate electrode 180 is not disposed.

A plurality of first electrodes 140 are arranged. In FIG. 8, a symbol of one first electrode 140 is shown as a representative of the plurality of first electrodes 140.

For convenience of illustration, in FIG. 8, the portion of the second electrode 150 overlapping with the connection layer 170 is omitted. In the surface 101 a, the second electrodes 150 are disposed so as to surround each of the first electrodes 140 constituting the plurality of first electrodes 140. The second electrode 150 is an assembly of a plurality of linear structures. The second electrode 150 constitutes a hexagon centered on the first electrode 140.

In an imaginary plane S1 (FIG. 1) parallel to the surface 101a and passing through the semiconductor substrate 100, the connection layer 170 passes through the respective first electrodes 140 constituting the plurality of first electrodes 140 and is perpendicular to the surface 101a. It is arrange | positioned so that the virtual straight line L1 may be enclosed. Two or more connection layers 170 are arranged to surround each virtual straight line L1. In FIG. 8, reference numerals of one connection layer 170 are shown as a representative of the plurality of connection layers 170. Each connection layer 170 constituting the plurality of connection layers 170 is formed of a pillar. Each connection layer 170 constituting the plurality of connection layers 170 is electrically connected to the second electrode 150 and the third electrode 160.

A plurality of electrode units U1 are arranged. In FIG. 8, reference numerals of one electrode unit U1 are shown as a representative of the plurality of electrode units U1. One electrode unit U1 includes one first electrode 140, a second electrode 150 forming a hexagon, and six connection layers 170. Six connection layers 170 are disposed at the apex of the hexagon formed by the second electrode 150. Two adjacent electrode units U1 share a second electrode 150 that constitutes one side of a hexagon. Two electrode units U1 adjacent to each other share two connection layers 170 arranged on one side of the hexagon.

The plurality of first electrodes 140 may be connected to each other by a common wiring. Thereby, the signals output from the plurality of first electrodes 140 are added. As a result, the sensitivity is improved. The plurality of first electrodes 140 may be respectively connected to the plurality of amplifiers, and the outputs of the plurality of amplifiers may be connected to each other by a common wiring. The plurality of first electrodes 140 may be connected to the plurality of analog-to-digital converters (AD converters), respectively, and the outputs of the plurality of AD converters may be connected to each other by common wiring.

The connection layer 170 may be configured by a cylinder surrounding the virtual straight line L1. The cross section of the connection layer 170 may be hexagonal.

As described above, a plurality of first electrodes 140 are disposed, and a second electrode 150 and a connection layer 170 are disposed around each first electrode 140. Therefore, the distance between the first electrode 140 and the second electrode 150 is short and the distance between the first electrode 140 and the connection layer 170 is short as compared with the semiconductor device 10 shown in FIG. That is, compared to the semiconductor device 10, the moving distance of electrons is shortened. Therefore, there is a high possibility that the electrons are detected by the first electrode 140 before the electrons generated by the fluorescent X-rays recombine with the holes. The chip size can be increased by arranging a plurality of electrode units U1.

Since there is a high possibility that the electrons are detected by the first electrode 140 before the electrons generated by the fluorescent X-rays recombine with the holes, the gate electrode 180 and the second impurity for forming a good potential gradient Layer 120 is not required. Even when the chip size is increased, the manufacturing cost of the semiconductor device 14 is reduced.

First Modification of Third Embodiment
FIG. 9 is a plan view of a semiconductor device 15 of a first modification of the third embodiment of the present invention. FIG. 9 shows each element when the semiconductor device 15 is viewed in the direction perpendicular to the surface 101 a of the first semiconductor layer 101. That is, in FIG. 9, each element when the semiconductor device 15 is viewed from the front of the semiconductor substrate 100 is shown. The sectional structure of the semiconductor device 15 is the same as that shown in FIG. The configuration shown in FIG. 9 will be described about differences from the configuration shown in FIG.

The second electrode 150 constitutes a quadrangle (square) centered on the first electrode 140. A plurality of electrode units U2 are arranged. In FIG. 9, the reference numeral of one electrode unit U2 is shown as a representative of the plurality of electrode units U2. One electrode unit U2 includes one first electrode 140, a second electrode 150 forming a square, and four connection layers 170. The four connection layers 170 are disposed at the vertexes of the square formed by the second electrode 150. Two electrode units U2 adjacent to each other share a second electrode 150 that constitutes one side of a square. Two electrode units U1 adjacent to each other share two connection layers 170 disposed on one side of a square.

The configuration shown in FIG. 9 is the same as the configuration shown in FIG. 8 except for the points described above.

As described above, a plurality of first electrodes 140 are disposed, and a second electrode 150 and a connection layer 170 are disposed around each first electrode 140. Therefore, as in the case of the semiconductor device 14 shown in FIG. 8, the chip size can be increased.

Second Modification of Third Embodiment
FIG. 10 is a plan view of a semiconductor device 16 according to a second modification of the third embodiment of the present invention. In FIG. 10, each element when the semiconductor device 16 is viewed in the direction perpendicular to the surface 101 a of the first semiconductor layer 101 is shown. That is, in FIG. 10, each element when the semiconductor device 16 is viewed from the front of the semiconductor substrate 100 is shown. The cross-sectional structure of the semiconductor device 16 is the same as that shown in FIG. Regarding the configuration shown in FIG. 10, points different from the configuration shown in FIG. 8 will be described.

A plurality of connection layers 170 are arranged. The number of connection layers 170 is smaller than the number of first electrodes 140. In FIG. 10, four connection layers 170 and eight first electrodes 140 are disposed. The position where the connection layer 170 is disposed is not limited to the position shown in FIG. Further, the number of connection layers 170 is not limited to four.

As described above, a plurality of first electrodes 140 are disposed, and a second electrode 150 and a connection layer 170 are disposed around each first electrode 140. Therefore, as in the case of the semiconductor device 14 shown in FIG. 8, the chip size can be increased. In addition, the number of connection layers 170 is smaller than the number of first electrodes 140. Therefore, compared to the semiconductor device 14 shown in FIG. 8, the material constituting the connection layer 170 is reduced. As a result, the manufacturing cost of the semiconductor device 16 is lower than that of the semiconductor device 14.

(Third Modification of Third Embodiment)
FIG. 11 is a plan view of a semiconductor device 17 according to a third modification of the third embodiment of the present invention. In FIG. 11, each element when the semiconductor device 17 is viewed in the direction perpendicular to the surface 101 a of the first semiconductor layer 101 is shown. That is, in FIG. 11, each element when the semiconductor device 17 is viewed from the front of the semiconductor substrate 100 is shown. The cross-sectional structure of the semiconductor device 17 is the same as that shown in FIG. The configuration shown in FIG. 11 will be described about differences from the configuration shown in FIG.

The second electrode 150 constitutes a quadrangle (rectangle). A linear first electrode 140 is disposed at the center of the second electrode 150 constituting a square. A laterally elongated first electrode 140 is disposed. The left and right ends of the first electrode 140 are in the vicinity of the second electrode 150. A plurality of electrode units U3 are arranged. In FIG. 11, the reference numeral of one electrode unit U3 is shown as a representative of the plurality of electrode units U3. One electrode unit U3 includes one first electrode 140, a second electrode 150 forming a square, and six connection layers 170. The six connection layers 170 are disposed on the side of the square formed by the second electrode 150. Two electrode units U3 adjacent to each other share a second electrode 150 which constitutes one side of a square. Two electrode units U3 adjacent to each other share one or two connection layers 170 disposed on one side of the square.

The configuration shown in FIG. 11 is the same as the configuration shown in FIG. 8 except for the points described above.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments and their modifications. Additions, omissions, substitutions, and other modifications of the configuration are possible without departing from the spirit of the present invention. Also, the present invention is not limited by the above description, and is limited only by the scope of the attached claims.

According to each embodiment of the present invention, the semiconductor device can be reduced in size, and an improvement in yield can be realized.

10, 11, 12, 13, 14, 15, 16, 17

semiconductor devices

100, 103, 1100, 1103

semiconductor substrates

101, 1101, 1104 first semiconductor layers 102, 1102 second semiconductor layers 110, 1110

first Impurity layer

120, 1120

Second impurity layer

130, 1130 Insulating layer 140 First electrode 150 Second electrode 160 Third electrode 170

Connection layer

180, 1180, 1190

Gate electrode

190, 191 Hole 200

Impurity layer

1010, 1011 , 1012 Detector 1140 Anode electrode 1150 Cathode electrode

Claims

A semiconductor substrate having a first main surface and a second main surface facing in opposite directions;
A first electrode and a second electrode disposed on the first major surface;
A conductive layer disposed on the second main surface or disposed in the semiconductor substrate to include the second main surface;
It is disposed in a hole opened in at least one of the first main surface and the second main surface in the semiconductor substrate, is electrically connected to the second electrode and the conductive layer, and has conductivity. Connection layer,
Semiconductor device having
The semiconductor device according to claim 1, wherein the connection layer is connected to the second electrode on the first main surface.
The semiconductor device according to claim 1, wherein the connection layer is configured by a cylinder that passes through the first electrode and surrounds a virtual straight line perpendicular to the first main surface.
The semiconductor device according to claim 1, further comprising a plurality of the connection layers disposed so as to pass through the first electrode and surround a virtual straight line perpendicular to the first main surface.
In a virtual plane parallel to the first main surface and passing through the semiconductor substrate, the connection layer is a virtual circle centered on a virtual straight line passing through the first electrode and perpendicular to the first main surface. The semiconductor device according to claim 1, wherein the semiconductor device is disposed on a circumference of a virtual polygon.
Having a plurality of said first electrodes,
2. The semiconductor device according to claim 1, wherein the second electrode is disposed on the first main surface so as to surround each of the first electrodes constituting the plurality of first electrodes.
In a virtual plane parallel to the first main surface and passing through the semiconductor substrate, the connection layer passes through the respective first electrodes constituting the plurality of first electrodes, and the first main surface The semiconductor device according to claim 6, wherein the semiconductor device is disposed so as to surround a virtual straight line perpendicular to the line.
Having a plurality of said connection layers,
The semiconductor device according to claim 6, wherein the number of connection layers is smaller than the number of first electrodes.