WO2006038363A1 - Dispositif de communication sans fil - Google Patents

Dispositif de communication sans fil Download PDF

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Publication number
WO2006038363A1
WO2006038363A1 PCT/JP2005/013395 JP2005013395W WO2006038363A1 WO 2006038363 A1 WO2006038363 A1 WO 2006038363A1 JP 2005013395 W JP2005013395 W JP 2005013395W WO 2006038363 A1 WO2006038363 A1 WO 2006038363A1
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WO
WIPO (PCT)
Prior art keywords
circuit
signal
control signal
frequency
antenna
Prior art date
Application number
PCT/JP2005/013395
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English (en)
Japanese (ja)
Inventor
Kiyofumi Takai
Original Assignee
Murata Manufacturing Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co., Ltd. filed Critical Murata Manufacturing Co., Ltd.
Publication of WO2006038363A1 publication Critical patent/WO2006038363A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B15/00—Suppression or limitation of noise or interference
    • H04B15/005—Reducing noise, e.g. humm, from the supply

Definitions

  • the present invention relates to a wireless communication device including a circuit that generates a clock signal.
  • FIG. 7 schematically shows an example of a main configuration of a wireless communication device.
  • the wireless communication device 1 includes an antenna 2, a radio communication high frequency circuit (RF circuit) 3, a baseband processing unit (BB) 4, and a clock generation circuit 5.
  • the wireless communication device 1 is capable of transmitting and receiving radio waves, and the high-frequency circuit 3 includes a receiving circuit 6, a transmitting circuit 7, and transmission / reception switching means 8.
  • the transmission / reception switching means 8 has a configuration in which one of the reception circuit 6 and the transmission circuit 7 is switched and connected to the antenna 2, and is configured by, for example, a SPDT (Single-Pole-Double-Throw) switch or the like. .
  • SPDT Single-Pole-Double-Throw
  • the transmission circuit 7 has a circuit configuration for generating a signal for radio transmission suitable for up-converting the signal supplied from the baseband processing unit 4 and supplying the signal to the antenna 2.
  • the signal for wireless transmission generated by the transmission circuit 7 is supplied to the antenna 2 through the transmission / reception switching means 8 and is wirelessly transmitted from the antenna 2.
  • the receiving circuit 6 down-converts the received signal received by the antenna 2 via the transmission / reception switching means 8 from the antenna 2 to a predetermined frequency and converts the down-converted signal into a baseband processing unit. It has a configuration that outputs to 4.
  • the baseband processing unit 4 is configured by, for example, a baseband IC (BB-IC).
  • BB-IC baseband IC
  • the baseband processing unit 4 has a circuit configuration for performing a predetermined signal processing operation, and also includes a control unit 10, and the control unit 10 controls the switching operation of the transmission / reception switching unit 8 of the high-frequency circuit 3. Then, control of the circuit operation of the reception circuit 6 and control of the circuit operation of the transmission circuit 7 are performed.
  • the clock generation circuit 5 generates a clock signal having a predetermined frequency.
  • the generated clock signal is used for the circuit operations of the baseband processing unit 4 and the high-frequency circuit 3.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2004-104281
  • Patent Document 2 Japanese Patent Laid-Open No. 2001-24539
  • Patent Document 3 Japanese Patent Laid-Open No. 2003-219290
  • the clock signal generated by the clock generation circuit 5 includes a harmonic wave as a noise component.
  • a clock signal is supplied to the control unit 10, and a control signal output from the control unit 10 toward the high-frequency circuit 3 (the reception circuit 6, the transmission circuit 7, or the transmission / reception switching unit 8) due to the clock signal.
  • a double wave of the clock signal is added as a noise component.
  • the harmonic wave of the clock signal is transmitted as a noise component.
  • the received signal is a much weaker signal than the signal for wireless transmission.
  • the double wave (noise component) of the clock signal transmitted from the control signal has such a magnitude that the S / N ratio of the received signal is adversely affected. For this reason, it is a big problem that a noise component due to the double wave of the clock signal is added to the received signal.
  • the predetermined reception frequency band of the antenna 2 is a frequency band including the frequency of the harmonic wave of the clock signal, the frequency of the reception signal and the frequency of the harmonic wave of the clock signal that is a noise component Since they are equal or nearly equal, it is difficult to remove (attenuate) only the double wave of the clock signal, which is a noise component, from the received signal.
  • the reception frequency band of the antenna 2 is a frequency band including the frequency of the harmonics of the clock signal, it is difficult to improve the SN ratio of the reception signal due to the harmonics of the clock signal.
  • the high reception sensitivity could not be obtained. For this reason, the problem that the reliability with respect to the radio
  • a clock signal is supplied from the clock generation circuit 5 to the baseband processing unit 4
  • a filter means for attenuating the harmonics of the clock signal in the clock signal supply path for this purpose see Patent Document 3, for example.
  • the noise component of the control signal due to the harmonic wave of the clock signal is reduced by reducing the harmonic wave (noise component) of the clock signal supplied to the baseband processing unit 4. .
  • the baseband processing unit 4 a circuit operation for dividing the clock signal or multiplying the clock signal is performed inside the baseband processing unit 4. A harmonic of the signal is generated. For this reason, even if the harmonic wave of the clock signal supplied from the clock generation circuit 5 to the baseband processing unit 4 is attenuated, the harmonic wave of the clock signal is generated inside the baseband processing unit 4. For this reason, the harmonics of the clock signal generated inside the baseband processing unit 4 ride on the control signal output from the control unit 10 to the high-frequency circuit 3 as a noise component, and the same problem as described above. It is generated.
  • the present invention has the following configuration as means for solving the above problems. In other words, this invention
  • a high frequency circuit connected to an antenna and performing a predetermined circuit operation for wireless communication using the antenna
  • a clock generation circuit for generating and outputting a clock signal
  • a control unit for controlling the circuit operation of the high-frequency circuit
  • control unit a circuit that uses the clock signal output from the clock generation circuit is formed.
  • Control unit power to control the circuit operation of the high-frequency circuit
  • the control signal supply path through which the control signal output to the high-frequency circuit is energized attenuates the noise component of the control signal caused by the harmonics of the clock signal It is characterized in that a filter means is provided.
  • the filter means for attenuating the noise component of the control signal due to the harmonic of the clock signal is provided in the control signal supply path for supplying the control signal to the control unit high frequency circuit. .
  • the harmonic wave can be attenuated by the filter means. As a result, it is possible to supply a control signal with a few harmonics of the clock signal to the high frequency circuit.
  • a noise component is added from the control signal to, for example, a reception signal or a signal for wireless transmission that energizes the inside of the high frequency circuit. It is possible to suppress the transmission of the harmonic wave of the clock signal. In other words, it is possible to prevent a bad signal-to-noise ratio of a received signal or a signal for wireless transmission due to a double wave of the clock signal, and to improve the wireless communication characteristics of the wireless communication device. Further, since the filter means for attenuating the noise component of the control signal due to the harmonic wave of the clock signal can be constructed with a simple configuration, the configuration of the wireless communication device is provided by including the configuration of the present invention. It is easy to provide a wireless communication device with high reliability for wireless communication while preventing the complication and enlargement of the wireless communication.
  • FIG. 1 is a diagram for explaining one embodiment according to a wireless communication device of the present invention.
  • FIG. 2a is a diagram for explaining a configuration example of filter means constituted by capacitors.
  • FIG. 2b is a diagram for explaining a configuration example of filter means including an inductor.
  • FIG. 3a is a diagram for explaining a configuration example of filter means configured by resistors.
  • FIG. 3b is a diagram for explaining a configuration example of filter means constituted by ferrite elements.
  • FIG. 4a is a diagram for explaining a configuration example of filter means configured by an LC series resonance circuit.
  • FIG. 4b is a diagram for explaining a configuration example of filter means configured by an LC parallel resonant circuit.
  • FIG. 4c is a diagram for explaining a configuration example of filter means constituted by a resonance circuit composed of a line filter.
  • FIG. 4d is a diagram for explaining another configuration example of the filter means configured by a resonance circuit composed of a line filter.
  • FIG. 5a is a diagram for explaining an example in which the filter means is constituted by a low-pass filter.
  • FIG. 5b is a diagram for explaining a configuration example of a low-pass filter.
  • FIG. 5c is a diagram for explaining another configuration example of the low-pass filter.
  • FIG. 6 is a diagram for explaining another embodiment.
  • FIG. 7 is a block configuration diagram for explaining an example of a main circuit configuration of a wireless communication device.
  • FIG. 1 schematically shows the main components of the wireless communication device of this embodiment.
  • the wireless communication device 1 according to this embodiment includes an antenna 2, a high frequency circuit 3, a baseband processing unit 4, and a clock generation circuit 5.
  • the clock generating circuit 5 has a circuit configuration for generating a clock signal having a predetermined frequency.
  • the clock generation circuit 5 is configured by a device such as TCXO (Temperature-Compensated-Crysta ⁇ Oscillator), for example, and is arranged separately from the high-frequency circuit 3 and the baseband processing unit 4 as shown in FIG.
  • TCXO Temporal-Compensated-Crysta ⁇ Oscillator
  • the clock generation circuit 5 may be incorporated in the IC constituting the high-frequency circuit 3.
  • the baseband processing unit 4 is composed of a BB-IC, it may be incorporated in the BB-IC.
  • the control unit 10 of the baseband processing unit 4 controls the circuit operation of the high frequency circuit 3.
  • the control unit 10 has a circuit that generates a control signal for controlling the circuit operation of the high-frequency circuit 3 using the clock signal output from the clock generation circuit 5, and the control generated by this circuit. The signal is output to the high frequency circuit 3.
  • the high frequency circuit 3 includes a receiving circuit 6, a transmitting circuit 7, and transmission / reception switching means 8.
  • the high-frequency circuit 3 may be integrated to form an IC component.
  • the circuit board may be formed by providing circuit patterns and components for high-frequency circuits.
  • a control signal supply path 12 for supplying a control signal from the control unit 10 of the baseband processing unit 4 to the transmission / reception switching unit 8 of the high-frequency circuit 3 is formed.
  • the transmission / reception switching means 8 switches and connects either the reception circuit 6 or the transmission circuit 7 to the antenna 2.
  • a control signal supply path 13 for supplying a control signal from the control unit 10 to the transmission circuit 7 is formed.
  • the transmission circuit 7 upconverts the signal received from the baseband processing unit 4 and generates a signal for wireless transmission.
  • the generated radio transmission signal is supplied from the transmission circuit 7 to the antenna 2 via the transmission / reception switching means 8.
  • the circuit configuration of the transmission circuit 7 is not particularly limited, and an appropriate circuit configuration considering various points is adopted.
  • the receiving circuit 6 has a circuit configuration that down-converts the received signal output from the antenna 2 and added via the transmission / reception switching means 8, and outputs the down-converted signal to the baseband processing unit 4. It is what.
  • the reception circuit 6 includes an LNA (low noise amplifier) 15, a down-conversion unit 16, and an amplification circuit unit 17.
  • LNA low noise amplifier
  • the LNA 15 amplifies a weak received signal applied from the antenna 2 via the transmission / reception switching means 8.
  • the down-conversion unit 16 includes two mixers 20 (20A, 20B) and a local oscillator 21 (VCO (Voltage Controlled Oscillator) etc.) individually connected to each of the mixers 20A, 20B. 21A, 21B).
  • the mixer 20A uses the oscillation signal output from the local oscillator 21A to down-convert the reception signal output from the LNA 15 to a signal in a predetermined intermediate frequency band.
  • the mixer 20B uses the oscillation signal output from the local oscillator 21B to down-convert the intermediate frequency band signal output from the mixer 20A into a predetermined low frequency signal.
  • the amplification circuit unit 17 amplifies the signal output from the down-conversion unit 16 and outputs the amplified signal to the baseband processing unit 4.
  • the LNA 15, the mixer 20 (20 A, 20 B), and the amplification circuit unit 17 constituting the reception circuit 6 are circuit units to be controlled by the control unit 10.
  • a control signal supply path 22 for supplying a control signal from the control unit 10 to the receiving circuit 6 is a main line path 23 common to a plurality of circuit units 15, 17, 20 (20A, 20B) to be controlled by the control unit 10, and
  • a branch path 24 (24a to 24d) for supplying control signals to the respective circuit units 15, 17, 20 (20A, 20B) is formed by branching from the main line 23.
  • the LNA 15, the mixer 20 (20A, 20B), and the amplifier circuit unit 17 are configured so that the control signal (drive control signal) instructing the drive is transmitted from the control unit 10 to the main signal path 23 and the branch path of the control signal supply path 22.
  • the circuit operation as described above is performed when 24 is added in order.
  • the portion of X12 shown in FIG. 1 in the control signal supply path 12 (that is, the vicinity of the transmission / reception switching means 8) and the main path 23 of the control signal supply path 22 in FIG. X23 shown in FIG. 1 (that is, a part near the branch of the control signal supply path 22) and Xa, Xb, Xc, and Xd shown in FIG. 1 in each branch path 24 (24a to 24d) (that is, circuit Filter means as will be described later is provided in at least X12 of the 17 and 20 (in the vicinity of 20A, 20B).
  • the filter means may be provided only at the X12 site, may be provided at the X12 site and the X23 site, or may be provided at the X12 site and the Xa, Xb, Xc, and Xd sites. It may be provided, or it may be provided at all of X12, X23, Xa, Xb, Xc, and Xd.
  • the filter means provided at each of the parts X12, X23, Xa, Xb, Xc, and Xd is constituted by, for example, a filter as shown in FIGS. 2a to 5c described later.
  • the filter is designed to attenuate a harmonic of a predetermined frequency of the control signal power clock signal. That is, the harmonic wave of the clock signal has a frequency that is an integer multiple of the clock signal frequency, and there are many.
  • the filter means provided at the X12 portion is designed to attenuate a harmonic (noise component) having a frequency in a predetermined reception frequency band of the antenna 2.
  • the filter means is generated by the harmonic wave having the frequency of the reception frequency band of the antenna 2 and the mixer 20A.
  • a harmonic having a frequency in the oscillation frequency band of the local oscillator 21 (21A, 21B) can be attenuated so that a harmonic having a frequency in the signal frequency band (that is, the intermediate frequency band) can be attenuated. Also designed to be damped.
  • the filter means 25 in FIG. 2a is constituted by a capacitor having the self-resonant frequency of the harmonic wave to be attenuated of the clock signal. One end of the capacitor is connected to the control signal supply path 1 2 (23, 24), and the other end of the capacitor is grounded.
  • the filter means 25 in FIG. 2b is composed of an inductor having the self-resonant frequency as the frequency of the harmonic wave to be attenuated of the clock signal. This inductor is interposed in series with the control signal supply path 12 (23, 24).
  • the filter means 25 of Fig. 3a is constituted by a resistor having a high impedance with respect to the frequency of the harmonic wave to be attenuated of the clock signal.
  • the resistor is interposed in series with the control signal supply path 12 (23, 24).
  • the filter means 25 in FIG. 3b is composed of a ferrite element having a high impedance with respect to the frequency of the harmonic wave to be attenuated of the clock signal.
  • the ferrite element is interposed in series with the control signal supply path 12 (23, 24).
  • the filter means 25 in Fig. 4a is configured by an LC series resonance circuit having the frequency of the harmonic wave to be attenuated of the clock signal as the resonance frequency.
  • One end of the LC series resonance circuit is connected to the control signal supply path 12 (23, 24), and the other end is grounded.
  • the filter means 25 in FIG. 4b is composed of an LC parallel resonance circuit having the frequency of the harmonic wave to be attenuated of the clock signal as the resonance frequency.
  • the LC parallel resonant circuit is inserted in series with the control signal supply path 12 (23, 24).
  • the filter means 25 of FIG. is constituted by a resonance circuit having a line (for example, microstrip line) force having a self-resonant frequency of the harmonic wave to be attenuated of the clock signal, but the line constituting the filter means 25 of FIG. Are connected in series to the control signal supply path 12 (23, 24).
  • the filter means 25 of Fig. 5a is constituted by a low-pass filter.
  • This low-pass filter is connected in series with the control signal supply path 12 (23, 24), and has a configuration that attenuates the harmonic wave to be attenuated of the clock signal and transmits the control signal.
  • the low-pass filter includes a resistor and a capacitor as shown in FIG. 5b, a inductor and a capacitor as shown in FIG. 5c, and the capacitor shown in FIG. 5b.
  • There are a line that functions as a capacitor instead of the capacitor for example, a microstrip line
  • a line that functions as an inductor instead of the inductor in FIG. 5c for example, a microstrip line.
  • the filter means provided in at least the control signal supply path 12 of the control signal supply paths 12, 23, 24 is configured by one of a number of filter configurations as described above. Or a plurality of the same filter configurations, or a combination of a plurality of different filter configurations.
  • the configuration of the filter means provided in the control signal supply paths 12, 23, 24 may be different from each other, or all the filter means may have the same configuration.
  • the filter means of the control signal supply path 12 and the filter means of the control signal supply path (main line) 23 are the same, and the filter means of the control signal supply path (branch path) 24 is the control signal supply path.
  • the configuration of each filter means provided in the control signal supply paths 12, 23, and 24, which may be different from the configuration of the filter means 12 and 23, has an appropriate configuration.
  • the filter means for attenuating the noise component of the control signal due to the harmonic of the clock signal supplies the control signal supply path for supplying the control signal from the control unit 10 to the high-frequency circuit 3. 12 (23, 24).
  • the clock signal that is riding on the control signal due to the double wave of the clock signal that has been on the control signal inside the control unit 10 or crosstalk between the control signal supply path and the clock signal supply path. ⁇ times The wave can be attenuated by the filter means.
  • a control signal with a few harmonics of the clock signal can be supplied to the high-frequency circuit 3.
  • a reception signal output from an antenna is a weak signal, and this reception signal tends to have a poor SN ratio, and it is difficult to improve the reception sensitivity of a wireless communication device.
  • a filter means for attenuating the noise component of the control signal caused by the harmonic of the clock signal is provided in the control signal supply path 22 from the control unit 10 to the receiving circuit 6. It has a configuration. As a result, the signal-to-noise ratio of the received signal due to the double wave of the clock signal in the control signal can be prevented. For this reason, the deterioration of the wireless communication performance of the wireless communication device can be effectively suppressed.
  • the preset reception frequency band of antenna 2 is a frequency band including the frequency of the harmonic of the clock signal, the frequency of the reception signal and the harmonic of the clock signal The frequency is equal or nearly equal. For this reason, it is difficult to attenuate only the double wave of the clock signal, which is a noise component, from the received signal. Therefore, as in this embodiment, the configuration in which the harmonic of the clock signal of the control signal is attenuated and the harmonic of the clock signal transmitted from the control signal to the received signal is reduced is the SN of the received signal. It is effective for improving the ratio.
  • the control signal supply path 12 for supplying the control signal from the control unit 10 to the transmission / reception switching means 8 is provided with the filter means, the wireless communication sensitivity of the wireless communication device is provided. Can be improved effectively. That is, the received signal passing through the transmission / reception switching means 8 is a high-frequency signal before being down-converted by the receiving circuit 6. Since the high frequency received signal before down-conversion can be prevented from being multiplied by the double wave of the clock signal, the S / N ratio of the received signal after down-conversion can be further improved. For this reason, the wireless communication performance (reception sensitivity) of the wireless communication device can be further improved.
  • the receiving circuit 6 of the high-frequency circuit 3 is a circuit to be controlled by the control unit 10, such as the low noise amplifier 15, the down-conversion unit 16, and the amplification circuit unit 17. It has a plurality of parts. Therefore, the power supply path of the control signal from the control unit 10 to the receiving circuit 6 is the main line path 23 common to the plurality of circuit parts 15, 16, and 17, and the circuit part 15 is divided from the main line path 23. 16 and 17, each having a plurality of branch paths 24 for supplying control signals. Each of the branch paths 24 is provided with filter means, and the filter means is configured to attenuate the noise component of the control signal caused by the harmonic wave of the clock signal by the filter means. It will be placed in the vicinity of each circuit section 15, 16, 17 respectively. For this reason, it is possible to more reliably prevent a situation in which the noise component of the harmonic wave of the clock signal is again added to the control signal after passing through the filter means.
  • the filter means is provided in the main path 23 and the filter means is not provided in each branch path 24, the number of filter means installed can be suppressed, and wireless communication due to the installation of the filter means can be achieved. An increase in the size of communication equipment can be prevented.
  • each The filter means of the branch path 24 also has a two-stage configuration that attenuates the harmonics of the clock signal. For this reason, the double wave of the clock signal in the control signal can be attenuated more reliably.
  • the present invention is not limited to the form of this embodiment, and may take various forms.
  • the transmission / reception switching unit 8 is provided.
  • a signal path selection unit such as a duplexer may be provided.
  • the signal path selection means uses the frequency difference between the reception signal output from the antenna 2 and the radio transmission signal output from the transmission circuit 7 toward the antenna 2, for example, the reception signal from the antenna 2 Is output, the received signal is supplied to the receiving circuit 6 by connecting the signal between the antenna 2 and the receiving circuit 6.
  • the signal path selection means has a configuration in which when a signal for radio transmission is output from the transmission circuit 7, the signal for radio transmission is supplied to the antenna 2 by connecting the transmission circuit 7 and the antenna 2. .
  • Some signal path selection means such as a duplexer having such a configuration require drive control by the control unit 10.
  • signal path selection means (required for driving control of the control unit 10)
  • a control signal supply path for supplying a control signal to is provided.
  • a filter means for attenuating a harmonic of a predetermined clock signal of the control signal may be provided in the control signal supply path.
  • the control signal supply path 22 for supplying a control signal from the control unit 10 to the receiving circuit 6 includes a main path 23 and branch paths 24 (24a to 24d).
  • the control unit 10 each circuit unit to be controlled in the receiving circuit 6 (LNA 15 and mixer 20 (20A, 20B), and amplifier circuit) Unit 17) may be connected to each other through separate control signal supply paths 26 (26a to 26d).
  • filter means for attenuating a harmonic of a predetermined clock signal of the control signal is provided in one or a plurality of the control signal supply paths 26a to 26d. Also good.
  • the filter means for attenuating the harmonics of the clock signal is provided in the vicinity of the circuit units 8, 15, 17, and 20 to be controlled in the control signal supply path.
  • the filter means may be provided at an appropriate position in consideration of component arrangement and the like.
  • the filter means for attenuating the double wave of the clock signal is provided in the control signal supply paths 12, 22 (23, 24), 26, the filter means is provided in the control signal supply path.
  • control signal supply path 13 for supplying the control signal from the control unit 10 to the transmission circuit 7 is provided with a filter means for attenuating the harmonic wave of the clock signal.
  • filter means for attenuating the harmonics of the clock signal is also provided in the control signal supply path 13. As a configuration to provide.
  • the clock signal supply path for supplying the clock signal from the clock generation circuit 5 to the control unit 10 also includes, for example, the reception frequency band of the antenna 2, the intermediate frequency band of the reception circuit 6, and the station. Filter means for attenuating a harmonic of a clock signal having a frequency in the frequency band of the partial oscillator may be provided.
  • the filter means provided in the branch paths 24a to 24d of the control signal supply path 22 are respectively a double wave having a frequency in a predetermined reception frequency band and an intermediate frequency band.
  • An example is shown in which both the harmonic and the harmonic wave having a frequency are attenuated.
  • the filter means provided in the branch path 24a is the reception frequency band. Attenuate one of the harmonics of a clock signal having a frequency of ⁇ and the harmonics of a clock signal having a frequency in the intermediate frequency band (for example, the harmonics of a clock signal having a frequency in the reception frequency band) It may be what you want to do.
  • the filter means provided in the branch path 24c of the control signal supply path 22 is designed to attenuate the harmonics of the intermediate frequency band clock signal.
  • the power described with reference to a wireless communication device capable of wireless transmission / reception is applied.
  • the present invention can also be applied to a reception-only wireless communication device.
  • the transmission circuit and transmission / reception switching means are omitted, and the control signal is supplied to the control signal supply path that supplies the control signal to the reception circuit of the high-frequency circuit.
  • a filter means is provided for attenuating the harmonics of the predetermined clock signal.
  • the present invention is applied to a wireless communication device including a circuit that generates a clock signal, and is particularly effective for a wireless communication device that requires improvement in reception sensitivity.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Noise Elimination (AREA)

Abstract

L’invention concerne un dispositif de communication sans fil (1) comprenant un circuit haute fréquence (3) connecté à une antenne (2) afin d’effectuer une opération de circuit prédéterminée pour une communication sans fil à l’aide de l’antenne (2) ; un circuit de génération d’horloge (5) pour générer et sortir un signal d’horloge ; et une partie de commande (10) pour commander l’opération de circuit du circuit haute fréquence (3). La partie de commande (10) comprend un circuit pour utiliser le signal d’horloge sorti du circuit de génération d’horloge (5). Des moyens de filtre, pour atténuer les composantes de bruit du signal de commande provoquées par une onde multipliée du signal d’horloge, sont disposés sur au moins une, par exemple, des parties X12, X23, Xa, Xb, Xc et Xd des chemins de fourniture de signaux de commande (12, 22) grâce auxquels le signal de commande est fourni de la partie de commande (10) au circuit haute fréquence (3) afin de commander l’opération de circuit du circuit haute fréquence (3).
PCT/JP2005/013395 2004-10-07 2005-07-21 Dispositif de communication sans fil WO2006038363A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004295134 2004-10-07
JP2004-295134 2004-10-07

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WO2006038363A1 true WO2006038363A1 (fr) 2006-04-13

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016213822A (ja) * 2015-05-08 2016-12-15 和碩聯合科技股▲分▼有限公司 携帯型電子機器

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000224061A (ja) * 1999-01-27 2000-08-11 Sharp Corp 放送受信機およびクロック動作回路
JP2001313585A (ja) * 2000-05-01 2001-11-09 Auto Network Gijutsu Kenkyusho:Kk 車載用無線装置
JP2004023396A (ja) * 2002-06-14 2004-01-22 Hitachi Kokusai Electric Inc 電子機器
JP2004104281A (ja) * 2002-09-06 2004-04-02 Tdk Corp 無線機器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000224061A (ja) * 1999-01-27 2000-08-11 Sharp Corp 放送受信機およびクロック動作回路
JP2001313585A (ja) * 2000-05-01 2001-11-09 Auto Network Gijutsu Kenkyusho:Kk 車載用無線装置
JP2004023396A (ja) * 2002-06-14 2004-01-22 Hitachi Kokusai Electric Inc 電子機器
JP2004104281A (ja) * 2002-09-06 2004-04-02 Tdk Corp 無線機器

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016213822A (ja) * 2015-05-08 2016-12-15 和碩聯合科技股▲分▼有限公司 携帯型電子機器

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