WO2006018818A1 - Minimizing power consumption in high frequency digital circuits - Google Patents

Minimizing power consumption in high frequency digital circuits Download PDF

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Publication number
WO2006018818A1
WO2006018818A1 PCT/IB2005/052715 IB2005052715W WO2006018818A1 WO 2006018818 A1 WO2006018818 A1 WO 2006018818A1 IB 2005052715 W IB2005052715 W IB 2005052715W WO 2006018818 A1 WO2006018818 A1 WO 2006018818A1
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WO
WIPO (PCT)
Prior art keywords
frequency
self
bias
digital circuit
resonant frequency
Prior art date
Application number
PCT/IB2005/052715
Other languages
French (fr)
Inventor
Henk Visser
Cicero Vaucher
Original Assignee
Koninklijke Philips Electronics, N.V.
U.S. Philips Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics, N.V., U.S. Philips Corporation filed Critical Koninklijke Philips Electronics, N.V.
Priority to KR1020077003535A priority Critical patent/KR20070033470A/en
Priority to JP2007526686A priority patent/JP2008510412A/en
Priority to EP05774786A priority patent/EP1782534A1/en
Publication of WO2006018818A1 publication Critical patent/WO2006018818A1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0233—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
    • H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
    • H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
    • H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
    • H03K3/288—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit
    • H03K3/2885—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit the input circuit having a differential configuration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
    • H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
    • H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
    • H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
    • H03K3/289—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable of the master-slave type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption

Definitions

  • the present invention relates to electronic digital circuitry, and more particularly to circuits and methods for operating high frequency dividers for minimized power consumption.
  • Reduced current demand in electronic devices translates directly into longer battery life and lower power dissipation.
  • Longer battery life is critical in wireless portable applications like cellphones, portable computers, and Wi-Fi wireless networking.
  • Power dissipation goes up as the square of the current demanded, and any wasted heat produced can unnecessarily shorten device life.
  • Semiconductor process variations and wide operating temperature ranges traditionally dictate high DC-biasing currents in order to guarantee reliable operation. Reducing these DC-biasing currents can lead to improved battery life.
  • a frequency divider to produce the in- phase (I) and quadrature-phase (Q) clocks needed by the radio transmitters and receivers.
  • a voltage controlled oscillator (VCO) is typically controlled by a phase locked loop (PLL) to synthesize one or more frequencies to drive the I-Q frequency divider.
  • PLL phase locked loop
  • Such dividers are conventionally constructed as two cross-coupled D-type flip-flops.
  • the typical I-Q frequency divider will free oscillate at some frequency of its own choosing if there is no oscillator input drive.
  • the self-resonant frequency represents the point where loop losses are minimum and positive feedback is maximum. This point represents maximum circuit power efficiency.
  • the free-oscillating frequency is affected by the DC-biasing currents applied. In conventional circuit design, these DC-biasing currents are fixed and set high enough to guarantee an operational margin over the range of process variations and operating temperatures that are expected to occur. In actual fact, such currents are at least double that which are really necessary. Reducing these margins can significantly reduce overall operating currents and contribute substantially to battery life in portable devices.
  • Each flip-flop comprises a gate section and a latch section. Each such section is respectively DC-biased by a gate-current (I gate ) and a latch-current (Ii atCh ) from independent current sources.
  • I gate gate-current
  • Ii atCh latch-current
  • Such self-resonant frequency has been observed to be dependent on the ratio of Igate and li atC h DC-biasing currents applied.
  • atCh DC-biasing currents can be varied over a wide range without any significant affect on the self-resonant frequency if the I gate /Iia tch ratio is maintained. Of course, such total current will directly affect battery consumption, and there is a minimal bias point where the circuit will no longer work.
  • the I-Q frequency divider can function reliably in operation at its minimum total I gate and Ii atch DC-biasing currents if the ratio of these currents is adjusted to result in a self- resonant frequency that approximates the oscillator input frequency.
  • a circuit embodiment of the present invention comprises a frequency divider connected to receive respective Igate and Iiatch DC-biasing currents. Such frequency divider will self-resonate at some frequency that depends in part on these DC-biasing currents.
  • Corresponding current sources provide programmable magnitudes for each of these DC-biasing currents, and can therefore affect the self-resonant frequency and overall power consumption.
  • the frequency divider is allowed to self-oscillate, and the DC-biasing currents are manipulated to cause the self-resonant frequency to approximate some target frequency.
  • the DC-biasing currents can be opportunistically lowered and still maintain reliable operation when the self-resonant frequency of the frequency divider is tuned to the target operational frequency. Such calibration is repeated as needed during the service life of the device.
  • An advantage of the present invention is a circuit is provided that can operate at reduced power.
  • a further advantage of the present invention is a circuit is provided that can extend battery life in portable devices.
  • a still further advantage of the present invention is that a method is provided for sensing an efficient DC-bias combination for a frequency divider.
  • Fig. 1 is a schematic diagram of a frequency divider circuit embodiment of the present invention
  • Fig. 2 is a flowchart diagram of a first method embodiment of the present invention, and is useful in the circuit of Fig. 1 ;
  • Fig. 3 is a flowchart diagram of a second method embodiment of the present invention, and is also useful in the circuit of Fig. 1.
  • Fig. 1 illustrates a frequency divider circuit embodiment of the present invention, and is referred to herein by the general reference numeral 100.
  • the frequency divider circuit 100 comprises a first gate section 102, a first latch section 104, a second gate section 106, and a second latch section 108 that is cross-coupled back to the first gate section 102.
  • a pair of output buffers 1 10 provides a differential output drive.
  • a frequency meter 112 measures the oscillations (if any) at this output.
  • a gate/latch bias generator 1 13 receives a control signal related to the self-resonant output frequency. It can switch off an oscillator input with a switch 1 14 during a calibration mode.
  • a temperature sensor is included in the bias generator 1 15 for this purpose.
  • the calibration mode may be engaged only once to detect and remove worst-case process margins, or every time the circuit is energized, or periodically, or on command.
  • the values to set the I-gate and I-latch bias currents, determined during calibration, can be stored in non-volatile digital memory or analog sample-and-hold devices.
  • a reference frequency input 1 16 is provided to the frequency meter 1 12.
  • a gate- bias output 1 18 from generator 1 13 is applied to an I-gate bias current source 120.
  • a latch- bias output 122 is applied to an I-latch bias current source 124.
  • the frequency divider circuit 100 is such that its self-resonant frequency is dependent on the ratio of the I-gate and I-latch bias currents provided by current sources 120 and 124. Such self-resonant frequency also corresponds with the frequency at which the frequency divider circuit 100 has its best input signal sensitivity. If operated at such a frequency, the required input drive can be reduced and the loading on an oscillator can be minimized. An object of this is to reduce operating power without sacrificing performance or reliability.
  • the sum total of the two I-gate and I-latch bias currents provided by current sources 120 and 124 is controlled by generator 1 12 to be just high enough to produce stable frequency divider circuit operation. Integrated circuit designers can optimize the high frequency performance of frequency divider circuit 100 by critically sizing the area of the gate pair transistors in relation to the latch pair transistors.
  • the optimum ratio to set for the two I-gate and I-latch bias currents is determined during a calibration mode. One, or the other, or both such currents can be manipulated for the desired effects.
  • the reference frequency input 1 16 is fixed to provide a frequency-measurement time-base.
  • the bias generator 1 13 switches off oscillator input switch 114, and manipulates the ratio of gate-bias 118 and latch-bias 122 outputs until the self-resonant output frequency approximates a desired target frequency. These bias values are then stored.
  • the reference frequency input 1 16 is adjusted to clock at the same frequency that the frequency divider circuit 100 should self- resonate.
  • the bias generator 113 switches off oscillator input switch 114 and manipulates the ratio of gate-bias 1 18 and latch-bias 122 outputs until the self-resonant output frequency sample approximates the reference frequency input 1 16. These bias values are then stored. Other methods are also possible that take advantage of circuitry already included for other purposes. After the initial finding of the current ratio that results in the desired self-resonant frequency, both the I-gate and I-latch bias currents are reduced in parallel, while maintaining their ratio, to the point where no divider output is detected. Too little bias current causes the device to turn off.
  • the I-gate and I-latch bias currents are tuned back up just high enough so that reliable frequency divider operation resumes. These bias current setpoints are then fixed, and the calibration mode is completed. Such currents are substantially less that those that would result if only worst-case process and temperature margins had to be fixed in the original integrated circuit design.
  • a circuit operation method embodiment of the present invention comprises measuring a first self-resonant frequency of a digital circuit in a step 202.
  • a first bias current applied to the digital circuit is adjusted to produce a second self-resonant frequency that approximates an operational frequency.
  • the power required by the digital circuit reduces during operation from the first to second self-resonant frequencies.
  • a second bias current applied to the digital circuit is adjusted to tune the circuit to the second self-resonant frequency.
  • the ratio of the first and second bias currents is principally manipulated to effectuate the second self-resonant frequency.
  • a step 212 the total of the first and second bias currents is adjusted to effectuate reduced power consumption by the digital circuit.
  • a minimum total for the first and second bias currents is detected that still allows the digital circuit to continue to operate.
  • a minimum total for the first and second bias currents, determined in the step of detecting, is set so the digital circuit will operate.
  • Fig. 3 represents another method embodiment of the present invention, and is referred to herein by the general reference numeral 300.
  • Method 300 is for reducing the power consumption of an electronic device during its operation. It comprises a step 302 that includes within an electronic device a digital circuit that has maximum signal input sensitivity at a self-resonant frequency, and such self-resonant frequency depends on at least one biasing input current.
  • a step 304 is for measuring the self-resonant frequency.
  • a step 306 is for adjusting at least one bias current applied to the digital circuit, to tune it to another self-resonant frequency that approximates an intended operational frequency.
  • a step 308 operates the digital circuit thereafter at the bias currents determined in the step of measuring.
  • the method 300 may comprise further steps.
  • a step 310 adjusts the ratio of a first bias current and a second bias current to tune to a self-resonant frequency that approximates an intended operational frequency.
  • a step 312 adjusts the total of the first and second bias currents to effectuate reduced power consumption by the digital circuit.
  • a step 314 detects a minimum total for the first and second bias currents that allows the digital circuit to continue to operate.
  • a step 316 fixes the first and second bias currents at respective values determined in detecting step 314.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

A circuit comprises a frequency divider connected to receive respective Igate and hatch DC-biasing currents. Such frequency divider will self-resonate at some frequency that depends, in part, on these DC-biasing currents. Corresponding current sources provide programmable magnitudes for each of these DC-biasing currents, and can therefore affect the self-resonant frequency and overall power consumption. During calibration, the frequency divider is allowed to self-oscillate, and the DC-biasing currents are manipulated to cause the self-resonant frequency to approximate some target frequency. The DC-biasing currents can be opportunistically lowered and still maintain reliable operation when the self­resonant frequency of the frequency divider is tuned to the target operational frequency. Such calibration is repeated as needed during the service life of the device.

Description

MINIMIZING POWER CONSUMPTION IN HIGH FREQUENCY DIGITAL CIRCUITS
The present invention relates to electronic digital circuitry, and more particularly to circuits and methods for operating high frequency dividers for minimized power consumption. Reduced current demand in electronic devices translates directly into longer battery life and lower power dissipation. Longer battery life is critical in wireless portable applications like cellphones, portable computers, and Wi-Fi wireless networking. Power dissipation goes up as the square of the current demanded, and any wasted heat produced can unnecessarily shorten device life. It is now very common practice to operate digital circuits with system clocks in excess of 1.0 GHz. A lot of power is consumed at these frequencies in just driving AC- voltages into capacitive impedance loads. Reductions in stray capacitance can limit parasitic currents. Semiconductor process variations and wide operating temperature ranges traditionally dictate high DC-biasing currents in order to guarantee reliable operation. Reducing these DC-biasing currents can lead to improved battery life.
Many wireless applications require the use of a frequency divider to produce the in- phase (I) and quadrature-phase (Q) clocks needed by the radio transmitters and receivers. A voltage controlled oscillator (VCO) is typically controlled by a phase locked loop (PLL) to synthesize one or more frequencies to drive the I-Q frequency divider. Such dividers are conventionally constructed as two cross-coupled D-type flip-flops.
The typical I-Q frequency divider will free oscillate at some frequency of its own choosing if there is no oscillator input drive. The self-resonant frequency represents the point where loop losses are minimum and positive feedback is maximum. This point represents maximum circuit power efficiency. The free-oscillating frequency is affected by the DC-biasing currents applied. In conventional circuit design, these DC-biasing currents are fixed and set high enough to guarantee an operational margin over the range of process variations and operating temperatures that are expected to occur. In actual fact, such currents are at least double that which are really necessary. Reducing these margins can significantly reduce overall operating currents and contribute substantially to battery life in portable devices.
Each flip-flop comprises a gate section and a latch section. Each such section is respectively DC-biased by a gate-current (Igate) and a latch-current (IiatCh) from independent current sources. Such self-resonant frequency has been observed to be dependent on the ratio of Igate and liatCh DC-biasing currents applied. The total of the Igate and I|atCh DC-biasing currents can be varied over a wide range without any significant affect on the self-resonant frequency if the Igate/Iiatch ratio is maintained. Of course, such total current will directly affect battery consumption, and there is a minimal bias point where the circuit will no longer work.
The I-Q frequency divider can function reliably in operation at its minimum total Igate and Iiatch DC-biasing currents if the ratio of these currents is adjusted to result in a self- resonant frequency that approximates the oscillator input frequency. Briefly, a circuit embodiment of the present invention comprises a frequency divider connected to receive respective Igate and Iiatch DC-biasing currents. Such frequency divider will self-resonate at some frequency that depends in part on these DC-biasing currents. Corresponding current sources provide programmable magnitudes for each of these DC-biasing currents, and can therefore affect the self-resonant frequency and overall power consumption. During calibration, the frequency divider is allowed to self-oscillate, and the DC-biasing currents are manipulated to cause the self-resonant frequency to approximate some target frequency. The DC-biasing currents can be opportunistically lowered and still maintain reliable operation when the self-resonant frequency of the frequency divider is tuned to the target operational frequency. Such calibration is repeated as needed during the service life of the device.
An advantage of the present invention is a circuit is provided that can operate at reduced power.
A further advantage of the present invention is a circuit is provided that can extend battery life in portable devices. A still further advantage of the present invention is that a method is provided for sensing an efficient DC-bias combination for a frequency divider.
The above and still further objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description of specific embodiments thereof, especially when taken in conjunction with the accompanying drawings.
Fig. 1 is a schematic diagram of a frequency divider circuit embodiment of the present invention; Fig. 2 is a flowchart diagram of a first method embodiment of the present invention, and is useful in the circuit of Fig. 1 ; and
Fig. 3 is a flowchart diagram of a second method embodiment of the present invention, and is also useful in the circuit of Fig. 1. Fig. 1 illustrates a frequency divider circuit embodiment of the present invention, and is referred to herein by the general reference numeral 100. The frequency divider circuit 100 comprises a first gate section 102, a first latch section 104, a second gate section 106, and a second latch section 108 that is cross-coupled back to the first gate section 102. A pair of output buffers 1 10 provides a differential output drive. A frequency meter 112 measures the oscillations (if any) at this output. A gate/latch bias generator 1 13 receives a control signal related to the self-resonant output frequency. It can switch off an oscillator input with a switch 1 14 during a calibration mode.
If a large operational temperature change since the last calibration is detected, it may be necessary to re-run the calibration mode. A temperature sensor is included in the bias generator 1 15 for this purpose. The calibration mode may be engaged only once to detect and remove worst-case process margins, or every time the circuit is energized, or periodically, or on command. The values to set the I-gate and I-latch bias currents, determined during calibration, can be stored in non-volatile digital memory or analog sample-and-hold devices. A reference frequency input 1 16 is provided to the frequency meter 1 12. A gate- bias output 1 18 from generator 1 13 is applied to an I-gate bias current source 120. A latch- bias output 122 is applied to an I-latch bias current source 124. These respectively control the DC-bias applied to first and second gate sections 102 and 106, and first and second latch sections 104 and 108. Manipulating these currents will cause the self-resonant frequency to shift, and such effects are detected by frequency meter 112.
The frequency divider circuit 100 is such that its self-resonant frequency is dependent on the ratio of the I-gate and I-latch bias currents provided by current sources 120 and 124. Such self-resonant frequency also corresponds with the frequency at which the frequency divider circuit 100 has its best input signal sensitivity. If operated at such a frequency, the required input drive can be reduced and the loading on an oscillator can be minimized. An object of this is to reduce operating power without sacrificing performance or reliability. The sum total of the two I-gate and I-latch bias currents provided by current sources 120 and 124 is controlled by generator 1 12 to be just high enough to produce stable frequency divider circuit operation. Integrated circuit designers can optimize the high frequency performance of frequency divider circuit 100 by critically sizing the area of the gate pair transistors in relation to the latch pair transistors.
The optimum ratio to set for the two I-gate and I-latch bias currents is determined during a calibration mode. One, or the other, or both such currents can be manipulated for the desired effects. In one embodiment, the reference frequency input 1 16 is fixed to provide a frequency-measurement time-base. The bias generator 1 13 switches off oscillator input switch 114, and manipulates the ratio of gate-bias 118 and latch-bias 122 outputs until the self-resonant output frequency approximates a desired target frequency. These bias values are then stored.
In another embodiment of the present invention, the reference frequency input 1 16 is adjusted to clock at the same frequency that the frequency divider circuit 100 should self- resonate. The bias generator 113 switches off oscillator input switch 114 and manipulates the ratio of gate-bias 1 18 and latch-bias 122 outputs until the self-resonant output frequency sample approximates the reference frequency input 1 16. These bias values are then stored. Other methods are also possible that take advantage of circuitry already included for other purposes. After the initial finding of the current ratio that results in the desired self-resonant frequency, both the I-gate and I-latch bias currents are reduced in parallel, while maintaining their ratio, to the point where no divider output is detected. Too little bias current causes the device to turn off. The I-gate and I-latch bias currents are tuned back up just high enough so that reliable frequency divider operation resumes. These bias current setpoints are then fixed, and the calibration mode is completed. Such currents are substantially less that those that would result if only worst-case process and temperature margins had to be fixed in the original integrated circuit design.
A circuit operation method embodiment of the present invention, herein referred to by the general reference numeral 200, comprises measuring a first self-resonant frequency of a digital circuit in a step 202. In a step 204, a first bias current applied to the digital circuit is adjusted to produce a second self-resonant frequency that approximates an operational frequency. The power required by the digital circuit reduces during operation from the first to second self-resonant frequencies. In a step 208, a second bias current applied to the digital circuit is adjusted to tune the circuit to the second self-resonant frequency. In a step 210, the ratio of the first and second bias currents is principally manipulated to effectuate the second self-resonant frequency. In a step 212, the total of the first and second bias currents is adjusted to effectuate reduced power consumption by the digital circuit. In a step 214, a minimum total for the first and second bias currents is detected that still allows the digital circuit to continue to operate. In a step 216, a minimum total for the first and second bias currents, determined in the step of detecting, is set so the digital circuit will operate.
In general, embodiments of the present invention reduce the power consumption of electronic circuits during operation by measuring circuit behavior and adjusting various operating currents below that which would otherwise be dictated by worst-case process and/or temperature variations. Such worst-case scenarios are rarely experienced in actual practice and use, and the considerable savings can benefit portable device battery life. Fig. 3 represents another method embodiment of the present invention, and is referred to herein by the general reference numeral 300. Method 300 is for reducing the power consumption of an electronic device during its operation. It comprises a step 302 that includes within an electronic device a digital circuit that has maximum signal input sensitivity at a self-resonant frequency, and such self-resonant frequency depends on at least one biasing input current. A step 304 is for measuring the self-resonant frequency. A step 306 is for adjusting at least one bias current applied to the digital circuit, to tune it to another self-resonant frequency that approximates an intended operational frequency. A step 308 operates the digital circuit thereafter at the bias currents determined in the step of measuring. The method 300 may comprise further steps. A step 310 adjusts the ratio of a first bias current and a second bias current to tune to a self-resonant frequency that approximates an intended operational frequency. A step 312 adjusts the total of the first and second bias currents to effectuate reduced power consumption by the digital circuit. A step 314 detects a minimum total for the first and second bias currents that allows the digital circuit to continue to operate. And a step 316 fixes the first and second bias currents at respective values determined in detecting step 314. Although particular embodiments of the present invention have been described and illustrated, such is not intended to limit the invention. Modifications and changes will no doubt become apparent to those skilled in the art, and it is intended that the invention only be limited by the scope of the appended claims.

Claims

CLAIMS What is claimed is:
1. A method (200) of circuit operation, comprising: measuring a first self- resonant frequency (202) of a digital circuit; and adjusting a first bias current (204) applied to said digital circuit to produce a second self-resonant frequency that approximates an operational frequency; wherein, power required by said digital circuit reduces during operation from said first to second self-resonant frequencies.
2. The method of claim 1 , further comprising: adjusting a second bias current (206) applied to said digital circuit to affect said second self-resonant frequency.
3. The method of claim 2, further comprising: adjusting the ratio (208) of said first and second bias currents to effectuate said second self-resonant frequency.
4. The method of claim 2, further comprising: adjusting the total (210) of said first and second bias currents to effectuate reduced power consumption by said digital circuit.
5. The method of claim 4, further comprising: detecting a minimum total (210) for said first and second bias currents that allows said digital circuit to continue to operate.
6. The method of claim 5, further comprising: setting a minimum total (210) for said first and second bias currents, determined in the step of detecting, so said digital circuit will operate.
7. A method (300) for reducing the power consumption of an electronic device during its operation, comprising: including within an electronic device (302) a digital circuit that has maximum signal input sensitivity at a self-resonant frequency, and such self- resonant frequency depends on at least one biasing input current; measuring said self- resonant frequency (304); adjusting at least one bias current (306) applied to said digital circuit, to tune it to another self-resonant frequency that approximates an intended operational frequency; and operating said digital circuit thereafter (308) at said bias currents determined in the step of measuring.
8. The method of claim 7, further comprising the steps of: adjusting the ratio (310) of a first bias current and a second bias current to tune to a self-resonant frequency that approximates an intended operational frequency; adjusting the total (312) of said first and second bias currents to effectuate reduced power consumption by said digital circuit; detecting a minimum total (314) for said first and second bias currents that allows said digital circuit to continue to operate; and fixating (316) said first and second bias currents at respective values determined in the step of detecting.
9. A semiconductor integrated electronic circuit (100), comprising: a frequency divider having at least a gate (102, 106) and a latch (104, 108), an oscillator input, and a divider output, and that is subject to self-resonance at frequencies that depend on particular bias currents supplied to it; a gate bias current source (120) that can be programmed to supply a plurality of gate bias currents to the frequency divider; a latch bias current source (124) that can be programmed to supply a plurality of latch bias currents to the frequency divider; a frequency meter (112) connected to sense signals at said divider output and to indicate their oscillation frequency; and a controller (1 13) connected to program the gate and latch bias current sources such that the frequency meter indicates the frequency divider self-resonates near a particular target frequency.
10. The semiconductor integrated electronic circuit of claim 9, wherein: the controller (1 13) is connected to a switch (1 14) that isolates said oscillator input to the frequency divider to enable such self-resonance.
1 1. The semiconductor integrated electronic circuit of claim 9, wherein: the controller (1 13) first determines a ratio of gate and latch bias currents that cause said self- resonant frequency to approximate said particular target frequency, then it determines what minimum total bias current will sustain frequency divider functionality.
12. The semiconductor integrated electronic circuit of claim 1 1, further comprising: a temperature sensor (1 15) disposed within the controller that monitors temperature changes and, if a sufficient change is detected, to cause the controller to re- determine what minimum total bias current will sustain frequency divider functionality.
PCT/IB2005/052715 2004-08-17 2005-08-17 Minimizing power consumption in high frequency digital circuits WO2006018818A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020077003535A KR20070033470A (en) 2004-08-17 2005-08-17 Minimize power consumption in high frequency digital circuits
JP2007526686A JP2008510412A (en) 2004-08-17 2005-08-17 Minimizing power consumption in high-frequency digital circuits
EP05774786A EP1782534A1 (en) 2004-08-17 2005-08-17 Minimizing power consumption by tuning self-resonance in a frequency divider

Applications Claiming Priority (2)

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US60244104P 2004-08-17 2004-08-17
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KR100967043B1 (en) * 2008-09-23 2010-06-29 삼성전기주식회사 Frequency divider using latch structure
US8456202B2 (en) * 2011-02-15 2013-06-04 Texas Instruments Incorporated Latch divider

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JP2008510412A (en) 2008-04-03

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