KR20070033470A - Minimize power consumption in high frequency digital circuits - Google Patents

Abstract

The circuit includes a frequency divider connected to receive the DC-bias currents I gate and I latch, respectively. Such a frequency divider self resonates at some frequencies which depend in part on this DC-bias current. The corresponding current source for each of these DC-bias currents provides a programmable magnitude, which can affect the magnetic resonance frequency and overall power consumption. During the adjustment period, the frequency divider is allowed to oscillate and the DC-bias current is adjusted so that the magnetic resonance frequency approaches some target frequency. The DC-bias current is properly lowered and still maintains reliable operation when the self-resonant frequency of the frequency divider is tuned to the target operating frequency. Such adjustment is repeated as necessary during the service life of the device.

Description

MINIMIZING POWER CONSUMPTION IN HIGH FREQUENCY DIGITAL CIRCUITS}

The present invention relates to electronic digital circuits, and more particularly to a method and circuit for operating a high frequency divider for minimizing power consumption.

Reduced current requirements in electronic devices are directly accounted for for longer battery life and lower power consumption. Longer battery life is critical for wireless portable applications such as cell phones, portable computers and Wi-Fi wireless networks. Power consumption rises with the square of the required current, and any waste heat generated unnecessarily shortens the life of the device.

It is now very common practice to operate digital circuits with system clocks above 1.0 GHz. Only a large amount of power is consumed at these frequencies to drive capacitive impedance loads with AC voltage. Reduction of stray capacitance can limit eddy currents. Semiconductor process variations and wide temperature range adjustments traditionally exhibit high DC-bias currents to ensure reliable operation.

Reducing this DC-bias current results in improved battery life.

Many wireless applications require the use of frequency dividers to generate in-phase (I) and quadrature-phase (Q) clocks required by radio transmitters and receivers. The voltage controlled oscillator (VCO) is typically controlled by a phase control loop (PLL) for summing one or more frequencies to drive the I-Q frequency divider. Such distributors are typically configured as two mutually coupled D-type flip-flops.

The typical I-Q frequency divider will not oscillate at some frequency it selects itself if there is no oscillator input drive. The self resonant frequency means a point where loop loss is minimum and positive feedback is maximum. This point represents the maximum circuit power efficiency. Free oscillation frequency is affected by the applied DC-bias current. In conventional circuit designs, this DC-bias current is fixed and set high enough to guarantee a driveable margin beyond the range of possible operating temperatures and process variations. In fact, such a current is at least twice as much as is really necessary. Reducing these margins can drastically reduce overall drive current and make a significant contribution to battery consumption in portable devices.

Each flip-flop includes a gate section and a latch section. Each of these sections is each DC-biased by a gate current I _gate and a latch current I _latch from separate current sources. Such self-resonant frequency has been shown to be dependent on the ratio of the applied DC-bias current I _gate and I _latch . The overall DC-bias current I _gate and I _latch can vary widely, without any significant influence on the self-resonant frequency via the I _gate / I _latch ratio. Of course, such total current will directly affect battery life, and there is a minimum bias point at which the circuit no longer operates.

The IQ frequency divider can reliably operate when driven at the minimum total DC bias current of the divider when the ratio of I _gate and I _latch currents is adjusted to result in a self resonant frequency close to the oscillator input frequency.

Briefly, circuit embodiments of the present invention include a frequency divider coupled to receive a DC-bias current I _gate and an I _latch , respectively. Such a frequency divider will self resonate at some frequencies that are partly dependent on this DC-bias current. The corresponding current source provides a programmable magnitude for each of these DC-bias currents, and thus can affect self-resonant frequency and overall power consumption. During the calibration period, the frequency divider is self-oscillating and the DC-bias current is adjusted so that the self resonant frequency approaches some target frequency. The DC-bias current can be lowered appropriately and still maintain reliable operation when the self-resonant frequency of the frequency divider is tuned to the desired operating frequency. Such adjustment is repeated as required for the service life of the device.

An advantage of the present invention is that a circuit capable of driving with reduced power is provided.

A further advantage of the present invention is that circuitry is provided that can extend battery life in portable devices.

A further advantage of the present invention is that a method is provided for recognizing an efficient DC-bias combination for a frequency divider.

These and further objects, features and advantages of the invention will become apparent from consideration of the following detailed description of particular embodiments of the invention, taken in conjunction with the accompanying drawings.

1 is a schematic diagram of a frequency divider circuit embodiment of the present invention.

FIG. 2 is a flow chart useful in the circuit of FIG. 1, for an embodiment of the first method of the present invention. FIG.

3 is a flow chart useful for the circuit of FIG. 1, for an embodiment of a second method of the present invention;

1 shows an embodiment of the frequency divider circuit of the present invention, referred to here by the general reference numeral 100. The frequency divider circuit 100 includes a second latch section reversely inter-coupled to the first gate section 102, the first latch section 104, the second gate section 106, and the first gate section 102. 108. The pair of output buffers 110 provides differential output drive. Frequency meter 112 measures the oscillation (if any) at this output. Gate / latch bias generator 113 receives a control signal related to the self resonant output frequency. It can switch off the oscillation input to switch 114 during the adjustment mode.

If a large drive temperature change has been detected since the last adjustment, it may be necessary to re-run the adjustment mode. The temperature sensor is included in the bias generator 115 for this purpose. The calibration mode may be used in the worst case, whenever energy is supplied to the circuit, or only once, periodically or in order to detect and remove the process margin of the command. The values of the DC-biased currents I _gate and I _latch set during the adjustment period can be stored in nonvolatile digital memory or analog sample and hold devices.

The reference frequency input 116 may be provided to the frequency meter 112. Gate bias output 118 from gate bias generator 113 is applied to I _gate bias current source 120. Latch bias output 122 is applied to an I _latch bias current source 124. Each of these controls the DC-bias applied to the first and second gate sections 102 and 106 and the first and second latch sections 104 and 108. By adjusting these currents the resonant frequency can be shifted and such effects are detected by the frequency meter 112. The frequency divider circuit 100 is thus dependent on the magnetic resonance frequency of the circuit at the ratio of the I-gate and I-bias currents applied by the current sources 120 and 124. Such self resonant frequency also corresponds to the frequency at which the frequency distribution circuit 100 has the best input signal sensitivity. If operating at such frequency, the required input drive can be reduced and the load on the oscillator can be minimized. The purpose is to reduce the driving power without compromising performance or reliability.

The sum of the two DC-bias currents (I _gate and I _latch ) supplied by current sources 120 and 124 is controlled by generator 113 to be high enough to provide stable frequency divider circuit operation. The integrated circuit designer can optimize the high frequency performance of the frequency divider circuit 100 by accurately allocating the gate pair transistor region associated with the latch pair transistor.

Setting the optimization ratio for the two bias currents I _gate and I _latch is determined during adjustment mode. One, the other, or two such currents can be manipulated for the desired effect. In one embodiment, the reference frequency input 116 is fixed to provide a frequency-measurement time-base. The bias generator 113 switches off the oscillation input switch 114 and adjusts the ratio of the gate bias 118 and latch bias 112 outputs until the self-resonant output frequency approaches the desired target frequency. These bias values are then stored.

In another embodiment of the invention, the reference frequency input 116 adjusts the clock at a frequency equal to the frequency at which the frequency distribution circuit 100 should self resonate. The bias generator 113 turns off the oscillator input switch 114 and adjusts the ratio of the gate bias 118 and latch bias 122 output until the self-resonant output frequency sample is close to the reference frequency input 116. do. These bias values are then stored. Other methods using circuits already included for other purposes are also possible.

After first finding the current ratio that leads to the desired self resonant frequency, the two bias currents I _gate and I _latch are reduced side by side while maintaining the ratio to the point where no divider output is detected. Too small a bias current turns the device off. The two bias currents, I _gate and I _latch , again rise moderately high, allowing the reliable frequency divider to resume operation. These bias current set points are then fixed and the adjustment mode is complete. Such currents are much smaller than the currents that result only if the worst case process and temperature margins have to be fixed in the original integrated circuit design.

A circuit driving method embodiment of the present invention, referred to herein by reference numeral 200, comprises a first self resonant frequency measurement of a digital circuit at step 202. In step 204, the first bias current applied to the digital circuit is adjusted to produce a second magnetic resonance frequency close to the drive frequency. The power required by the digital circuit is reduced during operation from the first self resonant frequency to the second self resonant frequency. In step 208 a second bias current applied to the digital circuit is adjusted to tune the circuit to a second self resonant frequency. In step 210 the ratio of the first and second bias currents is in principle adjusted to realize a second self resonant frequency. In step 212, the sum of the first and second bias currents is adjusted to realize power reduction reduction by the digital circuit. In step 214 the minimum value of the sum for the first and second bias currents is detected, allowing the digital circuit to still operate. In step 216, the minimum value of the sum of the first and second bias currents determined in the detecting step will be set so that the digital circuit will operate.

In general, embodiments of the present invention reduce power consumption of electronic circuits during operation by adjusting circuit operating measurements and various drive current sub-values otherwise indicated by worst-case process and / or temperature changes. Such worst case scenarios are rare in practical applications and uses, and these significant savings can benefit battery life of portable devices.

3 shows an embodiment of another method of the present invention, which is referred to herein by reference numeral 300. The method 300 is for reducing its power consumption during electronic device operation. It includes step 302 comprising a digital circuit having a maximum input signal sensitivity at a magnetic resonant frequency in the electronic device, the magnetic resonant frequency being dependent on at least one bias input current. Step 304 relates to magnetic resonance frequency measurements. Step 306 is to tune it to another magnetic resonant frequency close to the intended operating frequency in order to adjust the at least one bias current applied to the digital circuit. Step 308 then drives the digital circuit at the bias current determined in the measurement step. The method 300 may include further steps. Step 310 adjusts the ratio of the first bias current and the second bias current to tune the self resonant frequency close to the intended operating frequency. Step 312 adjusts the sum of the first and second bias currents to affect the reduction in power consumption by the digital circuit. Step 314 detects the minimum sum of the first and second bias currents causing the digital circuit to continue operation. Step 316 then locks the first and second bias currents at their respective values determined in detection step 314.

Although specific embodiments of the invention have been described and illustrated, it is not intended to limit the invention. Modifications and variations will no doubt be apparent to those skilled in the art, and the invention is intended to be limited only by the appended claims.

The invention is applicable to electronic digital circuits, in particular to methods and circuits for high frequency divider operation for minimizing power consumption.

Claims (12)

As a circuit operation method 200, Measuring the first magnetic resonance frequency of the digital circuit (202); And Adjusting 204 a first bias current applied to the above-mentioned digital circuit which produces a second self resonant frequency close to the operating frequency. Include, Wherein the power required by the digital circuit is reduced during operation from the first self resonant frequency to a second self resonant frequency. The method of claim 1, Adjusting a second bias current applied to the digital circuit executing the second self resonant frequency. The method of claim 2, Adjusting (208) a ratio of first and second bias currents to effect the second self resonant frequency. According to claim 2, Adjusting (210) the sum of the first and second bias currents to realize a reduction in power consumption by the digital circuit. The method of claim 4 wherein Detecting (210) a minimum sum of said first and second bias currents for causing said digital circuit to continue operating. The method of claim 5 wherein Setting (210) a minimum sum of the first and second bias currents determined in the detecting step, in which the digital circuit will operate. A method 300 for reducing power consumption during an operation period of an electronic device, the method comprising: Including a digital circuit having a maximum signal input sensitivity at a magnetic resonant frequency in the electronic device, wherein the magnetic resonant frequency is dependent on at least one bias input current; Measuring (304) the magnetic resonance frequency; Adjusting (306) at least one bias current applied to the digital circuit to tune the digital circuit to another magnetic resonant frequency approaching the intended drive frequency; And And subsequently driving said digital circuit (308) at said bias current determined in said measuring step (300). In claim 7, Adjusting the ratio of the first and second bias currents 310 to tune to a self resonant frequency close to the intended operating frequency; Adjusting (312) the sum of the first and second bias currents to realize a reduction in power consumption by the digital circuit; Detecting (314) a minimum sum of the first and second bias currents causing the digital circuit to continue operating; Fixing (316) the first and second bias currents at respective values determined in the detecting step. As a semiconductor integrated electronic circuit 100, A frequency divider self-resonant at a frequency dependent on a particular bias current applied to the divider, the frequency divider having at least gates (102, 106) and latches (104, 108), oscillator inputs and divider outputs; A gate bias current source 120 programmable to supply a plurality of gate bias currents to the frequency divider; And A latch bias current source 124 programmable to supply a plurality of latch bias currents to a frequency divider; And A frequency meter 112 connected to sense the signal at the divider output and indicate its oscillation frequency; And And a controller (113) coupled to program the gate and latch bias current source to indicate that the frequency meter indicates that a frequency divider is self-resonant near a particular target frequency. 10. The semiconductor integrated electronic circuit according to claim 9, wherein the controller (113) is connected to a switch (114) that separates the oscillator input to enable a frequency divider to enable such magnetic resonance. 10. The controller of claim 9, wherein the controller 113 first determines a ratio of gate and latch bias currents resulting in the self resonant frequency close to the particular target frequency, and then the minimum value of the sum of any bias currents maintains the frequency divider function. Semiconductor integrated electronic circuitry. 12. A temperature sensor (115) arranged in the controller according to claim 11, wherein the temperature sensor (115) is arranged in the controller to observe the temperature change and, if a sufficient change is detected, to cause the controller to re-determine which minimum current of bias current will maintain the frequency divider function. The semiconductor integrated electronic circuit further comprising.

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