WO2006004255A1 - ETCHANT FOR WET ETCHING AlXGaI-XAs EPITAXIAL LAYER AND METHOD FOR MANUFACTURING SEMI¬ CONDUCTOR DEVICE USING THE ETCHANT - Google Patents

ETCHANT FOR WET ETCHING AlXGaI-XAs EPITAXIAL LAYER AND METHOD FOR MANUFACTURING SEMI¬ CONDUCTOR DEVICE USING THE ETCHANT Download PDF

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Publication number
WO2006004255A1
WO2006004255A1 PCT/KR2005/000836 KR2005000836W WO2006004255A1 WO 2006004255 A1 WO2006004255 A1 WO 2006004255A1 KR 2005000836 W KR2005000836 W KR 2005000836W WO 2006004255 A1 WO2006004255 A1 WO 2006004255A1
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Prior art keywords
etchant
etching
mesa
epitaxial layer
layer
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PCT/KR2005/000836
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French (fr)
Inventor
O'dae Kwon
Moojin Kim
Dongkwon Kim
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Postech Academy-Industry Foundation
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Publication of WO2006004255A1 publication Critical patent/WO2006004255A1/en

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B67—OPENING, CLOSING OR CLEANING BOTTLES, JARS OR SIMILAR CONTAINERS; LIQUID HANDLING
    • B67D—DISPENSING, DELIVERING OR TRANSFERRING LIQUIDS, NOT OTHERWISE PROVIDED FOR
    • B67D7/00—Apparatus or devices for transferring liquids from bulk storage containers or reservoirs into vehicles or into portable containers, e.g. for retail sale purposes
    • B67D7/04—Apparatus or devices for transferring liquids from bulk storage containers or reservoirs into vehicles or into portable containers, e.g. for retail sale purposes for transferring fuels, lubricants or mixed fuels and lubricants
    • B67D7/0476—Vapour recovery systems
    • B67D7/0478—Vapour recovery systems constructional features or components
    • B67D7/048—Vapour flow control means, e.g. valves, pumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
    • H01L29/66318—Heterojunction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65D—CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS, e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES, DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS; ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR; PACKAGING ELEMENTS; PACKAGES
    • B65D90/00—Component parts, details or accessories for large containers
    • B65D90/22—Safety features
    • B65D90/30—Recovery of escaped vapours
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B67—OPENING, CLOSING OR CLEANING BOTTLES, JARS OR SIMILAR CONTAINERS; LIQUID HANDLING
    • B67D—DISPENSING, DELIVERING OR TRANSFERRING LIQUIDS, NOT OTHERWISE PROVIDED FOR
    • B67D7/00—Apparatus or devices for transferring liquids from bulk storage containers or reservoirs into vehicles or into portable containers, e.g. for retail sale purposes
    • B67D7/06—Details or accessories
    • B67D7/78—Arrangements of storage tanks, reservoirs or pipe-lines

Definitions

  • the present invention relates to an etchant for etching an epitaxial layer and a method of manufacturing semiconductor devices using the same, and more par ⁇ ticularly, to an etchant for wet etching an Al Ga As epitaxial layer and a method of
  • X. 1-X. manufacturing semiconductor devices including an operation of forming a mesa using the etchant, in which the semiconductor devices may be optical switch devices or unit elements using a laser.
  • a wet etching process using a chemical reaction is widely used to manufacture devices such as heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), and semiconductor lasers.
  • HBTs heterojunction bipolar transistors
  • HEMTs high electron mobility transistors
  • semiconductor lasers semiconductor lasers.
  • Previous wet etching processes have usually used selective etching characteristics, limiting their use to situations where a vertical mesa sidewall (hereinafter, referred to as a 'vertical mesa') does not adversely affect the device characteristics.
  • Dry etching is an essential process in the fabrication of devices, including a vertical mesa. Etching a vertical sidewall using dry etching is an already known technology. For example, it can be found in Mats Hagberg et al., J. Vac. Sci. Technol. B 12(2), Mar/Apr 1994, and Jun-youn Kim et al., J. Vac. Sci. Technol. B 19(4), Jul/Aug 2001. As shown in these publications, the dry etching process andits related equipmentare expensive, andthe time taken to developthenecessary high vacuum lengthens the overall process time.
  • the wet etching process has characteristics such as isotropic etching, low aspect ratio, and undercut, unlike the dry etching process.
  • SOS photonic quantum ring
  • PQR photonic quantum ring
  • SOS photonic quantum ring
  • PQR laser unit devices includes forming a multi-layer structured semiconductor layer having a plurality of GaAs/ AlGaAs epitaxial layers, and mesa-etching them.
  • DBR distributed bragg reflector
  • n-type DBR consisting of GaAs/ AlGaAs epitaxial layers
  • GaAs active layer between the above DBRs the fabrication includes the processes of etching the multi ⁇ layer structured semiconductor layer consisting of GaAs/ AlGaAs epitaxial layers and forming a mesa having a vertical and smooth sidewall down to the active layer. Disclosure of Invention
  • the present invention provides an etchant for etching an Al Ga As epitaxial layer to provide a vertical mesa by etching a multi-layer structured epitaxial layer using a wet etching process with lower production expenses than a dry etching process.
  • the present invention also provides a method of fabricating semiconductor devices for providing a desired patternshape and a mesa with a vertical and smooth sidewalls through etching an Al x Ga 1-x As epitaxial layer using the etchant.
  • an etchant for etching an Al Ga As (0 ⁇ x ⁇ 1) epitaxial layer including a mixture of H PO , H O , and CH OH.
  • the mixture may have a H PO : H O : CH OH volume ratio of 3: 1: 1.
  • the temperature of the mixture is at least 40 0 C.
  • a method of manufacturing semiconductor devices including forming a structure including an Al
  • Ga l-x As (0 ⁇ x ⁇ 1) epitaxial layer A mask pattern is formed on the structure.
  • Ga l-x As e r pitaxial lay J er is etched by J a mixture of H 3 PO 4 , H 2O 2, and CH 3 OH using & the mask pattern as an etch mask, thereby forming a mesa.
  • the etching of the Al Ga As epitaxial layer may be performed by agitating the x l-x mixture.
  • the etching of the Al x Ga l-x As epitaxial layer may be performed using a water bath apparatus.
  • the mask pattern may be composed of photoresist.
  • the method may further include cleaning the mesa using de-ionized water.
  • the cleaning may be performed for 1-5 minutes.
  • an Al Ga As (0 ⁇ x ⁇ 1) epitaxial layer is wet x 1-x etched using the etchant, which is composed of a mixture of H 3 PO 4 , H 2O 2, and CH 3 OH, thereby providing isotropic etching characteristics and forming a mesa with vertical sidewalls.
  • the mesa can be provided with a smooth surface on its sidewalls, since the etch selectivity of the GaAs layer and the AlGaAs layer is close to 1.
  • the mesa can have a desired shape in accordance with the shape of the mask pattern, for example, a circular shape. Therefore, according to the present invention, a large array of vertical mesa can be fabricated much more cheaply than with dry etching.
  • FIG. 1 is a flow chart illustrating a method of fabricating semiconductor devices according to an embodiment of the present invention
  • FIGS. 2A through 2E are sectional views illustrating processing sequences of the method of fabricating semiconductor devices of FIG. 1 according to an embodiment of the present invention
  • FIG. 3 is a diagram of a water bath apparatus suitable for use as a wet-etching apparatus in the fabrication of semiconductor devices according to the present invention
  • FIG. 4 is a table illustrating a sample structure of an epitaxial layer to be etched in an exemplary experiment of the present invention
  • FIGS. 5 A through 5C are photographs illustrating the lateral and upper surfaces of a mesa formed through a wet-etching process using an etchant of the present invention
  • FIGS. 6 A and 6B are photographs illustrating the lateral and upper surfaces of a mesa formed through a wet-etching process using aconventional etchant
  • FIG. 7A is a photograph illustrating surface roughness of a substrate in a mesa formed through a conventional dry-etching process.
  • FIGS. 7B through 7F are photographs illustrating surface roughness of a substrate in accordance with the temperature of an etchant when a mesa is formed by a method of fabricating semiconductor devices according to the present invention.
  • An etchant of the present invention includes a mixture of H PO , H O , and CH OH.
  • the etchant of the present invention is particularly effective for etching a multi- layer structure of an Al Ga As (0 ⁇ x ⁇ 1) epitaxial layer.
  • the multi-layer structure of an Al x Ga 1-x As (0 ⁇ x ⁇ 1) epitaxial layer is etched using the etchant of the present invention, thereby forming a vertical mesa having a bias of about 0.88 [1 -(horizontal etch rate/vertical etch rate)], which is close to anisotropic etching characteristics. Further, it is possible to form the desired shape of mesa, for example a circular mesa. [28] In the formation of a vertical mesa by etching the multi-layer structure of the Al Ga
  • the etchant As (0 ⁇ x ⁇ 1) epitaxial layer using the etchant of the present invention, it is found l-x that surface roughness of the mesa can be improved as the temperature of the etchant is increased.
  • the etchant is maintained at at least 40 0 C during etching.
  • etching is performed on the multi-layer structure of the Al x Ga l-x As (0 ⁇ x ⁇ 1) epitaxial layer to form an active layer having GaAs quantum wells, between a p-type DBR and an n-type DBR, thereby forming a circular mesa having a vertical sidewalls.
  • FIG. 1 is a flow chart illustrating a method of fabricating semiconductor devices according to an embodiment of the present invention.
  • FIGS. 2A through 2E are sectional views illustrating processing sequences of the method of fabricating semi ⁇ conductor devices of FIG. 1 according to an embodiment of the present invention.
  • the thicknesses of layers and regions are exaggerated for clarity.
  • the layer can be directly formed on the other layer or substrate, or a third layer can be positioned between the two.
  • a buffer layer, a spacer layer, a cap layer, or other layers can be further included, which is necessary to form semi ⁇ conductor devices. It should be understood that these are omitted for simplification of the drawings.
  • FIGS. 1 and 2A through 2E a method of fabricating semiconductor devices according to the present invention will be described.
  • a structure including an Al x Ga l-x As (0 ⁇ x ⁇ 1) epitaxial layer is formed.
  • the structure may be formed, for example, as shown in FIG. 2A. That is, an n-type DBR 110, an active layer 120 having a plurality of quantum wells, and a p-type DBR 130 are epitaxially grown.
  • the substrate 100 may be composed of material such as GaAs, InP, or the like, and the active layer 120 may be composed of, for example, GaAs.
  • the n-type DBR 110 and the p-type DBR 130 may each be composed of a multi-layer Al Ga As (0 ⁇ x ⁇ 1) epitaxial layer.
  • a mask pattern 140 is formed on the structure shown in
  • FIG. 2A (refer to FIG. 2B).
  • a photoresist pattern is preferably used as the mask pattern 140, because photoresist is resistant to acid, and is hardly consumed during etching. Therefore, pattern shapes such as circles, squares, or any other desired shape may be easily formed using aligner equipment. [34] In operation 30 of FIG. 1, using the mask pattern 140 as an etch mask, the Al Ga l-x
  • FIG. 3 is a diagram of a water bath apparatus 300 suitable for use as a wet etching apparatus.
  • a reference numeral '310' represents a wafer having a structure to be etched formed thereon
  • a reference numeral '320' represents a magnetic spin bar
  • a reference numeral '322' represents a thermometer
  • '324' represents a carrier
  • a reference numeral '330' represents etchant
  • a reference numeral '340' represents water. While performing wet-etching using the wet-etching apparatus 300, it is preferable to agitate using the magnetic spin bar 320.
  • the agitating speed may be varied depending on a size of the reservoir 332 in which the etchant 330 is held, but is preferably set so as not to cause a vortex swirl on the surface of the etchant, in order to provide reaction-limited etching characteristics, in which the etching speed depends on the reaction speed of the etchant.
  • the temperature of the etchant 330 is preferably maintained above 40 0 C, by maintaining the temperature of the water 340 above 40 0 C.
  • a mesa 200 having a bias close to anisotropic etching characteristics may be achieved. Furthermore, the desired shape of mesa along the upper surface of the mask pattern 140, for example, a circular mesa, can be easily formed.
  • the structure including the mesa 200 is cleaned using de- ionized water 150 (refer to FIG. 2D).
  • the cleaning needs to be performed for about 1 ⁇ 5 minutes, for example, 3 minutes.
  • the mask pattern 140 is removed, exposing the upper surface of the mesa 200 having vertical sidewalls, as shown in FIG. 2E.
  • FIG. 4 is a table illustrating a sample structure of an epitaxial layer to be etched in an exemplary experiment of the present invention. Further, the etching apparatus 300 shown in FIG. 3can be used to etch the epitaxial structure of FIG. 4.
  • Photoresist is deposited on an epitaxial layer to be etched after organic cleaning, thereby forming the desired shape of photoresist pattern.
  • Photoresist is suitable as an etch mask because it is durable to acid, and is not etched. Further, the photoresist layer can be easily patterned into various shapes such as circles, squares, or the like, using aligner equipment.
  • the mask pattern formed as above is hard-baked in an oven at 120 0 C for seven minutes. Then, oxygen plasma ashing is performed to remove residue on the mask pattern, thereby minimizing effects due to defects.
  • the defects of the sample surface adversely affect the structure to be etched locally during the etching process, reducing the uniformity of the etching.
  • the main elements affecting the etching are the thickness of the photoresist layer, and the time for hard baking the mask pattern. Preferably, the hard baking is performed for about 7 minutes. From the experiments by the inventors of the present invention, it has been found that the etchant permeates between the photoresist layer and the epitaxial layer if the hard baking is for less than 7 minutes, due to unstable adhesion of the photoresist layer, and the photoresist layer cannot be held for the time required for the etching process due to its lowered hardness.
  • the hard baking time is set too long, it is difficult to remove the photoresist after the etching process.
  • the etching is also affected by the etching selectivity, representing the ratio of the etch rates of the epitaxial layer and the photoresist layer by the etchant.
  • the ratio of phosphoric acid (H 3 PO 4 ) to the other components is high in order to increase the etch rate of Al, such that the etching selectivity of GaAs and AlGaAs is about 1.
  • Methanol (CH OH) is used as a diluent.
  • the reason that the methanol is used as a diluent instead of water is because the dielectric constant of methanol (about 27) is lower than the dielectric constant of water (about 81) at room temperature, thereby decreasing the dissociation of H O , and maintaining a uniform concentration of the etchant during the etching process.
  • the etchant shows reaction-limited etching characteristics, in which the etching speed depends on the reaction speed of the etchant, because the viscosity of the etchant is increased by the high volume ratio of H PO .
  • An epitaxial layer covered by the mask pattern formed by the method described in the (2) is etched using the etchant of the present invention, the mixture of H PO , H O , and CH OH in the wet etching apparatus 300 of FIG. 3.
  • the etchant is agitated using the magnetic spin bar 320 at 140 rpm.
  • the rotation speed of the magnetic spin bar 320 is varied with the size of the reservoir containing the etchant, but is set to maintain the interface between the etchant and the atmosphere substantially even, for consistent results.
  • the variation of etching characteristics with temperature is examined by changing the temperature of the water 340 to 21 0 C, 30 + 0.5 0 C, and 40 + 0.5 0 C. After the etching, the structure is sufficiently cleaned using de-ionized water for about 3 minutes, to completely remove the mask pattern.
  • FIGS. 5A through 5C the left photograph shows the shape of the sidewall of the mesa, and the right photograph shows the shape of the front surface of the mesa.
  • FIG. 5 A illustrates the shape and surface roughness of the mesa etched for 10 minutes using an etchant of the present invention at about 21 0 C.
  • the etching depth (H) measured from the upper surface of the mesa 18 of FIG. 4 is about 6.85 ⁇ m, showing isotropic etching characteristics. Also, it is found that a vertical mesa is formed down to about 1/3 the depth of the quantum well (about 1 ⁇ m). Further, with the generation of undercut shown in FIG. 5A, the etched shape in the crystalline direction [1 0 0] maintains the original circular shape identical to the initial pattern. As the volume ratio of H 3 PO 4 is high, residual material after etching may adhere to the surface of the epitaxial layer. The residual material can be sufficiently removed by cleaning using de-ionized water while checking the surface state by eye.
  • FIG. 5B illustrates the experiment results under the same processing conditions as those of FIG. 5 A except that the etching process was performed for 15 minutes after increasing the etchant temperature to 30 0 C, and the etching depth H is increased to about 11 ⁇ m. As a result, a vertical mesa is formed to about 2 ⁇ m. Spots shown on the surface of the mesa are photoresist material remaining on the mesa, which is dissolved by acetone while removing the photoresist mask pattern. In the etching process of forming the mesa, a cleaning operation such as removing and rinsing of the mask pattern also significantly affects the surface roughness of the mesa,as well as the main etching process conditions. Therefore, it is preferable to perform cleaning after the etching for about 3 minutes, with de-ionized water.
  • FIG. 5C illustrates the experiment results under the same processing conditions as those of FIG. 5A except that the temperature of the etchant was 40 0 C and the etching time was 20 minutes.
  • the shape of an epi mesa formed on a GaAs substrate can be found, and the epi mesa shows isotropic characteristics down to about 25 ⁇ m in depth.
  • thehorizontal etch rate to thevertical etch rate is about 0.24 (2.1 ⁇ m/ 8.68 ⁇ m), thereby providing a vertical sidewall close to anisotropic charac ⁇ teristics.
  • the horizontal etch rate to the vertical etch rate is about 0.12 (0.39 ⁇ m/ 3.21 ⁇ m). If it is considered that the horizontal etch rate to the vertical etch rate is typically about 1 in most wet etching, more vertical mesa sidewalls can be achieved in comparison with isotropic etching.
  • the shape of the lateral surface of the resultant structure is illustrated in FIG. 6A, and the shape of the upper surface of the mesa is shown in FIG. 6B.
  • FIGS. 7A through 7F are AFM (atomic force microscopy) photographs illustrating changes in surface roughness of a substrate in accordance with visual conditions when etching an epitaxial layer by various etching processes.
  • FIG. 7A depicts a mesa etched by a typical dry etching process using chemically assisted ion beam etching (CAIBE).
  • the surface roughness (rms) of FIG. 7A is 0.733nm.
  • FIGS. 7B through 7F illustrate the surface roughness of the substrate formed by wet-etching using an etchant of the present invention, in which temperatures of the etchant are respectively 20 0 C, 25°C, 30 0 C, 35°C, and 40 0 C.
  • the surface roughness of the substrate is improved as the temperature of the etchant is increased.
  • the roughness of the lateral surface of the mesa after etching cannot be directly found by AFM analysis, but it is estimated that it is also improved like the case of the substrate, since the etch selectivity of the GaAs layer and AlGaAs layer is close to 1 when using the etchant including a mixture of H PO , H O , and CH OH of the etchant.
  • the surface roughness (rms) in FIGS. 7B through 7F are re ⁇ spectively 4.690nm, 0.917nm, 0.903nm, 0.825nm and 0.703nm.
  • the above results show that when etching the mesa using the etchant of the present invention, surface roughness can be decreased by increasing the temperature of the etchant. However, its dependence on the temperature decreases above 25°C. If the temperature of the etchant is 40 0 C, the surface roughness is similar to that of the dry etching using CAIBE of FIG. 7A. In comparison of FIG. 7F with FIG. 7A, wet etching using the etchant of the present invention gives the more uniform surface.
  • the etchant of the present invention includes a mixture of H PO , H O , and CH r 3 4 2 2 3
  • An Al Ga As (0 ⁇ x ⁇ 1) epitaxial layer is etched using the etchant of the present invention, thereby forming a mesa having a vertical sidewall profile due to the isotropic etching characteristics.
  • the sidewall of the mesa has a smooth surface, since the etch selectivity of the GaAs layer and the AlGaAs layer is close to 1.
  • the mesa may have the desired shape in accordance with the shape of the mask pattern, for example, a circular mesa. Therefore, according to the present invention, a large array of vertical mesa can be fabricated more cheaply than with dry etching.
  • the present invention may be effectively employed in fabricating a heterojunction bipolar transistor (HBT), a high electron mobility transistor (HEMT), a semiconductor laser, or other devices.
  • HBT heterojunction bipolar transistor
  • HEMT high electron mobility transistor
  • semiconductor laser or other devices.

Abstract

Provided are an etchant for etching an Alx Ga1-x As epitaxial layer and a method of fabricating semiconductor devices using the same. The etchant includes a mixture of H3 PO4 , H2O2, and CH3OH. Using the etchant, an Alx Ga1-x As (O < x < 1) epitaxial layer is etched, thereby providing isotropic etching characteristics and forming a mesa with vertical sidewalls. Since the etch selectivity of the GaAs layer and the AlGaAs layer is close to 1, the sidewalls of the mesa are smooth.

Description

Description
ETCHANT FOR WET ETCHING AlXGaI-XAs EPITAXIAL LAYER AND METHOD FOR MANUFACTURING SEMI¬ CONDUCTOR DEVICE USING THE ETCHANT
Technical Field
[1] The present invention relates to an etchant for etching an epitaxial layer and a method of manufacturing semiconductor devices using the same, and more par¬ ticularly, to an etchant for wet etching an Al Ga As epitaxial layer and a method of
X. 1-X. manufacturing semiconductor devices including an operation of forming a mesa using the etchant, in which the semiconductor devices may be optical switch devices or unit elements using a laser.
Background Art
[2] A wet etching process using a chemical reaction is widely used to manufacture devices such as heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), and semiconductor lasers. Previous wet etching processeshave usually used selective etching characteristics, limiting their use to situations where a vertical mesa sidewall (hereinafter, referred to as a 'vertical mesa') does not adversely affect the device characteristics.
[3] Dry etching is an essential process in the fabrication of devices, including a vertical mesa. Etching a vertical sidewall using dry etching is an already known technology. For example, it can be found in Mats Hagberg et al., J. Vac. Sci. Technol. B 12(2), Mar/Apr 1994, and Jun-youn Kim et al., J. Vac. Sci. Technol. B 19(4), Jul/Aug 2001. As shown in these publications, the dry etching process andits related equipmentare expensive, andthe time taken to developthenecessary high vacuum lengthens the overall process time.
[4] Therefore, methods using the wet etching process are studied to solve the problems of the dry etching process. The wet etching process has characteristics such as isotropic etching, low aspect ratio, and undercut, unlike the dry etching process.
[5] The manufacture of semiconductor devices such as semiconductor optical switch
(SOS) devices or photonic quantum ring (PQR) laser unit devices includes forming a multi-layer structured semiconductor layer having a plurality of GaAs/ AlGaAs epitaxial layers, and mesa-etching them. Particularly, in the manufacture of PQR laser unit device including a multi-layer structured p-type distributed bragg reflector (DBR) and n-type DBR, consisting of GaAs/ AlGaAs epitaxial layers, and a GaAs active layer between the above DBRs, the fabrication includes the processes of etching the multi¬ layer structured semiconductor layer consisting of GaAs/ AlGaAs epitaxial layers and forming a mesa having a vertical and smooth sidewall down to the active layer. Disclosure of Invention
Technical Problem
[6] However, such a mesais difficult to form by wet etching the multi-layer structured epitaxial layer including GaAs and AlGaAs layers. Further, it is hard to form a mesa having the desired pattern shape, since the etching rate varies with every layer in accordance with the epi directions of the multi-layer structured semiconductor layers.
[7] Up to now, efforts have focused on providing a vertical mesa using a wet etching process (refer to J. Y. Lee et. al., Vac. Sci. Technol. B 17(6), Dec/1999). However, wet etching has not yet successfully been used to create a multi-layer structured epitaxial layer with the desired pattern shape, due to the different etch rates according to epi direction. Furthermore, the extended time for wet etching leaves the patterns with arough surface, and the mesa is not sufficiently vertical around an active region. As a result, the formation of the mesa using wet etching has not yet provided devices with desired characteristics.
Technical Solution
[8] The present invention provides an etchant for etching an Al Ga As epitaxial layer to provide a vertical mesa by etching a multi-layer structured epitaxial layer using a wet etching process with lower production expenses than a dry etching process.
[9] The present invention also provides a method of fabricating semiconductor devices for providing a desired patternshape and a mesa with a vertical and smooth sidewalls through etching an Al x Ga 1-x As epitaxial layer using the etchant.
[10] According to an aspect of the present invention, there is provided an etchant for etching an Al Ga As (0 < x < 1) epitaxial layer, including a mixture of H PO , H O , and CH OH. The mixture may have a H PO : H O : CH OH volume ratio of 3: 1: 1.
3 3 4 2 2 3
Further, the temperature of the mixture is at least 40 0C.
[11] According to another aspect of the present invention, there is provided a method of manufacturing semiconductor devices including forming a structure including an Al
Ga l-x As (0 < x < 1) epitaxial layer. A mask pattern is formed on the structure. The Al x
Ga l-x As e rpitaxial lay Jer is etched by J a mixture of H 3 PO 4 , H 2O 2, and CH 3 OH using & the mask pattern as an etch mask, thereby forming a mesa. [12] The etching of the Al Ga As epitaxial layer may be performed by agitating the x l-x mixture. The etching of the Al x Ga l-x As epitaxial layer may be performed using a water bath apparatus.
[13] The mask pattern may be composed of photoresist.
[14] After etching the Al Ga As epitaxial layer, the method may further include cleaning the mesa using de-ionized water. The cleaning may be performed for 1-5 minutes.
Advantageous Effects
[15] According to the present invention, an Al Ga As (0 <x < 1) epitaxial layer is wet x 1-x etched using the etchant, which is composed of a mixture of H 3 PO 4 , H 2O 2, and CH 3 OH, thereby providing isotropic etching characteristics and forming a mesa with vertical sidewalls. Further, the mesa can be provided with a smooth surface on its sidewalls, since the etch selectivity of the GaAs layer and the AlGaAs layer is close to 1. Further, the mesa can have a desired shape in accordance with the shape of the mask pattern, for example, a circular shape. Therefore, according to the present invention, a large array of vertical mesa can be fabricated much more cheaply than with dry etching.
Description of Drawings
[16] FIG. 1 is a flow chart illustrating a method of fabricating semiconductor devices according to an embodiment of the present invention;
[17] FIGS. 2A through 2E are sectional views illustrating processing sequences of the method of fabricating semiconductor devices of FIG. 1 according to an embodiment of the present invention;
[18] FIG. 3 is a diagram of a water bath apparatus suitable for use as a wet-etching apparatus in the fabrication of semiconductor devices according to the present invention;
[19] FIG. 4 is a table illustrating a sample structure of an epitaxial layer to be etched in an exemplary experiment of the present invention;
[20] FIGS. 5 A through 5C are photographs illustrating the lateral and upper surfaces of a mesa formed through a wet-etching process using an etchant of the present invention;
[21] FIGS. 6 A and 6B are photographs illustrating the lateral and upper surfaces of a mesa formed through a wet-etching process using aconventional etchant;
[22] FIG. 7A is a photograph illustrating surface roughness of a substrate in a mesa formed through a conventional dry-etching process; and
[23] FIGS. 7B through 7F are photographs illustrating surface roughness of a substrate in accordance with the temperature of an etchant when a mesa is formed by a method of fabricating semiconductor devices according to the present invention.
Best Mode
[24] The present invention will now be described more fully with reference to the ac¬ companying drawings
[25] An etchant of the present invention includes a mixture of H PO , H O , and CH OH.
^ 3 4 2 2 3
[26] Preferably, the volume ratio of the mixture components is H PO : H O : CH OH =
3: 1: 1. [27] The etchant of the present invention is particularly effective for etching a multi- layer structure of an Al Ga As (0 <x < 1) epitaxial layer. The multi-layer structure of an Al x Ga 1-x As (0 <x < 1) epitaxial layer is etched using the etchant of the present invention, thereby forming a vertical mesa having a bias of about 0.88 [1 -(horizontal etch rate/vertical etch rate)], which is close to anisotropic etching characteristics. Further, it is possible to form the desired shape of mesa, for example a circular mesa. [28] In the formation of a vertical mesa by etching the multi-layer structure of the Al Ga
As (0 <x < 1) epitaxial layer using the etchant of the present invention, it is found l-x that surface roughness of the mesa can be improved as the temperature of the etchant is increased. Preferably, the etchant is maintained at at least 40 0C during etching. [29] Using a mask pattern, for example, a photoresist pattern, as an etch mask and using the etchant of the present invention, etching is performed on the multi-layer structure of the Al x Ga l-x As (0 <x < 1) epitaxial layer to form an active layer having GaAs quantum wells, between a p-type DBR and an n-type DBR, thereby forming a circular mesa having a vertical sidewalls.
[30] FIG. 1 is a flow chart illustrating a method of fabricating semiconductor devices according to an embodiment of the present invention. FIGS. 2A through 2E are sectional views illustrating processing sequences of the method of fabricating semi¬ conductor devices of FIG. 1 according to an embodiment of the present invention. In FIGS. 2A through 2E, the thicknesses of layers and regions are exaggerated for clarity. In addition, when it is described that one layer is positioned 'on' another layer or substrate, the layer can be directly formed on the other layer or substrate, or a third layer can be positioned between the two. For example, a buffer layer, a spacer layer, a cap layer, or other layers can be further included, which is necessary to form semi¬ conductor devices. It should be understood that these are omitted for simplification of the drawings.
[31] Referring to FIGS. 1 and 2A through 2E, a method of fabricating semiconductor devices according to the present invention will be described.
[32] In operation 10 of FIG. 1, a structure including an Al x Ga l-x As (0 <x < 1) epitaxial layer is formed. The structure may be formed, for example, as shown in FIG. 2A. That is, an n-type DBR 110, an active layer 120 having a plurality of quantum wells, and a p-type DBR 130 are epitaxially grown. The substrate 100 may be composed of material such as GaAs, InP, or the like, and the active layer 120 may be composed of, for example, GaAs. The n-type DBR 110 and the p-type DBR 130 may each be composed of a multi-layer Al Ga As (0 <x < 1) epitaxial layer. x l-x
[33] In operation 20 of FIG. 1, a mask pattern 140 is formed on the structure shown in
FIG. 2A (refer to FIG. 2B). A photoresist pattern is preferably used as the mask pattern 140, because photoresist is resistant to acid, and is hardly consumed during etching. Therefore, pattern shapes such as circles, squares, or any other desired shape may be easily formed using aligner equipment. [34] In operation 30 of FIG. 1, using the mask pattern 140 as an etch mask, the Al Ga l-x
As epitaxial layer is wet etched using an etchant including a mixture of H PO , H O , and CH OH, thereby forming a mesa 200. In this operation, it is important to provide a stable etching environment, controlling factors such as temperature and agitation, to ensure reproducible results. [35] The volume ratio of the etchant mixture is H PO : H O : CH OH = 3: 1: 1.
3 4 2 2 3
[36] FIG. 3 is a diagram of a water bath apparatus 300 suitable for use as a wet etching apparatus. In FIG. 3, a reference numeral '310' represents a wafer having a structure to be etched formed thereon, a reference numeral '320' represents a magnetic spin bar, a reference numeral '322' represents a thermometer, '324' represents a carrier,a reference numeral '330' represents etchant, and a reference numeral '340' represents water. While performing wet-etching using the wet-etching apparatus 300, it is preferable to agitate using the magnetic spin bar 320. At this time, the agitating speed may be varied depending on a size of the reservoir 332 in which the etchant 330 is held, but is preferably set so as not to cause a vortex swirl on the surface of the etchant, in order to provide reaction-limited etching characteristics, in which the etching speed depends on the reaction speed of the etchant. The temperature of the etchant 330 is preferably maintained above 400C, by maintaining the temperature of the water 340 above 400C.
[37] Performing an etching process as above, a mesa 200 having a bias close to anisotropic etching characteristics may be achieved. Furthermore, the desired shape of mesa along the upper surface of the mask pattern 140, for example, a circular mesa, can be easily formed.
[38] In operation 40 of FIG. 1, the structure including the mesa 200 is cleaned using de- ionized water 150 (refer to FIG. 2D). The cleaning needs to be performed for about 1 ~ 5 minutes, for example, 3 minutes.
[39] In operation 50 of FIG. 1, the mask pattern 140 is removed, exposing the upper surface of the mesa 200 having vertical sidewalls, as shown in FIG. 2E.
Mode for Invention
[40] A description follows of specific exemplary experiments of forming a mesa by etching an epitaxial structure according to the method of fabricating semiconductor devices of the present invention.
[41] Example 1
[42] (I) Structure of an epitaxial layer to be etched and experiment apparatus
[43] A stable etching environment, such as temperature, agitating speed, and the like, is important to reproducibly wet etch a structure including an active layer having GaAs quantum wells, and a plurality of epitaxial layers, which is composed of GaAs and AlGaAs, to form a p-type DBR and an n-type DBR. [44] FIG. 4 is a table illustrating a sample structure of an epitaxial layer to be etched in an exemplary experiment of the present invention. Further, the etching apparatus 300 shown in FIG. 3can be used to etch the epitaxial structure of FIG. 4.
[45] (2) Formation of a mask pattern as etch mask
[46] Photoresist is deposited on an epitaxial layer to be etched after organic cleaning, thereby forming the desired shape of photoresist pattern. Photoresist is suitable as an etch mask because it is durable to acid, and is not etched. Further, the photoresist layer can be easily patterned into various shapes such as circles, squares, or the like, using aligner equipment. The mask pattern formed as above is hard-baked in an oven at 1200C for seven minutes. Then, oxygen plasma ashing is performed to remove residue on the mask pattern, thereby minimizing effects due to defects.
[47] The defects of the sample surface adversely affect the structure to be etched locally during the etching process, reducing the uniformity of the etching. The main elements affecting the etching are the thickness of the photoresist layer, and the time for hard baking the mask pattern. Preferably, the hard baking is performed for about 7 minutes. From the experiments by the inventors of the present invention, it has been found that the etchant permeates between the photoresist layer and the epitaxial layer if the hard baking is for less than 7 minutes, due to unstable adhesion of the photoresist layer, and the photoresist layer cannot be held for the time required for the etching process due to its lowered hardness. Further, if the hard baking time is set too long, it is difficult to remove the photoresist after the etching process. The etching is also affected by the etching selectivity, representing the ratio of the etch rates of the epitaxial layer and the photoresist layer by the etchant.
[48] (3) Etching using etchant of the present invention
[49] A sample of the epitaxial layer is etched using an etchant of the present invention, in which the volume ratio of the etchant mixture is H PO (purity 85%): H O (purity 30%): CH 3 OH = 3: 1: 1. In this mixture, the ratio of phosphoric acid (H 3 PO 4 ) to the other components is high in order to increase the etch rate of Al, such that the etching selectivity of GaAs and AlGaAs is about 1. Methanol (CH OH) is used as a diluent. The reason that the methanol is used as a diluent instead of water is because the dielectric constant of methanol (about 27) is lower than the dielectric constant of water (about 81) at room temperature, thereby decreasing the dissociation of H O , and maintaining a uniform concentration of the etchant during the etching process. However, the etchant shows reaction-limited etching characteristics, in which the etching speed depends on the reaction speed of the etchant, because the viscosity of the etchant is increased by the high volume ratio of H PO . An epitaxial layer covered by the mask pattern formed by the method described in the (2) is etched using the etchant of the present invention, the mixture of H PO , H O , and CH OH in the wet etching apparatus 300 of FIG. 3. The etchant is agitated using the magnetic spin bar 320 at 140 rpm. The rotation speed of the magnetic spin bar 320 is varied with the size of the reservoir containing the etchant, but is set to maintain the interface between the etchant and the atmosphere substantially even, for consistent results. Further, the variation of etching characteristics with temperature is examined by changing the temperature of the water 340 to 210C, 30 + 0.50C, and 40 + 0.50C. After the etching, the structure is sufficiently cleaned using de-ionized water for about 3 minutes, to completely remove the mask pattern.
[50] The shapes of mesa at various temperatures and etching times are shown in FIGS.
5A through 5C. In FIGS. 5A through 5C, the left photograph shows the shape of the sidewall of the mesa, and the right photograph shows the shape of the front surface of the mesa.
[51] More particularly, FIG. 5 A illustrates the shape and surface roughness of the mesa etched for 10 minutes using an etchant of the present invention at about 210C. The etching depth (H) measured from the upper surface of the mesa 18 of FIG. 4 is about 6.85 μm, showing isotropic etching characteristics. Also, it is found that a vertical mesa is formed down to about 1/3 the depth of the quantum well (about 1 μm). Further, with the generation of undercut shown in FIG. 5A, the etched shape in the crystalline direction [1 0 0] maintains the original circular shape identical to the initial pattern. As the volume ratio of H 3 PO 4 is high, residual material after etching may adhere to the surface of the epitaxial layer. The residual material can be sufficiently removed by cleaning using de-ionized water while checking the surface state by eye.
[52] FIG. 5B illustrates the experiment results under the same processing conditions as those of FIG. 5 A except that the etching process was performed for 15 minutes after increasing the etchant temperature to 300C, and the etching depth H is increased to about 11 μm. As a result, a vertical mesa is formed to about 2 μm. Spots shown on the surface of the mesa are photoresist material remaining on the mesa, which is dissolved by acetone while removing the photoresist mask pattern. In the etching process of forming the mesa, a cleaning operation such as removing and rinsing of the mask pattern also significantly affects the surface roughness of the mesa,as well as the main etching process conditions. Therefore, it is preferable to perform cleaning after the etching for about 3 minutes, with de-ionized water.
[53] FIG. 5C illustrates the experiment results under the same processing conditions as those of FIG. 5A except that the temperature of the etchant was 400C and the etching time was 20 minutes. The shape of an epi mesa formed on a GaAs substrate can be found, and the epi mesa shows isotropic characteristics down to about 25 μm in depth. However, in consideration of the structure of an epitaxial layer including p-type DBR - active region - n-type DBR, thehorizontal etch rate to thevertical etch rate is about 0.24 (2.1 μm/ 8.68 μm), thereby providing a vertical sidewall close to anisotropic charac¬ teristics. Further, in consideration of an etch depth down to about 3 μm, the horizontal etch rate to the vertical etch rate is about 0.12 (0.39 μm/ 3.21 μm). If it is considered that the horizontal etch rate to the vertical etch rate is typically about 1 in most wet etching, more vertical mesa sidewalls can be achieved in comparison with isotropic etching.
[54] Comparative Example
[55] Etching is performed on a mesa for 7 minutes under the same etching conditions as those of FIG. 5B, except that the etchant is a mixture of H 3 PO 4 , H 2O 2, and H 2 O, and the etchant has a volume ratio of H 3 PO 4 : H 2O 2 : H 2O =1: 1: 10. The shape of the lateral surface of the resultant structure is illustrated in FIG. 6A, and the shape of the upper surface of the mesa is shown in FIG. 6B.
[56] As shown in FIGS. 6A and 6B, since a GaAs layer active region is etched faster due to the difference in etch rates of a GaAs epitaxial layer and a AlGaAs epitaxial layer, the region is recessed, and the profile of the sidewall is not vertical. Further, it is difficult to achieve the same circular shape as the shape of the mask pattern on the upper surface of the mesa, since the etching rates vary with the epi direction as shown in FIG. 6B. The result is a typical result achieved by isotropic wet etching in the con¬ ventional technology.
[57] FIGS. 7A through 7F are AFM (atomic force microscopy) photographs illustrating changes in surface roughness of a substrate in accordance with visual conditions when etching an epitaxial layer by various etching processes.
[58] More specifically, FIG. 7A depicts a mesa etched by a typical dry etching process using chemically assisted ion beam etching (CAIBE). The surface roughness (rms) of FIG. 7A is 0.733nm.
[59] FIGS. 7B through 7F illustrate the surface roughness of the substrate formed by wet-etching using an etchant of the present invention, in which temperatures of the etchant are respectively 200C, 25°C, 300C, 35°C, and 400C. In FIGS. 7B through 7F, the surface roughness of the substrate is improved as the temperature of the etchant is increased. The roughness of the lateral surface of the mesa after etching cannot be directly found by AFM analysis, but it is estimated that it is also improved like the case of the substrate, since the etch selectivity of the GaAs layer and AlGaAs layer is close to 1 when using the etchant including a mixture of H PO , H O , and CH OH of the
& & 3 4 2 2 3 present invention. The surface roughness (rms) in FIGS. 7B through 7F are re¬ spectively 4.690nm, 0.917nm, 0.903nm, 0.825nm and 0.703nm.
[60] The above results show that when etching the mesa using the etchant of the present invention, surface roughness can be decreased by increasing the temperature of the etchant. However, its dependence on the temperature decreases above 25°C. If the temperature of the etchant is 400C, the surface roughness is similar to that of the dry etching using CAIBE of FIG. 7A. In comparison of FIG. 7F with FIG. 7A, wet etching using the etchant of the present invention gives the more uniform surface. [61] The etchant of the present invention includes a mixture of H PO , H O , and CH r 3 4 2 2 3
OH. An Al Ga As (0 <x < 1) epitaxial layer is etched using the etchant of the present invention, thereby forming a mesa having a vertical sidewall profile due to the isotropic etching characteristics. The sidewall of the mesa has a smooth surface, since the etch selectivity of the GaAs layer and the AlGaAs layer is close to 1. Further, the mesa may have the desired shape in accordance with the shape of the mask pattern, for example, a circular mesa. Therefore, according to the present invention, a large array of vertical mesa can be fabricated more cheaply than with dry etching.
[62] While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.
Industrial Applicability
[63] The present invention may be effectively employed in fabricating a heterojunction bipolar transistor (HBT), a high electron mobility transistor (HEMT), a semiconductor laser, or other devices.

Claims

Claims
[I] An etchant for etching an Al Ga As (0 < x < 1) epitaxial layer comprising a mixture of H 3 PO 4 , H 2 O 2 , and CH 3 OH.
[2] The etchant for etching an Al Ga As epitaxial layer of claim 1, wherein the mixture has a H 3 PO 4 : H 2 O 2 : CH 3 OH volume ratio of 3: 1: 1.
[3] The etchant for etching an Al Ga As epitaxial layer of claim 1, wherein the x 1-x temperature of the mixture is at least 40 0C.
[4] A method of manufacturing semiconductor devices comprising: forming a structure including an Al x Ga 1-x As (0 < x < 1) epitaxial layer; forming a mask pattern on the structure; and etching the Al x Ga 1-x As epitaxial layer with a mixture of H 3 PO 4 , H 2O 2, and CH 3
OH, using the mask pattern as an etch mask, to form a mesa.
[5] The method of claim 4, wherein the mixture has a H 3 PO 4 : H 2 O 2 : CH 3 OH volume ratio of 3: 1: 1.
[6] The method of claim 4, wherein the etching of the Al Ga As epitaxial layer is x 1-x performed with the mixture at a temperature of at least 40 0C.
[7] The method of claim 4, wherein the etching of the Al Ga As epitaxial layer is x 1-x performed while agitating the mixture.
[8] The method of claim 4, wherein the etching of the Al Ga As epitaxial layer is x 1-x performed using a water bath apparatus.
[9] The method of claim 4, wherein the mask pattern is composed of photoresist.
[10] The method of claim 4, further comprising cleaning the mesa using de-ionized water, after etching the Al Ga As epitaxial layer. x 1-x
[I I] The method of claim 10, wherein the cleaning is performed for 1-5 minutes. [12] The method of claim 4, wherein the mesa has a substantially circular upper surface.
PCT/KR2005/000836 2004-03-23 2005-03-23 ETCHANT FOR WET ETCHING AlXGaI-XAs EPITAXIAL LAYER AND METHOD FOR MANUFACTURING SEMI¬ CONDUCTOR DEVICE USING THE ETCHANT WO2006004255A1 (en)

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CN111106007A (en) * 2019-12-04 2020-05-05 福建省福联集成电路有限公司 Semiconductor table top and etching method

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CN111106007B (en) * 2019-12-04 2022-06-10 福建省福联集成电路有限公司 Semiconductor table top and etching method

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