WO2006003844A1 - Semiconductor device, method for fabricating the same and electronic apparatus - Google Patents

Semiconductor device, method for fabricating the same and electronic apparatus Download PDF

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Publication number
WO2006003844A1
WO2006003844A1 PCT/JP2005/011605 JP2005011605W WO2006003844A1 WO 2006003844 A1 WO2006003844 A1 WO 2006003844A1 JP 2005011605 W JP2005011605 W JP 2005011605W WO 2006003844 A1 WO2006003844 A1 WO 2006003844A1
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WIPO (PCT)
Prior art keywords
semiconductor device
manufacturing
source
conductive material
thin film
Prior art date
Application number
PCT/JP2005/011605
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French (fr)
Japanese (ja)
Inventor
Katsura Hirai
Original Assignee
Konica Minolta Holdings, Inc.
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Publication date
Application filed by Konica Minolta Holdings, Inc. filed Critical Konica Minolta Holdings, Inc.
Priority to JP2006528615A priority Critical patent/JP4946438B2/en
Publication of WO2006003844A1 publication Critical patent/WO2006003844A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1292—Multistep manufacturing methods using liquid deposition, e.g. printing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/60—Forming conductive regions or layers, e.g. electrodes
    • H10K71/611—Forming conductive regions or layers, e.g. electrodes using printing deposition, e.g. ink jet printing

Definitions

  • the present invention relates to a semiconductor device, a manufacturing method thereof, and an electronic device.
  • an IC card As an example of an IC card, a radio wave (electromagnetic wave) that also generates a coil force of a reader / writer device is received by a coil on the IC card side, and power, a clock, and a transmission / reception signal are generated, and a command received from the reader / writer device is received.
  • An RFID (Radio Frequency Identification) type IC card hereinafter referred to as an RFID card) to be processed has been proposed (for example, Patent Document 2).
  • FIG. 13 is a block diagram showing an electrical configuration of a conventional RFID card.
  • the RFID card 10 rectifies the received AC signal connected to the coil 12 and converts it into a DC voltage, and drives the circuit of the RFID card 10 based on the DC voltage converted by the rectifier circuit 13.
  • a power supply circuit 14 that generates the required power supply voltage VDD, a demodulation circuit 15 that extracts (demodulates) received information contained in an AC signal supplied from the outside via the coil 12, and an AC signal that includes transmission information are formed.
  • the memory circuit 18 Based on the received information demodulated by the modulation circuit 16 that modulates and drives the coil 12, the memory circuit 18 that stores identification information for identifying the RFID card 10 and the demodulation circuit 15, the data is stored in the memory circuit 18.
  • Read / write control circuit 17 that performs processing such as writing transmission data and outputting transmission information read from memory circuit 18 to modulation circuit 16 and protocol control for transmission and reception with an external reader / writer (not shown). It is more structured etc..
  • the AC signal received by the coil 12 is input to the demodulation circuit 15, where it is demodulated from the ASK modulated (amplitude modulated) signal, and the data signal is reproduced.
  • the reproduced data is written into the memory circuit 18 by the read / write control circuit 17 that performs read / write control of the memory circuit 18 and transmission / reception protocol control.
  • transmission from the RFID card to the reader / writer Data is read from the memory circuit 18 by the read / write control circuit 17, LSK (load modulation) is performed on the coil signal by the modulation circuit 16, and the data is transmitted.
  • the RFID card 10 as an electronic device needs to hold an ID code in order to identify each other during the exchange of data with the reader / writer.
  • the memory circuit 18 that holds the ID code, it is common to use an electrically writable / erasable nonvolatile memory such as EEPROM (Electrically Erasable Programmable Read Only Memory) (for example, Patent Document 2).
  • EEPROM Electrically Erasable Programmable Read Only Memory
  • Patent Document 2 EEPROM (Electrically Erasable Programmable Read Only Memory)
  • Patent Document 1 JP-A-2-13046
  • Patent Document 2 Japanese Patent Laid-Open No. 2000-172806
  • Patent Document 3 Japanese Patent Laid-Open No. 2002-344113
  • the EEPROM of Patent Document 2 can be written with an ID code or a production number while being incorporated in an electronic device.
  • an invalid ID code or serial number is written.
  • a portable device such as an IC tag or a mobile phone
  • information is written via radio waves, so there is a risk that the contents of the EEPROM can be rewritten relatively easily.
  • an ID code and a manufacturing number can be written in a state of being incorporated in an electronic device.
  • An object of the present invention is to provide a semiconductor device that can be rewritten and difficult to rewrite, and a manufacturing method thereof.
  • the present inventor has found that the object of the present invention can be achieved by adopting one of the following configurations.
  • a plurality of thin film transistors each including a gate electrode, a gate insulating layer, and a source electrode and a drain electrode connected by a semiconductor layer on a substrate, and a gate line connecting the plurality of gate electrodes.
  • a semiconductor device having a thin film transistor array having a source line connecting the source electrode and a bit line connecting the drain electrode, the connection between the source electrode and the source line, and the drain electrode and the A semiconductor device having a separation portion in which at least one of the connections to the bit line is separated and can be connected with a conductive material.
  • a plurality of thin film transistors each including a gate electrode, a gate insulating layer, and a source electrode and a drain electrode connected by a semiconductor layer, and a gate line connecting the plurality of gate electrodes
  • a method for manufacturing a semiconductor device comprising: a connection step of connecting a separation portion between the drain electrode and the bit line, which has been previously separated based on the wiring pattern input in step 1, with a conductive material.
  • connection process is based on the wiring pattern input in the input process.
  • connection step the insulating portion to be insulated is insulated with a fluid insulating material based on the wiring pattern input in the input step, and then the other separating portion is connected with a conductive material.
  • the storage means is a semiconductor manufactured by the manufacturing method according to (1) above in (1).
  • FIG. 1 is a partial circuit diagram of a TFT array according to the present invention.
  • FIG. 2 (a) is a plan view of the TFT shown in FIG. 1, and FIG. 2 (b) is a cross-sectional view taken along the line AA in FIG. 2 (a).
  • FIG. 2 (c) is a cross-sectional view showing a state in which the source separation portion is filled with a conductive material in FIG. 2 (b).
  • FIG. 3 is a partial circuit diagram of a TFT array according to another embodiment of the present invention.
  • FIG. 4 (a) is a plan view of the TFT shown in FIG. 3, and FIG. 4 (b) is a cross-sectional view taken along the line BB in FIG. 4 (a).
  • FIG. 4 (c) is a cross-sectional view showing a state where the drain isolation portion is filled with the conductive material in FIG. 4 (b).
  • FIG. 5 is a schematic view showing an outline of a manufacturing process of a semiconductor device according to the present invention.
  • FIG. 6 is a state transition diagram of a TFT in the manufacturing process of the semiconductor device according to the invention.
  • FIG. 7 is a schematic view showing a pattern of separation part connection by an ink jet method.
  • FIG. 8 is a schematic diagram showing an outline of a manufacturing process of a semiconductor device according to another embodiment of the present invention.
  • FIG. 9 is a state transition diagram of a TFT in a manufacturing process of a semiconductor device according to another embodiment of the present invention.
  • FIG. 10 is a block diagram of a TFTROM.
  • FIG. 11 is a block diagram showing an electrical configuration of an RFID card equipped with a TFTROM.
  • FIG. 12 is an external perspective view of an RFID card equipped with a TFTROM.
  • FIG. 13 is a block diagram showing an electrical configuration of a conventional RFID card.
  • FIG. 1 shows a thin film transistor (hereinafter referred to as TFT) array which is a semiconductor device according to the present invention.
  • FIG. 6 is a partial circuit diagram of FIG.
  • the TFT array 66 includes a TFT 20, a source line 22, and a source separation unit 2 arranged in a matrix.
  • the TFT 20 is a field effect transistor, and includes a source electrode 21, a gate electrode 24, and a drain electrode 26.
  • the source line 22 is a bus provided so that the source electrodes 21 of the TFTs 20 arranged in the Y direction in the figure can be connected to each other. At least one source line 22 is provided for each column of the TFTs 20 arranged in the X direction. It is installed.
  • the source separation unit 23 which is the separation unit of the present invention, includes a source electrode 21 and a source line 2 of each TFT 20.
  • the source electrode 21 and the source line 22 are electrically separated, and can be connected with a conductive material by a method described later.
  • the gate line 25 is a bus that connects the gate electrodes 24 of the TFTs 20 arranged in the X direction in the figure, and at least one gate line 25 is provided for each row of the TFTs 20 arranged in the Y direction! /
  • FIG. 2 is a structural diagram of the TFT 20 shown in FIG. 1 and its peripheral part.
  • Fig. 2 (a) is a plan view of the TFT 20 and its peripheral part
  • Fig. 2 (b) is a cross-sectional view taken along the AA line in Fig. 2 (a).
  • FIG. 2 (c) shows a state where the conductive material 32 is filled in the source separator 23 in FIG. 2 (b).
  • the same symbols are assigned to the same elements as those described above in order to avoid duplication of explanation.
  • the TFT 20 has a gate line 25 connected to a gate electrode (not shown) on a base material 35 that is an insulating material, and an insulating layer 34 formed thereon, and further a semiconductor 31 and a bit line 27 formed thereon.
  • the source electrode 21 and the source line 22 are stacked, and are covered with an insulating layer 33 except for the source separation portion 23.
  • the semiconductor 31 is connected to the bit line 27 and the source electrode 21 provided at a constant interval.
  • the surface where the semiconductor 31 and the bit line 27 are connected corresponds to the drain electrode 26 shown in FIG.
  • the source electrode 21 and the source line 22 are formed so that a source separation portion 23 whose upper surface is opened up to the insulating layer 34 is formed. It is provided.
  • the source separator 23 is selectively filled in accordance with a desired wiring pattern with the conductive material 32 supplied from the opened upper cover, and is electrically connected. Is done.
  • the conductive material 32 any material may be used as long as it includes a conductive material.
  • a conductive polymer described later, a conductive paste containing metal fine particles, An ink or a metal thin film precursor material can be suitably used.
  • Materials for the metal fine particles include platinum, gold, silver, nickel, chromium, copper, iron, tin, antimony lead, tantalum, indium, palladium, tellurium, rhenium, iridium, aluminum, ruthenium, germanium, Molybdenum, tungsten, zinc, or the like can be used.
  • the solvent or dispersion medium is preferably a solvent or dispersion medium containing 60% or more, preferably 90% or more of water in order to suppress damage to the organic semiconductor.
  • conductive polymer dispersions whose conductivity has been improved by doping or the like, such as conductive polyarine, conductive polypyrrole, conductive polythiophene, polyethylene dioxythiophene and polysulfonic acid complex, etc. are also preferably used.
  • a ⁇ -conjugated material is used as the semiconductor 31 material.
  • polypyrrole such as polypyrrole, poly ( ⁇ -substituted pyrrole), poly (3-substituted pyrrole), and poly (3,4-disubstituted pyrrole).
  • Polythiophene poly (3-substituted thiophene), poly (3,4-disubstituted thiophene), polybenzones such as polybenzothiophene, polyisothianaphthenes such as polyisothianaphthene, and polychelenylene bilene
  • Polyethylene vinylenes poly ( ⁇ phenylene vinylenes) such as poly ( ⁇ phenylene vinylene), polyaniline, poly ( ⁇ substituted alkylene), poly (trisubstituted vinyl), poly (2, (3 substituted alkylenes), polyacetylenes such as polyacetylene, polydiacetylenes such as polydiacetylene, polyazulenes such as polyazulene, Polypyrenes such as polypyrene, polycarbazole, poly rubazoles such as poly ( ⁇ -substituted carbazole), polyselenophenes such as polyselenophene, polyfurans such as polyfuran
  • oligomers such as ⁇ , ⁇ -bis (3-butoxypropyl) -a-sectiophene and styrylbenzene derivatives can also be suitably used.
  • copper phthalocyanine is a metal phthalocyanine such as fluorine-substituted copper phthalocyanine described in JP-A-11-251601, naphthalene 1, 4, 5, 8-tetracarboxylic acid diimide, N, N, Bis (4 trifluoromethylbenzyl) naphthalene 1, 4, 5, 8—tetra-force With rubonic acid diimide, N, N, 1 bis (1H, 1H—perfluorooctyl), N, N, Naphthalene such as bis (1H, 1H perfluorobutyl) and N, N, dioctylnaphthalene 1, 4, 5, 8-tetracarboxylic diimide derivatives, naphthalene 2, 3, 6, 7 tetracarboxylic diimide Tetracarboxylic acid diimides and anthracene 2, 3, 6, 7-tetra force Fused ring tetra force such as anthracene te
  • thiophene, vinylene, thiazylene vinylene, phenylene vinylene, ⁇ -phenylene these substitution products, or a combination of two or more thereof as a repeating unit
  • Number of repeating units ⁇ Force ⁇ 10 or polymers having a repeating unit ⁇ of 20 or more, condensed polycyclic aromatic compounds such as pentacene, fullerenes, condensed ring tetracarboxylic diimides, metal phthalocyanines At least one selected from the group is preferred.
  • organic semiconductor materials include tetrathiafulvalene (TTF) -tetracyanoquinodimethane (TCNQ) complex, bisethylenetetrathiafulvalene (BEDTTTF) -perchloric acid complex, BEDTTTF iodine complex, TCNQ iodine complex, etc.
  • TTF tetrathiafulvalene
  • BEDTTTF bisethylenetetrathiafulvalene
  • TCNQ iodine complex etc.
  • the organic molecular complex can also be used.
  • ⁇ -conjugated polymers such as polysilane and polygermane can also be used as organic'inorganic hybrid materials described in JP-A-2000-260999.
  • a material having a functional group such as acrylic acid, acetamido, dimethylamino group, cyano group, strong lpoxyl group, nitro group, benzoquinone derivatives, tetracyanethylene and tetracyanoquinodimethane, and their A material that serves as an acceptor such as a derivative, a material having a functional group such as an amino group, a triphenyl group, an alkyl group, a hydroxyl group, an alkoxy group, or a phenyl group, or a substituted amine such as phenoldiamine.
  • a material having a functional group such as acrylic acid, acetamido, dimethylamino group, cyano group, strong lpoxyl group, nitro group, benzoquinone derivatives, tetracyanethylene and tetracyanoquinodimethane, and their A material that serves as an acceptor such as a derivative, a material having a functional group such as an amino group
  • Anthracene benzoanthracene, substituted benzoanthracene, pyrene, substituted pyrene, force rubazole and its derivatives, tetrathiafulvalene and its derivatives, etc.
  • a so-called doping process may be performed.
  • the doping is an electron-donating molecule (acceptor) or an electron-donating molecule (donor). Is introduced into the thin film as a dopant. Therefore, the doped thin film is a thin film containing the condensed polycyclic aromatic compound and the dopant. Known dopants can be used.
  • a resin material such as a plastic film sheet can be preferably used.
  • the plastic film include polyethylene terephthalate, polyethylene naphthalate, polyethersulfone, polyetherimide, polyetherketone, polyphenylene sulfide, polyacrylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. Film.
  • the TFT array can be manufactured by a known semiconductor manufacturing process.
  • the TFT20 size is a rectangle or square with sides of 20 ⁇ m to 100 ⁇ m, and the bus line width including the bit line 27, source line 22, and gate line 25 is 10 ⁇ m.
  • the distance between the source electrode 21 and the source line 22 of the source separation unit 23 is 10 ⁇ m to 40 ⁇ m.
  • FIG. 3 is a circuit diagram of a part of a TFT array 66, which is a semiconductor device according to another embodiment of the present invention.
  • a difference from the TFT array 66 shown in FIG. 1 is that, instead of the source isolation portion 23 in FIG. 1, a drain isolation portion 41 corresponding to the isolation portion of the present invention is provided between the drain electrode 26 and the bit line 27. This is the point in between.
  • FIG. 4 is a structural diagram of the TFT 20 shown in FIG. Figure 4 (a) is a plan view of TFT20.
  • FIG. 4 (b) is a cross-sectional view taken along section B-B in Fig. 4 (a).
  • FIG. 4 (c) shows the state in which the drain separating part 41 of the TFT 20 is filled with the conductive material 32 in FIG. 4 (b).
  • FIG. 5 is a schematic diagram showing an outline of the manufacturing process of the semiconductor device according to the present invention.
  • the manufacturing process of the semiconductor device includes an identification information input unit 61, a wiring pattern generation unit 62, an ink jet printer 63, a heating unit 64, a sealing unit 65, and a transport unit 67. Not shown, it is controlled intensively by the control unit.
  • the identification information input unit 61 is composed of input devices such as a CPU (Central Processing Unit), a work memory, a storage unit, a display unit, a keyboard, etc. (not shown), and an ID code and a serial number written in the TFT array 66 And the like.
  • the identification information generated by the identification information input unit 61 is sent to the wiring pattern generation unit 62.
  • the wiring pattern generation unit 62 includes a CPU (Central Processing Unit), a work memory, a storage unit, and the like (not shown), and is based on the identification information sent from the identification information input unit 61 and the model information of the inkjet printer 63. To the wiring pattern information of the source separation unit 23 of the TFT array, and further to the control data such as allocation to the head and nozzle (not shown) of the inkjet printer 63, alignment of the ejection start position, and the number of ejections. To the Inkjet printer 63.
  • a CPU Central Processing Unit
  • the inkjet printer 63 applies a conductive material (not shown) to the TFT array 66 based on the control data transferred from the wiring pattern generation unit 62, and the wiring pattern of the conductive material is applied to the TFT array 66.
  • an ink containing metal particles containing any one of platinum, gold, silver, copper, cobalt, chromium, iridium, nickel, palladium, molybdenum, and tungsten can be used.
  • the heating unit 64 includes a hot plate, lamp annealing, and the like, and has a function of baking the metal particles by heating and drying the solvent of the ink 72 at 100 ° C to 300 ° C.
  • the sealing portion 65 has a function of applying a sealing material to insulate and protect the TFT array from moisture.
  • the TFT array is covered with a sealing material by a spray coating method, a blade coating method, a printing method, or an ink jet method.
  • sealing material polyimide, polyamide polybulal alcohol, polybulfenol, polyester, and polyacrylate are preferable.
  • the transport unit 67 includes rollers, a belt, a motor, a support material, a drive circuit, and the like (not shown).
  • the transport unit 67 supports and transports the TFT array, forms a wiring pattern by the ink jet printer 63, performs heat treatment by the heating unit 64, and seals 65. The sealing is performed continuously.
  • FIG. 6 is a cross-sectional view showing the state transition of the TFT 20 shown in FIG. 1 and FIG. 2 in the manufacturing process shown in FIG. 5, where the separation part is selectively connected with a conductive material (a — The cases where the separator is not connected are shown in (b–l), (b–2), and (b–3) in 1), (a–2), and (a–3).
  • the TFT array 66 having the source isolation portion between the source line and the source electrode will be described as an example.
  • the TFT array having the drain isolation portion between the bit line and the drain electrode No. 67 is applied so that the drain isolation portion is electrically connected or isolated in place of the source isolation portion.
  • the TFT array 66 located at the position PO is transported to the ejection position P 1 of the ink jet printer 63.
  • Fig. 6 (a-1) (b-l)) o TFT array 66 transported to PI receives conductive material (ink 72 containing metal particles) from wiring pattern generator 62 by ink jet printer 63.
  • a predetermined wiring pattern is applied to the source separation part 23 of the TFT array according to the control data sent (FIG. 6 (a-2)).
  • the ink 72 is not applied to the separation portion that is not connected (FIG. 6 (b-2)).
  • FIG. 7 is a schematic diagram showing how the ink 72 is ejected from the ink jet printer 63 of FIG.
  • the ink 72 is ejected from the head 74 to the TFT array 66 through the nozzle 73 toward the source separation unit 23.
  • the ejection means that the ink is ejected also with the nozzle force
  • the application means a state where the ejected ink has landed on the separation portion.
  • the source separation unit 23 on which the ink 72 has landed is filled with the ink 23.
  • the TFT array 66 to which the ink 72 has been applied by the inkjet printer 63 is conveyed to the heating unit 64 (P2).
  • the heating unit 64 the solvent contained in the ink 72 applied by the ink jet printer 63 is heated and dried, and the conductive material is baked to electrically connect the separation unit 23 to which the ink 72 has been applied.
  • the TFT array 66 transported to the position P3 is sealed with the sealing material 71 at the sealing portion 65 (P3) (FIGS. 6 (a-3) (b-3)).
  • an ID code or a serial number is used as identification information, and each separation part of TFT array 66 is connected with a wiring pattern based on the identification information.
  • identification information not shown, using the image information such as a face photograph, logo mark, fingerprint, etc. acquired by an image capture device such as a digital still camera or scanner, and connecting each separation part of the TFT array 66 with an image-like wiring pattern It may be.
  • a signal output from the TFT array 66 having an image-like wiring pattern can be used as identification information of an electronic device in which the TFT array 66 is incorporated, and a one-time password or time
  • identification information for temporary use such as restricted card keys
  • the amount of the ink 72 applied to the source separation unit 23 may be changed stepwise based on the input identification information.
  • the amount of the ink 72 to be applied is changed by changing the area covering the source separation unit 23 by a known area gradation image forming method, or changing the area covering the source separation unit 23 by a known overlaid image forming method. Or change the thickness.
  • FIG. 8 is a schematic diagram showing an outline of the manufacturing process of the semiconductor device according to the present invention.
  • the manufacturing process of the semiconductor device includes a heating unit 64 and a sealing unit in the manufacturing process illustrated in FIG.
  • a conductive material supply unit 80 is added between 65.
  • the wiring pattern generation unit 62 converts the identification information sent from the identification information input unit 61 into pattern information, further generates control data for the wiring pattern information power, and transfers the control data to the inkjet printer 63.
  • the inkjet printer 63 discharges an insulating material, which will be described later, to the TFT array on the basis of the control data transferred from the wiring pattern generation unit 62, and the insulating material to the TFT array 66.
  • a wiring pattern is formed using a material.
  • the insulating material it is possible to use an ink containing polyimide, polyamide polybulal alcohol, polybuluphenol, polyester, polyacrylate, or the like.
  • the conductive material supply unit 80 is insulated by the inkjet printer 63 by applying the above-described fluid conductive material to the entire surface of the TFT array, or by bringing a conductive sheet or aluminum foil into close contact with the entire surface of the TFT array. It has a function of electrically connecting the source separation part 23 when the material 81 is applied. Since the source separation part 23 is coated with an insulating material in advance by the ink jet printer 63, the insulating material 81 is applied and only the base separation part is connected with a conductive sheet or aluminum foil.
  • FIG. 9 is a cross-sectional view showing the state transition of the TFT 20 shown in FIGS. 1 and 2 in the manufacturing process shown in FIG. 8, where the source separation portion 23 is selectively applied with an insulating material 81.
  • (d 1), (d-2), (d-3), (d-4) are not coated with the source separator 23, (c 1), (c-2), (b-3) ) and (c 4).
  • the TFT array 66 at the position PO is transported to the ejection position P 1 of the ink jet printer 63. (Fig. 9 (c 1) (d- 1))
  • a predetermined wiring pattern is applied to the source separation unit 23 of the TFT array 66 in accordance with the control data sent from the wiring pattern generation unit 62 (FIG. 9 (d-2)). .
  • the TFT array 66 transported to the position P2 is heated, dried, and baked, and then adhered to the position P3 with a conductive material 82 such as a conductive sheet or aluminum foil.
  • the source separation portion 23 coated with the insulating material 81 is filled with the insulating material 81, it remains electrically insulated (Fig. 9 (d-3)). 81 is applied and the V-shaped separation part 23 is electrically connected by a conductive material 82 such as a conductive sheet or aluminum foil (FIG. 9 (c 3)).
  • the TFT array 66 transported to the position P4 is sealed with a sealing material such as an insulating sheet 83 at the sealing portion 65 (Fig. 9 (c 4) (d-4)) G
  • image information such as a face photograph or logo mark may be used as identification information, and each separation part of the TFT array 66 may be connected with an image-like wiring pattern! / Needless to say! /.
  • TFT ROM Read Only Memory
  • FIG. 10 is a circuit diagram schematically showing the concept of the TFTROM 100 using the TFT array 66 shown in FIG. The same configuration is used when the TFT array 67 shown in FIG.
  • TFTROM100 consists of TFT array 66, ROW decoder 551, COLUMN decoder 552
  • the TFT array 66 has the same configuration as the TFT array 66 shown in FIG. 1, and is arranged in a matrix form TFT201 to TFT205, gate lines 251 to 253, bit lines 27, source lines 221 to 2
  • the TFTROM 100 has data written in advance in storage elements arranged in two dimensions, and the contents are not lost even if the power supply is turned off and on.
  • the device is accessed using the address lines in the row and column directions.
  • the accessed storage element outputs its contents.
  • TFTs 201 to 205 are the TFTs 20 described above with reference to FIG.
  • the ROW decoder 551 and the COLUMN decoder 552 are circuits that decode binary address signal input from an external circuit (not shown).
  • the gate lines 251 to 253 are ROM address lines, and are connected to the output of the ROW decoder 551 by connecting the gate electrodes 24 in the X row direction.
  • the source lines 221 to 224 are the TFTROM 100 address lines, and the COLUMN decoder 5
  • the bit line 27 is a ROM data line, and is connected to the input of the buffer 53 by connecting all the drain electrodes 26 !.
  • One of the resistors 52 is connected to the power supply VDD 51 and the other is connected to the bit line 27.
  • the resistor 52 functions as a pull-up resistor to maintain the VDD potential.
  • the buffer 53 is a voltage level conversion IC (integrated circuit) for causing the external circuit to match the voltage of the bit line 27 that is the output of the TFTs 201 to 205.
  • One of the source lines 221 to 223 is connected to the source separator 23 and the other is connected to the output of the COLUMN decoder 552 !.
  • ROW address signal input from an external circuit (not shown) enables one of the outputs of the ROW decoder 551 to be enabled.
  • the COLUMN decoder 5 receives a COLUMN address signal input from an external circuit.
  • the COLUMN decoder 552 sets the source line 221 to low (LOW potential) and the other source lines 222 to 224 to high (HI potential).
  • the source isolation part 23 connected to the TFT 201 is connected by the conductive material 32, so that the COLUMN is connected from the power source VDD51 via the resistor 52, bit line 27, TFT201, and source line 221.
  • the potential of the bit line 27 is converted by the output buffer 53, and the output 54 to the external circuit becomes low. Since the other source lines 222 to 224 are high, no current flows between the drains and sources of the TFTs 202 to 204.
  • the source separation part 23 of the TFT 202 is not connected by the conductive material 32, and therefore the bit line 27 from the power supply VDD 51
  • the current does not flow to the output of the COLUMN decoder 552 via the TFT 202 and the source line 202, and the bit line 27 maintains the same potential as the power supply VDD51. Therefore, the potential of the bit line 27 becomes high, the voltage is converted by the output buffer 53, and the output 54 to the external circuit becomes high.
  • one of the TFTs 201 to 205 is selected by the ROW address signal and the COLUMN address signal from the external circuit, and the source connected to the selected TFT.
  • the separator 23 When the separator 23 is connected with a conductive material, the output to the external circuit is low, and when it is connected, it is high.
  • the output data related to one read operation of the TFTROM 100 shown in FIG. 10 is 1 bit.
  • the source separation unit 23 if the amount of ink 72 applied to the source separation unit 23 is changed stepwise based on the input identification information, the source separation is performed. Depending on the amount of the conductive material that connects part 23, the output signal strength differs, and it becomes possible to handle multi-value signals in one TFT.
  • the ROW decoder 551, the COLUMN decoder 552, and the output buffer 53 are configured to detect the signal strength so that a multilevel signal can be handled.
  • FIG. 11 is an electrical block diagram of the RFID card 9 on which the TFTROM 100 is mounted.
  • TFTROM 101 which has a plurality of TFTROMs 100 connected in parallel, can be used to obtain multiple bits of output data in a single read operation.
  • the configuration of the memory circuit 98 of the RFID card 9 is different from that of the RFID card of Fig. 13 described above.
  • the memory circuit 98 includes an EEPROM 99 and a TFT ROM 101.
  • EEPROM99 is a read Z write memory and TFTROM101 is a read only memory.
  • the control program and temporarily stored data are written and read by EEPROM99, and the ID code is written to TFTROM101. Since TFTROM101 cannot be easily rewritten, it is possible to realize a system with high security that prevents tampering and counterfeiting.
  • FIG. 12 is an external perspective view showing the configuration of the RFID card 9.
  • the coil 92 is configured by a printed wiring or the like formed in a spiral shape on the substrate 90.
  • the IC 91 includes a rectifier 93 for generating a power supply voltage in FIG. 11, a power supply circuit 94, a demodulation circuit 95 for demodulating data captured from the coil, a modulation circuit 96 for transmitting data to the outside via the coil, data Control circuit 97 that controls the exchange of commands and commands, etc. And EEPROM99, which is part of the memory circuit.
  • TFTROM101 is connected to IC91. Since the TFTROM101 is not built in the IC91, the ID code can be physically written by the customer.
  • the wiring pattern is generated by the method shown in FIGS. 4 to 9 in a state where the TFT ROM 101 is mounted on the RFID force card 9. . In this way, it is possible to easily and quickly create the RFID card 9 that is not easily tampered with or counterfeited.
  • the information writing to the TFTROM 101 of the RFID card 9 is performed by directly using biometrics information such as fingerprints, palm prints, and nose prints using a conductive material instead of the method shown in FIGS. It is also possible to transfer to the TFT array 66 constituting the TF TROM101.
  • the electronic device includes a plurality of thin film transistors including a gate electrode, a gate insulating layer, a source electrode and a drain electrode connected by a semiconductor layer, and a plurality of thin film transistors on a substrate.
  • An electronic device identification comprising: a connection step of connecting with a material; and a step of using a signal output from the semiconductor device connected in the connection step as identification information Broadcast issuing method it is possible to configure the.
  • the image-like conductive material such as fingerprints, palm prints, and nose prints transferred to the TFT array 66 electrically connects specific separation portions of the TFT array 66.
  • the signal output from the TFT array 66 having an image-like wiring pattern can be used as the identification information of the electronic device in which the TFT array 66 is incorporated, with a one-time password or time limit.
  • identification information for the purpose of temporary use, such as card keys, it is possible to easily issue identification information that is not easily tampered with or counterfeited, and it is possible to visually recognize image-like metric information. Since it is easy, unauthorized use such as impersonation can also be prevented.
  • the description content in each of the above embodiments is a preferred example of the semiconductor device and the electronic device according to the present invention, and the present invention is not limited to this.
  • the description has been given by taking an RFID card as an example of an electronic device.
  • the present invention is also applicable to an electronic device such as a RFID tag, a mobile phone, a PDA (Personal Digital Assistant), or a digital still camera. .
  • the separation part is provided between one of the source electrode and the source line or between the drain electrode and the bit line, and the separation part is connected by a conductive material.
  • the separation part can be connected in a state of being mounted on the substrate.
  • the separation part is connected with a conductive material, it is not electrically rewritten or erased.
  • the isolation part that is insulated based on the wiring pattern input in the input process is insulated with the fluid insulating material, and the other isolation part is connected with the conductive material, all the isolation parts are connected. Since it is hermetically sealed with a conductive material or an insulating material, after that, for example, even if the entire TFT array is sealed, there is a wide range of options in selecting a sealing material that does not directly contact the electrode. Spread.
  • the storage means of the electronic device is a semiconductor manufactured by the manufacturing method according to the present invention, the identification information written in the storage means that is not easily affected by physical disturbances. This makes it possible to provide electronic devices that are difficult to be intentionally tampered with at low cost with little effort.

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Abstract

A memory in which writing can be performed while being mounted on a substrate as a memory for storing the ID code or the production number of an electronic apparatus and in which rewriting is very difficult, and its writing method. The semiconductor device and its fabrication method are characterized in that the isolation part in a TFT array provided between the source and the source line or between the drain and the bit line of a TFT is connected with a conductive material by ink jet system according to a desired pattern.

Description

明 細 書  Specification
半導体装置、その製造方法及び電子装置  Semiconductor device, method for manufacturing the same, and electronic device
技術分野  Technical field
[0001] 本発明は、半導体装置、その製造方法及び電子装置に関する。  The present invention relates to a semiconductor device, a manufacturing method thereof, and an electronic device.
背景技術  Background art
[0002] 近年、マイクロコンピュータなどの IC (集積回路)を使った携帯電話に代表される携帯 電子装置の普及率は高い。また、今後 ICカードや無線タグなどの普及拡大が見込ま れる。  [0002] In recent years, the penetration rate of portable electronic devices typified by cellular phones using ICs (integrated circuits) such as microcomputers has been high. In addition, the spread of IC cards and wireless tags is expected in the future.
[0003] ICカードの一例としてリーダライタ装置のコイル力も発生される電波（電磁波）を IC カード側のコイルで受信し、電力及びクロック、送受信信号を生成して、リーダライタ 装置より受信したコマンドを処理する、 RFID (Radio Frequency Identification) 方式の ICカード (以下、 RFIDカードという）が提案されている（例えば、特許文献 2)。  As an example of an IC card, a radio wave (electromagnetic wave) that also generates a coil force of a reader / writer device is received by a coil on the IC card side, and power, a clock, and a transmission / reception signal are generated, and a command received from the reader / writer device is received. An RFID (Radio Frequency Identification) type IC card (hereinafter referred to as an RFID card) to be processed has been proposed (for example, Patent Document 2).
[0004] 図 13は従来の RFIDカードの電気的構成を示すブロック図である。 RFIDカード 10 は、コイル 12に接続された受信交流信号を整流して直流電圧に変換する整流回路 1 3と、該整流回路 13により変換された直流電圧に基づいて RFIDカード 10の回路の 駆動に必要な電源電圧 VDDを発生する電源回路 14と、コイル 12を介して外部から 供給される交流信号に含まれる受信情報を抽出 (復調)する復調回路 15と、送信情 報を含む交流信号を形成 (変調)してコイル 12を駆動する変調回路 16と、 RFIDカー ド 10を識別するため識別情報を記憶するメモリ回路 18と復調回路 15により復調され た受信情報に基づいてメモリ回路 18内へデータを書き込んだり、メモリ回路 18から 読み出された送信情報を変調回路 16へ出力するなどの処理並びに図示しない外部 のリーダライタとの間の送受信のプロトコル制御を行うリードライト制御回路 17などに より構成されている。  FIG. 13 is a block diagram showing an electrical configuration of a conventional RFID card. The RFID card 10 rectifies the received AC signal connected to the coil 12 and converts it into a DC voltage, and drives the circuit of the RFID card 10 based on the DC voltage converted by the rectifier circuit 13. A power supply circuit 14 that generates the required power supply voltage VDD, a demodulation circuit 15 that extracts (demodulates) received information contained in an AC signal supplied from the outside via the coil 12, and an AC signal that includes transmission information are formed. Based on the received information demodulated by the modulation circuit 16 that modulates and drives the coil 12, the memory circuit 18 that stores identification information for identifying the RFID card 10 and the demodulation circuit 15, the data is stored in the memory circuit 18. Read / write control circuit 17 that performs processing such as writing transmission data and outputting transmission information read from memory circuit 18 to modulation circuit 16 and protocol control for transmission and reception with an external reader / writer (not shown). It is more structured etc..
[0005] コイル 12で受信された交流信号は、復調回路 15に入力され、 ASK変調 (振幅変 調)された信号からこれを復調し、データ信号を再生する。再生されたデータは、メモ リ回路 18のリードライト制御並びに送受信プロトコル制御を行うリードライト制御回路 1 7によってメモリ回路 18へ書き込まれる。一方、 RFIDカードからリードライタへの送信 データは、リードライト制御回路 17によってメモリ回路 18から読み出され、変調回路 1 6によってコイル信号に対して LSK (負荷変調）を行い、データを送信する。 [0005] The AC signal received by the coil 12 is input to the demodulation circuit 15, where it is demodulated from the ASK modulated (amplitude modulated) signal, and the data signal is reproduced. The reproduced data is written into the memory circuit 18 by the read / write control circuit 17 that performs read / write control of the memory circuit 18 and transmission / reception protocol control. Meanwhile, transmission from the RFID card to the reader / writer Data is read from the memory circuit 18 by the read / write control circuit 17, LSK (load modulation) is performed on the coil signal by the modulation circuit 16, and the data is transmitted.
[0006] ここで、電子装置である RFIDカード 10はリーダライタとのデータのやり取りの中で 相互間で識別するために IDコードを保持する必要がある。 IDコードを保持するメモリ 回路 18には、 EEPROM (Electrically Erasable Programmable Read Only Memory)のような電気的に書き込み、消去可能な不揮発性メモリを用いるのが一 般的である (例えば、特許文献 2)。また、所望の情報に従って切断用端子に高電圧 をかけて大電流を流して溶断することで IDコードを物理的に書き込むことができるヒ ユー ROMを使用することも知られて 、る（例えば特許文献 1)。  [0006] Here, the RFID card 10 as an electronic device needs to hold an ID code in order to identify each other during the exchange of data with the reader / writer. For the memory circuit 18 that holds the ID code, it is common to use an electrically writable / erasable nonvolatile memory such as EEPROM (Electrically Erasable Programmable Read Only Memory) (for example, Patent Document 2). . It is also known to use a fuse ROM that can physically write an ID code by applying a high voltage to a cutting terminal according to desired information and blowing it with a large current (for example, patents). Reference 1).
[0007] 近年では、製品番号や IDコードなどの識別情報に応じた配線パターンをインクジェ ットプリンタによって形成する電子回路基板の製造法が提案されている (例えば、特 許文献 3)。この方法によれば、手間が力からず低コストで IDコードを書き込むことが できる。  [0007] In recent years, a method of manufacturing an electronic circuit board in which a wiring pattern corresponding to identification information such as a product number or ID code is formed by an inkjet printer has been proposed (for example, Patent Document 3). According to this method, the ID code can be written at low cost without much effort.
特許文献 1 :特開平 2— 13046号公報  Patent Document 1: JP-A-2-13046
特許文献 2：特開 2000— 172806号公報  Patent Document 2: Japanese Patent Laid-Open No. 2000-172806
特許文献 3：特開 2002— 344113号公報  Patent Document 3: Japanese Patent Laid-Open No. 2002-344113
発明の開示  Disclosure of the invention
[0008] 特許文献 1のヒューズ ROMに IDコードや製造番号を書き込む場合、大電流を流し て溶断するための専用書き込み装置にヒユー ROMを取り付けて IDコードや製造 番号を書き込む必要があり、また、書き込み後に電子装置の基板に取り付けなけれ ばならず、手間が力からず低コストで IDコードや製造番号を書き込むことが困難であ つた o  [0008] When writing the ID code and serial number in the fuse ROM of Patent Document 1, it is necessary to write the ID code and serial number by attaching a new ROM to a dedicated writing device for blowing by flowing a large current. It must be attached to the board of the electronic device after writing, and it is difficult to write ID code and serial number at low cost because it is laborious and o
[0009] 一方、特許文献 2の EEPROMは、電子装置に組み込まれた状態で IDコードや製 造番号の書き込みが可能である。し力しながら、不正な IDコードや製造番号が書き 込まれるというセキュリティの問題が残る。まして、 ICタグや携帯電話等の携帯機器に 搭載する場合は電波を経由して情報が書き込まれるので、比較的容易に EEPROM の内容を書き換えられるおそれがある。  On the other hand, the EEPROM of Patent Document 2 can be written with an ID code or a production number while being incorporated in an electronic device. However, there remains a security problem that an invalid ID code or serial number is written. Moreover, when it is mounted on a portable device such as an IC tag or a mobile phone, information is written via radio waves, so there is a risk that the contents of the EEPROM can be rewritten relatively easily.
[0010] 本発明は、電子装置に組み込まれた状態で IDコードや製造番号を書き込むことが でき、かつ、書き換えが困難な半導体装置とその製造法を提供することを課題として いる。 [0010] According to the present invention, an ID code and a manufacturing number can be written in a state of being incorporated in an electronic device. An object of the present invention is to provide a semiconductor device that can be rewritten and difficult to rewrite, and a manufacturing method thereof.
本発明者は鋭意検討した結果、本発明の目的は下記構成のいずれかを採ることに より、達成されることが分った。  As a result of intensive studies, the present inventor has found that the object of the present invention can be achieved by adopting one of the following configurations.
(構成 1)基材上に、ゲート電極と、ゲート絶縁層と、半導体層で連結されたソース電 極及びドレイン電極とを有する複数の薄膜トランジスタと、複数の前記ゲート電極を連 結するゲート線と、前記ソース電極を連結するソース線と、前記ドレイン電極を連結す るビット線とを有する薄膜トランジスタアレイを有する半導体装置であって、前記ソー ス電極と前記ソース線との接続及び前記ドレイン電極と前記ビット線との接続の少なく とも一方の接続が分離されており、かつ導電性材料で接続可能な分離部を有する半 導体装置。  (Configuration 1) A plurality of thin film transistors each including a gate electrode, a gate insulating layer, and a source electrode and a drain electrode connected by a semiconductor layer on a substrate, and a gate line connecting the plurality of gate electrodes. A semiconductor device having a thin film transistor array having a source line connecting the source electrode and a bit line connecting the drain electrode, the connection between the source electrode and the source line, and the drain electrode and the A semiconductor device having a separation portion in which at least one of the connections to the bit line is separated and can be connected with a conductive material.
(構成 2)基材上に、ゲート電極と、ゲート絶縁層と、半導体層で連結されたソース電 極及びドレイン電極とを有する複数の薄膜トランジスタと、複数の前記ゲート電極を連 結するゲート線と、前記ソース電極を連結するソース線と、前記ドレイン電極を連結す るビット線とを有する薄膜トランジスタアレイを有する半導体装置の製造方法において 、前記薄膜トランジスタアレイの配線パターンを入力する入力工程と、前記入力工程 で入力された配線パターンに基づき、予め接続が分離された、前記ソース電極と前 記ソース線間の分離部を、導電性材料で接続する接続工程とを含む半導体装置の 製造方法。  (Configuration 2) On a base material, a plurality of thin film transistors having a gate electrode, a gate insulating layer, and a source electrode and a drain electrode connected by a semiconductor layer, and a gate line connecting the plurality of gate electrodes In the method of manufacturing a semiconductor device having a thin film transistor array having a source line connecting the source electrode and a bit line connecting the drain electrode, an input step of inputting a wiring pattern of the thin film transistor array, and the input step A method for manufacturing a semiconductor device, comprising: a connection step of connecting a separation portion between the source electrode and the source line, which has been previously separated based on the wiring pattern input in step 1, with a conductive material.
(構成 3)基材上に、ゲート電極と、ゲート絶縁層と、半導体層で連結されたソース電 極及びドレイン電極とを有する複数の薄膜トランジスタと、複数の前記ゲート電極を連 結するゲート線と、前記ソース電極を連結するソース線と、前記ドレイン電極を連結す るビット線とを有する薄膜トランジスタアレイを有する半導体装置の製造方法において 、前記薄膜トランジスタアレイの配線パターンを入力する入力工程と、前記入力工程 で入力された配線パターンに基づき、予め接続が分離された、前記ドレイン電極と前 記ビット線間の分離部を、導電性材料で接続する接続工程とを含む半導体装置の製 造方法。  (Configuration 3) On a base material, a plurality of thin film transistors each including a gate electrode, a gate insulating layer, and a source electrode and a drain electrode connected by a semiconductor layer, and a gate line connecting the plurality of gate electrodes In the method of manufacturing a semiconductor device having a thin film transistor array having a source line connecting the source electrode and a bit line connecting the drain electrode, an input step of inputting a wiring pattern of the thin film transistor array, and the input step A method for manufacturing a semiconductor device, comprising: a connection step of connecting a separation portion between the drain electrode and the bit line, which has been previously separated based on the wiring pattern input in step 1, with a conductive material.
(構成 4)前記接続工程は、前記入力工程で入力された配線パターンに基づき、接続 する前記分離部を流動性導電材料で接続する前記 (2)又は (3)に記載の半導体装 置の製造方法。 (Configuration 4) The connection process is based on the wiring pattern input in the input process. The method for manufacturing a semiconductor device according to (2) or (3), wherein the separation part is connected with a fluid conductive material.
(構成 5)前記分離部の流動性導電材料による接続は、インクジェット方式により、前 記流動性導電材料が前記分離部に塗布される前記 (4)に記載の半導体装置の製造 方法。  (Configuration 5) The method for manufacturing a semiconductor device according to (4), wherein the connection of the separation part with the fluid conductive material is applied to the separation part by an inkjet method.
(構成 6)前記接続工程は、前記入力工程で入力された配線パターンに基づき、絶縁 する前記分離部を流動性絶縁材料で絶縁した後、他の前記分離部を導電性材料で 接続する前記 (2)又は（3)に記載の半導体装置の製造方法。  (Structure 6) In the connection step, the insulating portion to be insulated is insulated with a fluid insulating material based on the wiring pattern input in the input step, and then the other separating portion is connected with a conductive material. (2) A method for manufacturing a semiconductor device according to (3).
(構成 7)前記分離部の流動性絶縁材料による絶縁は、インクジェット方式により、前 記流動性絶縁材料が前記分離部に塗布される前記 (6)に記載の半導体装置の製造 方法。  (Configuration 7) The method of manufacturing a semiconductor device according to (6), wherein the fluid insulating material is applied to the separation part by an ink jet method.
(構成 8)前記分離部が接続された薄膜トランジスタアレイを封止材料で封止する封 止工程を含む前記（2)〜（7)の何れか 1項に記載の半導体装置の製造方法。  (Structure 8) The method for manufacturing a semiconductor device according to any one of (2) to (7), including a sealing step of sealing the thin film transistor array to which the separation portion is connected with a sealing material.
(構成 9)電子情報を記憶する記憶手段を有する電子装置にお!、て、前記記憶手段 は、前記（2)〜（8)の 、ずれ力 1項に記載の製造方法で製造された半導体装置であ る電子装置。 (Arrangement 9) In an electronic device having a storage means for storing electronic information, the storage means is a semiconductor manufactured by the manufacturing method according to (1) above in (1). An electronic device that is a device.
図面の簡単な説明 Brief Description of Drawings
[図 1]本発明に係る TFTアレイの一部の回路図である。 FIG. 1 is a partial circuit diagram of a TFT array according to the present invention.
[図 2]図 2 (a)は図 1に示した TFTの平面図であり、図 2 (b)は図 2 (a)中の A— A断面 で切断した断面図である。図 2 (c)は図 2 (b)においてソース分離部に導電性材料が 満たされた状態を示す断面図である。  [FIG. 2] FIG. 2 (a) is a plan view of the TFT shown in FIG. 1, and FIG. 2 (b) is a cross-sectional view taken along the line AA in FIG. 2 (a). FIG. 2 (c) is a cross-sectional view showing a state in which the source separation portion is filled with a conductive material in FIG. 2 (b).
[図 3]本発明の他の実施形態に係る TFTアレイの一部の回路図である。  FIG. 3 is a partial circuit diagram of a TFT array according to another embodiment of the present invention.
[図 4]図 4 (a)は図 3に示した TFTの平面図であり、図 4 (b)は図 4 (a)中の B— B断面 で切断した断面図である。図 4 (c)は図 4 (b)においてドレイン分離部に導電性材料 が満たされた状態を示す断面図である。 [FIG. 4] FIG. 4 (a) is a plan view of the TFT shown in FIG. 3, and FIG. 4 (b) is a cross-sectional view taken along the line BB in FIG. 4 (a). FIG. 4 (c) is a cross-sectional view showing a state where the drain isolation portion is filled with the conductive material in FIG. 4 (b).
[図 5]本発明に係る半導体装置の製造工程の概略を示した模式図である。  FIG. 5 is a schematic view showing an outline of a manufacturing process of a semiconductor device according to the present invention.
[図 6]本発明に係る半導体装置の製造工程における TFTの状態遷移図である。  FIG. 6 is a state transition diagram of a TFT in the manufacturing process of the semiconductor device according to the invention.
[図 7]インクジェット方式による分離部接続の模様を示した模式図である。 [図 8]本発明の他の形態に係る半導体装置の製造工程の概略を示した模式図である FIG. 7 is a schematic view showing a pattern of separation part connection by an ink jet method. FIG. 8 is a schematic diagram showing an outline of a manufacturing process of a semiconductor device according to another embodiment of the present invention.
[図 9]本発明の他の形態に係る半導体装置の製造工程における TFTの状態遷移図 である。 FIG. 9 is a state transition diagram of a TFT in a manufacturing process of a semiconductor device according to another embodiment of the present invention.
[図 10]TFTROMの構成図である。  FIG. 10 is a block diagram of a TFTROM.
[図 ll]TFTROMを搭載した RFIDカードの電気的構成を示すブロック図である。  FIG. 11 is a block diagram showing an electrical configuration of an RFID card equipped with a TFTROM.
[図 12]TFTROMを搭載した RFIDカードの外観斜視図である。  FIG. 12 is an external perspective view of an RFID card equipped with a TFTROM.
[図 13]従来の RFIDカードの電気的構成を示すブロック図である。  FIG. 13 is a block diagram showing an electrical configuration of a conventional RFID card.
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0013] 以下、実施の形態により本発明を詳しく説明するが、本発明はこれに限定されるも のではない。 [0013] Hereinafter, the present invention will be described in detail with reference to embodiments, but the present invention is not limited thereto.
[0014] 本発明の構成 1に係る半導体装置について図 1及び図 2を用いて説明する。  A semiconductor device according to Configuration 1 of the present invention will be described with reference to FIGS.
[0015] 図 1は、本発明に係る半導体装置である薄膜トランジスタ（以下 TFTと呼ぶ)アレイ 6FIG. 1 shows a thin film transistor (hereinafter referred to as TFT) array which is a semiconductor device according to the present invention.
6の一部の回路図である。 6 is a partial circuit diagram of FIG.
[0016] TFTアレイ 66は、マトリックス状に並べられた TFT20、ソース線 22、ソース分離部 2[0016] The TFT array 66 includes a TFT 20, a source line 22, and a source separation unit 2 arranged in a matrix.
3、ゲート線 25、ビット線 27からなる。 3. It consists of 25 gate lines and 27 bit lines.
[0017] TFT20は、電界効果型のトランジスタであり、ソース電極 21と、ゲート電極 24と、ド レイン電極 26とを有する。 The TFT 20 is a field effect transistor, and includes a source electrode 21, a gate electrode 24, and a drain electrode 26.
[0018] ソース線 22は、図中 Y方向に並べられた各 TFT20のソース電極 21同士を連結可 能に設けられたバスであり、 X方向に並べられた TFT20の 1列毎に少なくとも 1本設 けられている。 [0018] The source line 22 is a bus provided so that the source electrodes 21 of the TFTs 20 arranged in the Y direction in the figure can be connected to each other. At least one source line 22 is provided for each column of the TFTs 20 arranged in the X direction. It is installed.
[0019] 本発明の分離部であるソース分離部 23は、各 TFT20のソース電極 21とソース線 2 [0019] The source separation unit 23, which is the separation unit of the present invention, includes a source electrode 21 and a source line 2 of each TFT 20.
2との間に設けられて、ソース電極 21とソース線 22とを電気的に分離しており、後述 する方法により導電性材料で接続可能となっている。 2, the source electrode 21 and the source line 22 are electrically separated, and can be connected with a conductive material by a method described later.
[0020] ゲート線 25は、図中 X方向に並べられた各 TFT20のゲート電極 24同士を連結す るバスであり、 Y方向に並べられた TFT20の 1行毎に少なくとも 1本設けられて!/、る。 [0020] The gate line 25 is a bus that connects the gate electrodes 24 of the TFTs 20 arranged in the X direction in the figure, and at least one gate line 25 is provided for each row of the TFTs 20 arranged in the Y direction! /
[0021] ビット線 27は、図中 Y方向に並べられた各 TFT20のドレイン電極 26同士を連結す るバスであり、 X方向に並べられた TFT20の 1列毎に少なくとも 1本設けられて!/、る。 [0022] 図 2は図 1に示した TFT20及びその周辺部の構造図である。図 2 (a)は TFT20及 びその周辺部の平面図であり、図 2 (a)中の A— A断面で切断した断面図が図 2 (b) である。図 2 (c)は図 2 (b)においてソース分離部 23に導電性材料 32が満たされた状 態を表している。以下の図においては、説明の重複を避けるため、前述したものと同 様の要素については同符号を付してある。 [0021] The bit line 27 is a bus that connects the drain electrodes 26 of the TFTs 20 arranged in the Y direction in the figure, and is provided at least one for each column of the TFTs 20 arranged in the X direction! / FIG. 2 is a structural diagram of the TFT 20 shown in FIG. 1 and its peripheral part. Fig. 2 (a) is a plan view of the TFT 20 and its peripheral part, and Fig. 2 (b) is a cross-sectional view taken along the AA line in Fig. 2 (a). FIG. 2 (c) shows a state where the conductive material 32 is filled in the source separator 23 in FIG. 2 (b). In the following drawings, the same symbols are assigned to the same elements as those described above in order to avoid duplication of explanation.
[0023] TFT20は、絶縁材料である基材 35の上に図示しないゲート電極が連結されたゲ ート線 25、その上を絶縁層 34が積層され、さらにその上に半導体 31、ビット線 27、ソ ース電極 21及びソース線 22が積層され、ソース分離部 23を除いて絶縁層 33で覆わ れている。  The TFT 20 has a gate line 25 connected to a gate electrode (not shown) on a base material 35 that is an insulating material, and an insulating layer 34 formed thereon, and further a semiconductor 31 and a bit line 27 formed thereon. The source electrode 21 and the source line 22 are stacked, and are covered with an insulating layer 33 except for the source separation portion 23.
[0024] 半導体 31は、一定の間隔を隔てて設けられたビット線 27及びソース電極 21に接続 している。なお、この場合は半導体 31とビット線 27とが接続している面が図 1に示し たドレイン電極 26に相当することになる。  The semiconductor 31 is connected to the bit line 27 and the source electrode 21 provided at a constant interval. In this case, the surface where the semiconductor 31 and the bit line 27 are connected corresponds to the drain electrode 26 shown in FIG.
[0025] また、ソース電極 21とソース線 22との間には、絶縁層 34に至るまで上面が開放さ れたソース分離部 23が形成されるように、ソース電極 21及びソース線 22とが設けら れている。 In addition, between the source electrode 21 and the source line 22, the source electrode 21 and the source line 22 are formed so that a source separation portion 23 whose upper surface is opened up to the insulating layer 34 is formed. It is provided.
[0026] 図 2 (c)に示すように、ソース分離部 23は、所望の配線パターンに従って選択的に 、開放された上部カゝら供給される導電性材料 32で満たされ、電気的に接続される。  [0026] As shown in FIG. 2 (c), the source separator 23 is selectively filled in accordance with a desired wiring pattern with the conductive material 32 supplied from the opened upper cover, and is electrically connected. Is done.
[0027] 導電性材料 32としては、導電性材料を含むものであればどのような材料を用いても 構わないが、特に後述の導電性ポリマーや、金属微粒子を含有する導電性ペースト 、導電性インク又は金属薄膜前駆体材料を好適に用いることができる。  [0027] As the conductive material 32, any material may be used as long as it includes a conductive material. In particular, a conductive polymer described later, a conductive paste containing metal fine particles, An ink or a metal thin film precursor material can be suitably used.
[0028] 金属微粒子の材料としては白金、金、銀、ニッケル、クロム、銅、鉄、錫、アンチモン 鉛、タンタル、インジウム、パラジウム、テルル、レニウム、イリジウム、アルミニウム、ル テ-ゥム、ゲルマニウム、モリブデン、タングステン、亜鉛等を用いることができる。  [0028] Materials for the metal fine particles include platinum, gold, silver, nickel, chromium, copper, iron, tin, antimony lead, tantalum, indium, palladium, tellurium, rhenium, iridium, aluminum, ruthenium, germanium, Molybdenum, tungsten, zinc, or the like can be used.
[0029] また、溶媒や分散媒体としては、有機半導体へのダメージを抑制するため、水を 60 %以上、好ましくは 90%以上含有する溶媒又は分散媒体であることが好ましい。  [0029] The solvent or dispersion medium is preferably a solvent or dispersion medium containing 60% or more, preferably 90% or more of water in order to suppress damage to the organic semiconductor.
[0030] さらに、ドーピング等により導電率を向上させた公知の導電性ポリマーの分散物、 例えば導電性ポリア-リン、導電性ポリピロール、導電性ポリチォフェン、ポリエチレン ジォキシチォフェンとポリスルホン酸の錯体なども好適に用いられる。 [0031] 半導体 31材料としては、 π共役系材料が用いられ、例えばポリピロール、ポリ（Ν— 置換ピロール）、ポリ（3—置換ピロール）、ポリ（3, 4—二置換ピロール）などのポリピ ロール類、ポリチォフェン、ポリ（3—置換チォフェン）、ポリ（3, 4—二置換チォフェン )、ポリべンゾチオフ ンなどのポリチオフ ン類、ポリイソチアナフテンなどのポリイソ チアナフテン類、ポリチェ-レンビ-レンなどのポリチェ-レンビ-レン類、ポリ（ρ フ ェニレンビニレン）などのポリ（ρ フエ二レンビニレン）類、ポリア二リン、ポリ（Ν 置換 ァ-リン）、ポリ（3 置換ァ-リン）、ポリ（2, 3 置換ァ-リン)などのポリア-リン類、 ポリアセチレンなどのポリアセチレン類、ポリジアセチレンなどのポリジアセチレン類、 ポリアズレンなどのポリアズレン類、ポリピレンなどのポリピレン類、ポリカルバゾール、 ポリ（Ν 置換カルバゾール）などのポリ力ルバゾール類、ポリセレノフェンなどのポリ セレノフェン類、ポリフラン、ポリべンゾフランなどのポリフラン類、ポリ（ρ フエ二レン） などのポリ（ρ—フエ-レン）類、ポリインドールなどのポリインドール類、ポリピリダジン などのポリピリダジン類、ナフタセン、ペンタセン、へキサセン、ヘプタセン、ジベンゾ ペンタセン、テトラべンゾペンタセン、ピレン、ジベンゾピレン、タリセン、ペリレン、コロ ネン、テリレン、ォバレン、クオテリレン、サ一力ムアントラセンなどのポリアセン類及び ポリアセン類の炭素の一部を N、 S、 Oなどの原子、カルボ-ル基などの官能基に置 換した誘導体（トリフエノジォキサジン、トリフエノジチアジン、へキサセン— 6, 15 キ ノンなど）、ポリビュルカルバゾール、ポリフエ-レンスルフイド、ポリビニレンスルフイド などのポリマーゃ特開平 11— 195790号公報に記載された多環縮合体などを用い ることがでさる。 [0030] Further, known conductive polymer dispersions whose conductivity has been improved by doping or the like, such as conductive polyarine, conductive polypyrrole, conductive polythiophene, polyethylene dioxythiophene and polysulfonic acid complex, etc. Are also preferably used. [0031] As the semiconductor 31 material, a π-conjugated material is used. For example, polypyrrole such as polypyrrole, poly (Ν-substituted pyrrole), poly (3-substituted pyrrole), and poly (3,4-disubstituted pyrrole). , Polythiophene, poly (3-substituted thiophene), poly (3,4-disubstituted thiophene), polybenzones such as polybenzothiophene, polyisothianaphthenes such as polyisothianaphthene, and polychelenylene bilene Polyethylene vinylenes, poly (ρphenylene vinylenes) such as poly (ρphenylene vinylene), polyaniline, poly (Ν substituted alkylene), poly (trisubstituted vinyl), poly (2, (3 substituted alkylenes), polyacetylenes such as polyacetylene, polydiacetylenes such as polydiacetylene, polyazulenes such as polyazulene, Polypyrenes such as polypyrene, polycarbazole, poly rubazoles such as poly (Ν-substituted carbazole), polyselenophenes such as polyselenophene, polyfurans such as polyfuran and polybenzofuran, poly (ρ phenylene) Poly (ρ-phenol) s, polyindoles such as polyindoles, polypyridazines such as polypyridazine, naphthacene, pentacene, hexacene, heptacene, dibenzopentacene, tetrabenzopentacene, pyrene, dibenzopyrene, taricene, perylene , Coronene, terylene, ovalene, quaterylene, derivatives of polyacene such as muanthracene, and derivatives of polyacenes substituted with atoms such as N, S, O, and functional groups such as carbo groups (Triphenozoxazine, Triphenodi Polymers such as azine, hexacene-6, 15 quinone, etc.), polybulucarbazole, polyphenylenesulfide, polyvinylenesulfide and the like, and polycyclic condensates described in JP-A-11-195790 are used. It is out.
[0032] また、これらのポリマーと同じ繰返し単位を有する例えばチォフェン 6量体である α ーセクシチォフェン α , ω—ジへキシノレ aーセクシチォフェン、 α , ω—ジへキシ ルー α—キンケチォフェン、 α , ω—ビス（3—ブトキシプロピル） - a—セクシチオフ ェン、スチリルベンゼン誘導体などのオリゴマーも好適に用いることができる。  [0032] Further, for example, thiophene hexamer α-seccithiophene α, ω-dihexenole a-seccithiophene, α, ω-dihexyl leu α-kinketiophene having the same repeating unit as these polymers Further, oligomers such as α, ω-bis (3-butoxypropyl) -a-sectiophene and styrylbenzene derivatives can also be suitably used.
[0033] さらに銅フタロシア-ンゃ特開平 11— 251601号公報に記載のフッ素置換銅フタ ロシアニンなどの金属フタロシアニン類、ナフタレン 1, 4, 5, 8—テトラカルボン酸ジ イミド、 N, N，一ビス（4 トリフルォロメチルベンジル）ナフタレン 1 , 4, 5, 8—テトラ力 ルボン酸ジイミドとともに、 N, N，一ビス（1H, 1H—ペルフルォロォクチル）、 N, N， ビス（1H, 1H ペルフルォロブチル）及び N, N，一ジォクチルナフタレン 1, 4, 5 , 8—テトラカルボン酸ジイミド誘導体、ナフタレン 2, 3, 6, 7テトラカルボン酸ジイミド などのナフタレンテトラカルボン酸ジイミド類、及びアントラセン 2, 3, 6, 7—テトラ力 ルボン酸ジイミドなどのアントラセンテトラカルボン酸ジイミド類などの縮合環テトラ力 ルボン酸ジイミド類、 C60、 C70、 C76、 C78、 C84等フラーレン類、 SWNTなどの力 一ボンナノチューブ、メロシアニン色素類、へミシァニン色素類などの色素などがあげ られる。 [0033] Further, copper phthalocyanine is a metal phthalocyanine such as fluorine-substituted copper phthalocyanine described in JP-A-11-251601, naphthalene 1, 4, 5, 8-tetracarboxylic acid diimide, N, N, Bis (4 trifluoromethylbenzyl) naphthalene 1, 4, 5, 8—tetra-force With rubonic acid diimide, N, N, 1 bis (1H, 1H—perfluorooctyl), N, N, Naphthalene such as bis (1H, 1H perfluorobutyl) and N, N, dioctylnaphthalene 1, 4, 5, 8-tetracarboxylic diimide derivatives, naphthalene 2, 3, 6, 7 tetracarboxylic diimide Tetracarboxylic acid diimides and anthracene 2, 3, 6, 7-tetra force Fused ring tetra force such as anthracene tetracarboxylic acid diimides such as rubonic acid diimide, C60, C70, C76, C78, C84, etc. Powers such as fullerenes and SWNTs Examples include single-bonn nanotubes, merocyanine dyes, and hemicyanine dyes.
[0034] これらの π共役系材料のうちでも、チォフェン、ビニレン、チヱ二レンビニレン、フエ 二レンビ-レン、 ρ—フエ-レン、これらの置換体又はこれらの 2種以上を繰返し単位 とし、かつ該繰返し単位の数 η力 〜 10であるオリゴマーもしくは該繰返し単位の数 η が 20以上であるポリマー、ペンタセンなどの縮合多環芳香族化合物、フラーレン類、 縮合環テトラカルボン酸ジイミド類、金属フタロシアニンよりなる群カゝら選ばれた少なく とも 1種が好ましい。  [0034] Among these π-conjugated materials, thiophene, vinylene, thiazylene vinylene, phenylene vinylene, ρ-phenylene, these substitution products, or a combination of two or more thereof as a repeating unit, and Number of repeating units η Force ˜10 or polymers having a repeating unit η of 20 or more, condensed polycyclic aromatic compounds such as pentacene, fullerenes, condensed ring tetracarboxylic diimides, metal phthalocyanines At least one selected from the group is preferred.
[0035] また、その他の有機半導体材料としては、テトラチアフルバレン (TTF)—テトラシァ ノキノジメタン (TCNQ)錯体、ビスエチレンテトラチアフルバレン（BEDTTTF)—過 塩素酸錯体、 BEDTTTF ヨウ素錯体、 TCNQ ヨウ素錯体、などの有機分子錯体 も用いることができる。さらにポリシラン、ポリゲルマンなどの σ共役系ポリマーゃ特開 2000— 260999に記載の有機'無機混成材料も用いることができる。  [0035] Other organic semiconductor materials include tetrathiafulvalene (TTF) -tetracyanoquinodimethane (TCNQ) complex, bisethylenetetrathiafulvalene (BEDTTTF) -perchloric acid complex, BEDTTTF iodine complex, TCNQ iodine complex, etc. The organic molecular complex can also be used. Furthermore, σ-conjugated polymers such as polysilane and polygermane can also be used as organic'inorganic hybrid materials described in JP-A-2000-260999.
[0036] 有機半導体層に、例えば、アクリル酸、ァセトアミド、ジメチルァミノ基、シァノ基、力 ルポキシル基、ニトロ基などの官能基を有する材料や、ベンゾキノン誘導体、テトラシ ァノエチレン及びテトラシァノキノジメタンやそれらの誘導体などのように電子を受容 するァクセプターとなる材料や、例えばアミノ基、トリフエニル基、アルキル基、水酸基 、アルコキシ基、フエ-ル基などの官能基を有する材料、フエ-レンジァミンなどの置 換ァミン類、アントラセン、ベンゾアントラセン、置換べンゾアントラセン類、ピレン、置 換ピレン、力ルバゾール及びその誘導体、テトラチアフルバレンとその誘導体などの ように電子の供与体であるドナーとなるような材料を含有させ、 、わゆるドーピング処 理を施してもよい。  [0036] In the organic semiconductor layer, for example, a material having a functional group such as acrylic acid, acetamido, dimethylamino group, cyano group, strong lpoxyl group, nitro group, benzoquinone derivatives, tetracyanethylene and tetracyanoquinodimethane, and their A material that serves as an acceptor such as a derivative, a material having a functional group such as an amino group, a triphenyl group, an alkyl group, a hydroxyl group, an alkoxy group, or a phenyl group, or a substituted amine such as phenoldiamine. , Anthracene, benzoanthracene, substituted benzoanthracene, pyrene, substituted pyrene, force rubazole and its derivatives, tetrathiafulvalene and its derivatives, etc. In other words, a so-called doping process may be performed.
[0037] 前記ドーピングとは電子授与性分子 (ァクセプター)又は電子供与性分子 (ドナー） をドーパントとして該薄膜に導入することを意味する。従って、ドーピングが施された 薄膜は、前記の縮合多環芳香族化合物とドーパントを含有する薄膜である。ドーパン トとしては公知のものを採用することができる。 [0037] The doping is an electron-donating molecule (acceptor) or an electron-donating molecule (donor). Is introduced into the thin film as a dopant. Therefore, the doped thin film is a thin film containing the condensed polycyclic aromatic compound and the dopant. Known dopants can be used.
[0038] 基材には特に制限はな!/ヽが、榭脂材料、例えばプラスチックフィルムシートを好まし く用いることができる。前記プラスチックフィルムとしては、例えばポリエチレンテレフタ レート、ポリエチレンナフタレート、ポリエーテルスルホン、ポリエーテルイミド、ポリエ ーテルケトン、ポリフエ-レンスルフイド、ポリアタリレート、ポリイミド、ポリカーボネート 、セルローストリアセテート、セルロースアセテートプロピオネート等からなるフィルム等 があげられる。  [0038] Although there is no particular limitation on the base material! / Soot, a resin material such as a plastic film sheet can be preferably used. Examples of the plastic film include polyethylene terephthalate, polyethylene naphthalate, polyethersulfone, polyetherimide, polyetherketone, polyphenylene sulfide, polyacrylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. Film.
[0039] また、 TFTアレイは公知の半導体製造工程により製造することができる。  [0039] The TFT array can be manufactured by a known semiconductor manufacturing process.
[0040] なお、 TFT20のサイズは一辺が 20 μ m〜100 μ mの長方形又は正方形であり、ビ ット線 27、ソース線 22、ゲート線 25をはじめとするバスの線幅は 10 μ m〜30 μ mで あり、ソース分離部 23のソース電極 21とソース線 22との間隔は 10 μ m〜40 μ mであ る。 [0040] The TFT20 size is a rectangle or square with sides of 20 μm to 100 μm, and the bus line width including the bit line 27, source line 22, and gate line 25 is 10 μm. The distance between the source electrode 21 and the source line 22 of the source separation unit 23 is 10 μm to 40 μm.
[0041] 本発明の半導体装置の他の形態について図 3及び図 4を用いて説明する。  Another embodiment of the semiconductor device of the present invention will be described with reference to FIGS.
[0042] 図 3は、本発明の他の実施形態に係る半導体装置である、 TFTアレイ 66の一部の 回路図である。 FIG. 3 is a circuit diagram of a part of a TFT array 66, which is a semiconductor device according to another embodiment of the present invention.
[0043] 図 1に示した TFTアレイ 66との相違点は、図 1のソース分離部 23に代えて、本発明 の分離部に相当するドレイン分離部 41がドレイン電極 26とビット線 27との間に設けら れている点である。  A difference from the TFT array 66 shown in FIG. 1 is that, instead of the source isolation portion 23 in FIG. 1, a drain isolation portion 41 corresponding to the isolation portion of the present invention is provided between the drain electrode 26 and the bit line 27. This is the point in between.
[0044] 図 4は図 3に示した TFT20の構造図である。図 4 (a)は TFT20の平面図であり、図  FIG. 4 is a structural diagram of the TFT 20 shown in FIG. Figure 4 (a) is a plan view of TFT20.
4 (a)中の B— B断面で切断した断面図が図 4 (b)である。図 4 (c)は図 4 (b)にお!/、て TFT20のドレイン分離部 41に導電性材料 32が満たされた状態を表して 、る。  Fig. 4 (b) is a cross-sectional view taken along section B-B in Fig. 4 (a). FIG. 4 (c) shows the state in which the drain separating part 41 of the TFT 20 is filled with the conductive material 32 in FIG. 4 (b).
[0045] 本発明の構成 2及び 3に係る半導体装置の製造方法について、図 5〜図 7を用い て説明する。図 5は、本発明に係る半導体装置の製造工程の概略を示した模式図で ある。  A method for manufacturing a semiconductor device according to configurations 2 and 3 of the present invention will be described with reference to FIGS. FIG. 5 is a schematic diagram showing an outline of the manufacturing process of the semiconductor device according to the present invention.
[0046] 半導体装置の製造工程は、識別情報入力部 61、配線パターン生成部 62,インク ジェットプリンタ 63,加熱部 64,封止部 65,搬送部 67とからなり、これらの各部は図 示しな 、制御部により集中的に制御されて 、る。 [0046] The manufacturing process of the semiconductor device includes an identification information input unit 61, a wiring pattern generation unit 62, an ink jet printer 63, a heating unit 64, a sealing unit 65, and a transport unit 67. Not shown, it is controlled intensively by the control unit.
[0047] 識別情報入力部 61は、図示しない CPU (中央処理装置）、ワークメモリ、記憶部、 表示部、キーボード等の入力デバイス等力 構成され、 TFTアレイ 66に書き込まれ る IDコードや製造番号等の識別情報を生成する機能を持つ。識別情報入力部 61で 発生した識別情報は配線パターン生成部 62に送られる。  [0047] The identification information input unit 61 is composed of input devices such as a CPU (Central Processing Unit), a work memory, a storage unit, a display unit, a keyboard, etc. (not shown), and an ID code and a serial number written in the TFT array 66 And the like. The identification information generated by the identification information input unit 61 is sent to the wiring pattern generation unit 62.
[0048] 配線パターン生成部 62は、図示しない CPU (中央処理装置）、ワークメモリ、記憶 部等から構成され、識別情報入力部 61から送られた識別情報及びインクジェットプリ ンタ 63の機種情報に基づいて TFTアレイのソース分離部 23の配線パターン情報に 変換し、さらに配線パターン情報力 インクジェットプリンタ 63の図示しないヘッド、ノ ズル等への割付や吐出開始位置合わせ、吐出回数等の制御データに変換してイン クジェットプリンタ 63に転送する。  The wiring pattern generation unit 62 includes a CPU (Central Processing Unit), a work memory, a storage unit, and the like (not shown), and is based on the identification information sent from the identification information input unit 61 and the model information of the inkjet printer 63. To the wiring pattern information of the source separation unit 23 of the TFT array, and further to the control data such as allocation to the head and nozzle (not shown) of the inkjet printer 63, alignment of the ejection start position, and the number of ejections. To the Inkjet printer 63.
[0049] インクジェットプリンタ 63は、配線パターン生成部 62から転送された制御データに 基づ 、て TFTアレイ 66に図示しな 、導電性材料を塗布して、 TFTアレイ 66に導電 性材料による配線パターンを形成する。  The inkjet printer 63 applies a conductive material (not shown) to the TFT array 66 based on the control data transferred from the wiring pattern generation unit 62, and the wiring pattern of the conductive material is applied to the TFT array 66. Form.
[0050] 導電性材料として、白金、金、銀、銅、コバルト、クロム、イリジウム、ニッケル、パラジ ゥム、モリブデン、タングステンのいずれかを含有する金属粒子を含んだインクを使う ことができる。  [0050] As the conductive material, an ink containing metal particles containing any one of platinum, gold, silver, copper, cobalt, chromium, iridium, nickel, palladium, molybdenum, and tungsten can be used.
[0051] 加熱部 64は、ホットプレート、ランプアニール等からなりインク 72の溶媒を 100°C〜 300°Cで加熱、乾燥させ、金属粒子を焼成する機能を有する。  [0051] The heating unit 64 includes a hot plate, lamp annealing, and the like, and has a function of baking the metal particles by heating and drying the solvent of the ink 72 at 100 ° C to 300 ° C.
[0052] 封止部 65は、封止材料を塗布し TFTアレイを絶縁、防湿保護する機能を持つ。  The sealing portion 65 has a function of applying a sealing material to insulate and protect the TFT array from moisture.
[0053] 封止は、スプレーコート法、ブレードコート法、印刷法やインクジェット法により TFT アレイが封止材で覆われるようにする。  For sealing, the TFT array is covered with a sealing material by a spray coating method, a blade coating method, a printing method, or an ink jet method.
[0054] 封止材料としては、ポリイミド、ポリアミドポリビュルアルコール、ポリビュルフエノール 、ポリエステル、ポリアタリレートが好ましい。  [0054] As the sealing material, polyimide, polyamide polybulal alcohol, polybulfenol, polyester, and polyacrylate are preferable.
[0055] 搬送部 67は、図示しないローラー、ベルト、モーター、支持材、駆動回路等からなり 、 TFTアレイを支持搬送し、インクジェットプリンタ 63による配線パターン形成、加熱 部 64による熱処理、封止部 65による封止を連続的に行わせるようにする。  The transport unit 67 includes rollers, a belt, a motor, a support material, a drive circuit, and the like (not shown). The transport unit 67 supports and transports the TFT array, forms a wiring pattern by the ink jet printer 63, performs heat treatment by the heating unit 64, and seals 65. The sealing is performed continuously.
[0056] 図 5に示した TFTアレイ 66の製造工程の動作について、図 5及び図 6を用いて説 明する。 [0056] The operation of the manufacturing process of the TFT array 66 shown in FIG. 5 will be described with reference to FIGS. Light up.
[0057] 図 6は、図 5に示した製造工程における図 1及び図 2に示した TFT20の状態遷移を 示す断面図であり、選択的に導電性材料で分離部を接続する場合を (a— 1) , (a— 2) , (a—3)に、分離部を接続しない場合を (b— l)、 （b— 2)、 （b— 3)に示した。 実施例  FIG. 6 is a cross-sectional view showing the state transition of the TFT 20 shown in FIG. 1 and FIG. 2 in the manufacturing process shown in FIG. 5, where the separation part is selectively connected with a conductive material (a — The cases where the separator is not connected are shown in (b–l), (b–2), and (b–3) in 1), (a–2), and (a–3). Example
[0058] 以下、実施例により具体的に説明するが本発明はこれらの記載に限定されるもので はない。  [0058] Hereinafter, the present invention will be specifically described with reference to Examples, but the present invention is not limited to these descriptions.
[0059] 本実施の形態において、ソース線とソース電極との間にソース分離部を有する TFT アレイ 66を例にして説明する力 ビット線とドレイン電極との間にドレイン分離部を有 する TFTアレイ 67においては、ソース分離部に代えてドレイン分離部を電気的に接 続又は分離するように適用するものである。  In the present embodiment, the TFT array 66 having the source isolation portion between the source line and the source electrode will be described as an example. The TFT array having the drain isolation portion between the bit line and the drain electrode No. 67 is applied so that the drain isolation portion is electrically connected or isolated in place of the source isolation portion.
[0060] 図 5において、位置 POにあった TFTアレイ 66はインクジェットプリンタ 63の吐出位 置 P1まで搬送される。 （図 6 (a— 1) (b- l) ) o PIまで搬送された TFTアレイ 66はィ ンクジェットプリンタ 63によって導電性材料 (金属粒子を含有したインク 72)を配線パ ターン生成部 62から送られてきた制御データに従って、所定配線パターンを TFTァ レイのソース分離部 23に塗布される（図 6 (a— 2) )。  In FIG. 5, the TFT array 66 located at the position PO is transported to the ejection position P 1 of the ink jet printer 63. (Fig. 6 (a-1) (b-l)) o TFT array 66 transported to PI receives conductive material (ink 72 containing metal particles) from wiring pattern generator 62 by ink jet printer 63. A predetermined wiring pattern is applied to the source separation part 23 of the TFT array according to the control data sent (FIG. 6 (a-2)).
[0061] 一方、接続しない分離部にはインク 72は塗布されない（図 6 (b— 2) )。  On the other hand, the ink 72 is not applied to the separation portion that is not connected (FIG. 6 (b-2)).
[0062] ここで、インクジェットプリンタ 63によるインク 72の塗布について、図 7を用いて説明 する。図 7は、図 6のインクジェットプリンタ 63におけるインク 72が吐出される様子を示 す模式図である。  Here, application of the ink 72 by the ink jet printer 63 will be described with reference to FIG. FIG. 7 is a schematic diagram showing how the ink 72 is ejected from the ink jet printer 63 of FIG.
[0063] インクジェットプリンタ 63では、 TFTアレイ 66に、ヘッド 74からノズル 73を通ってィ ンク 72がソース分離部 23へ向けて吐出される。ここで吐出とはノズル力もインクが射 出されることを言い、塗布とは吐出されたインクが分離部に着弾した状態を言う。イン ク 72が着弾したソース分離部 23にはインク 23が満たされる。  In the inkjet printer 63, the ink 72 is ejected from the head 74 to the TFT array 66 through the nozzle 73 toward the source separation unit 23. Here, the ejection means that the ink is ejected also with the nozzle force, and the application means a state where the ejected ink has landed on the separation portion. The source separation unit 23 on which the ink 72 has landed is filled with the ink 23.
[0064] 図 5及び図 6に戻り、インクジェットプリンタ 63でインク 72が塗布された TFTアレイ 6 6は、加熱部 64 (P2)に搬送される。加熱部 64では、インクジェットプリンタ 63で塗布 されたインク 72に含まれる溶剤を加熱、乾燥し、導電性材料を焼成させることでイン ク 72が塗布された分離部 23が電気的に接続される。 [0065] 次に位置 P3に搬送された TFTアレイ 66は封止部 65 (P3)で封止材料 71を使って 封止される（図 6 (a— 3) (b— 3) )。 Returning to FIGS. 5 and 6, the TFT array 66 to which the ink 72 has been applied by the inkjet printer 63 is conveyed to the heating unit 64 (P2). In the heating unit 64, the solvent contained in the ink 72 applied by the ink jet printer 63 is heated and dried, and the conductive material is baked to electrically connect the separation unit 23 to which the ink 72 has been applied. Next, the TFT array 66 transported to the position P3 is sealed with the sealing material 71 at the sealing portion 65 (P3) (FIGS. 6 (a-3) (b-3)).
[0066] なお、本実施の形態において、識別情報として IDコードや製造番号等を用い、識 別情報に基づく配線パターンで TFTアレイ 66の各分離部を接続するようにしたが、 識別情報として、図示しな 、デジタルスチルカメラやスキャナ等の画像取り込み装置 で取得された顔写真やロゴマーク、指紋等の画像情報を用い、画像様の配線パター ンで TFTアレイ 66の各分離部を接続するようにしてもよい。このようにすることで、画 像様の配線パターンを有する TFTアレイ 66から出力される信号を、当該 TFTアレイ 66が組み込まれた電子装置の識別情報とすることができ、ワンタイムパスワードや時 間制限付きカードキー等の一時利用を目的とした識別情報の発行において、改ざん や偽造がされにくい識別情報の発行を容易に行うことが可能になるとともに、画像様 の配線パターンを視認することが容易であるので、なりすまし等の不正利用も防止で きる。  [0066] In the present embodiment, an ID code or a serial number is used as identification information, and each separation part of TFT array 66 is connected with a wiring pattern based on the identification information. However, as identification information, Not shown, using the image information such as a face photograph, logo mark, fingerprint, etc. acquired by an image capture device such as a digital still camera or scanner, and connecting each separation part of the TFT array 66 with an image-like wiring pattern It may be. In this way, a signal output from the TFT array 66 having an image-like wiring pattern can be used as identification information of an electronic device in which the TFT array 66 is incorporated, and a one-time password or time When issuing identification information for temporary use such as restricted card keys, it is possible to easily issue identification information that is not easily altered or counterfeited, and it is easy to visually check the wiring pattern of the image. Therefore, unauthorized use such as impersonation can be prevented.
[0067] また、インクジェットプリンタ 63によるインク 72の塗布において、ソース分離部 23に 塗布されるインク 72の量は、入力される識別情報に基づいて、段階的に変更される ようにしてもよい。塗布されるインク 72の量の変更は、公知の面積階調画像形成方法 によってソース分離部 23を覆う面積を変更したり、公知の重ね打ち画像形成方法に よって、ソース分離部 23を覆うインク 72の厚みを変更したりする。  [0067] Further, in the application of the ink 72 by the ink jet printer 63, the amount of the ink 72 applied to the source separation unit 23 may be changed stepwise based on the input identification information. The amount of the ink 72 to be applied is changed by changing the area covering the source separation unit 23 by a known area gradation image forming method, or changing the area covering the source separation unit 23 by a known overlaid image forming method. Or change the thickness.
[0068] 本発明の構成 2及 3に係る半導体装置の製造方法の他の形態について図 8及び図 9を用いて説明する。  Another embodiment of the semiconductor device manufacturing method according to configurations 2 and 3 of the present invention will be described with reference to FIGS.
[0069] 図 8は、本発明に係る半導体装置の製造工程の概略を示した模式図である。  FIG. 8 is a schematic diagram showing an outline of the manufacturing process of the semiconductor device according to the present invention.
[0070] 半導体装置の製造工程は、図 5で説明した製造工程において、加熱部 64と封止部[0070] The manufacturing process of the semiconductor device includes a heating unit 64 and a sealing unit in the manufacturing process illustrated in FIG.
65の間に導電性材料供給部 80を追加したものである。 A conductive material supply unit 80 is added between 65.
[0071] 配線パターン生成部 62は、識別情報入力部 61から送られた識別情報を、パターン 情報に変換して、さらに配線パターン情報力も制御データを生成してインクジェットプ リンタ 63に転送する。 The wiring pattern generation unit 62 converts the identification information sent from the identification information input unit 61 into pattern information, further generates control data for the wiring pattern information power, and transfers the control data to the inkjet printer 63.
[0072] インクジェットプリンタ 63は、配線パターン生成部 62から転送された制御データに 基づ 、て TFTアレイに後述する絶縁性材料を吐出して、 TFTアレイ 66に絶縁性材 料による配線パターンを形成する。 The inkjet printer 63 discharges an insulating material, which will be described later, to the TFT array on the basis of the control data transferred from the wiring pattern generation unit 62, and the insulating material to the TFT array 66. A wiring pattern is formed using a material.
[0073] 絶縁性材料としては、ポリイミド、ポリアミドポリビュルアルコール、ポリビュルフエノー ル、ポリエステル、ポリアタリレート等を含むインクを使うことができる。  [0073] As the insulating material, it is possible to use an ink containing polyimide, polyamide polybulal alcohol, polybuluphenol, polyester, polyacrylate, or the like.
[0074] 導電性材料供給部 80は、 TFTアレイの全面に前述の流動性導電材料を塗布した り、 TFTアレイの全面に導電性シートやアルミ箔を密着させることで、インクジェットプ リンタ 63で絶縁性材料 81が塗布されて ヽな 、ソース分離部 23を電気的に接続する 機能を有する。予めインクジェットプリンタ 63によって絶縁性材料でソース分離部 23 を塗布して 、るので、絶縁性材料 81が塗布されて 、な ヅース分離部だけが導電性 シートやアルミ箔で接続される。  [0074] The conductive material supply unit 80 is insulated by the inkjet printer 63 by applying the above-described fluid conductive material to the entire surface of the TFT array, or by bringing a conductive sheet or aluminum foil into close contact with the entire surface of the TFT array. It has a function of electrically connecting the source separation part 23 when the material 81 is applied. Since the source separation part 23 is coated with an insulating material in advance by the ink jet printer 63, the insulating material 81 is applied and only the base separation part is connected with a conductive sheet or aluminum foil.
[0075] 図 9は、図 8に示した製造工程における図 1及び図 2に示した TFT20の状態遷移を 示す断面図であり、選択的に絶縁性材料 81でソース分離部 23を塗布する場合を (d — 1) , (d- 2) , (d- 3) , (d— 4)に、ソース分離部 23を塗布しない場合を (c 1) , ( c- 2) , (b- 3) , (c 4)に示した。  FIG. 9 is a cross-sectional view showing the state transition of the TFT 20 shown in FIGS. 1 and 2 in the manufacturing process shown in FIG. 8, where the source separation portion 23 is selectively applied with an insulating material 81. When (d 1), (d-2), (d-3), (d-4) are not coated with the source separator 23, (c 1), (c-2), (b-3) ) and (c 4).
[0076] 位置 POにあった TFTアレイ 66はインクジェットプリンタ 63の吐出位置 P1まで搬送 される。 (図 9 (c 1) (d- 1) )  The TFT array 66 at the position PO is transported to the ejection position P 1 of the ink jet printer 63. (Fig. 9 (c 1) (d- 1))
次に、インクジェットプリンタ 63では絶縁性材料 81を配線パターン生成部 62から送 られてきた制御データに従って、所定配線パターンを TFTアレイ 66のソース分離部 23に塗布する（図 9 (d— 2) )。  Next, in the inkjet printer 63, a predetermined wiring pattern is applied to the source separation unit 23 of the TFT array 66 in accordance with the control data sent from the wiring pattern generation unit 62 (FIG. 9 (d-2)). .
[0077] TFTアレイ 66のソース分離部 23に塗布しない場合はソース分離部 23は分離され た状態を保つ（図 9 (c 2) )。  [0077] When not applied to the source separation portion 23 of the TFT array 66, the source separation portion 23 remains separated (Fig. 9 (c2)).
[0078] 位置 P2に搬送された TFTアレイ 66は加熱、乾燥、焼成後、位置 P3で導電性シー トゃアルミ箔等の導電性材料 82で密着される。  [0078] The TFT array 66 transported to the position P2 is heated, dried, and baked, and then adhered to the position P3 with a conductive material 82 such as a conductive sheet or aluminum foil.
[0079] 絶縁性材料 81が塗布されたソース分離部 23は、絶縁性材料 81で満たされている ので電気的に絶縁された状態を保つ（図 9 (d- 3) )が、絶縁性材料 81が塗布されて Vヽな ヅース分離部 23は、導電性シートやアルミ箔である導電性材料 82で電気的 に接続される（図 9 (c 3) )。  [0079] Since the source separation portion 23 coated with the insulating material 81 is filled with the insulating material 81, it remains electrically insulated (Fig. 9 (d-3)). 81 is applied and the V-shaped separation part 23 is electrically connected by a conductive material 82 such as a conductive sheet or aluminum foil (FIG. 9 (c 3)).
[0080] さらに位置 P4に搬送された TFTアレイ 66は封止部 65で絶縁シート 83等の封止材 料で封止される（図 9 (c 4) (d-4) ) G [0081] なお、本実施の形態においても、識別情報として顔写真やロゴマーク等の画像情 報を用い、画像様の配線パターンで TFTアレイ 66の各分離部を接続するようにして もよ！/、ことは言うまでもな！/、。 [0080] Further, the TFT array 66 transported to the position P4 is sealed with a sealing material such as an insulating sheet 83 at the sealing portion 65 (Fig. 9 (c 4) (d-4)) G [0081] In this embodiment, image information such as a face photograph or logo mark may be used as identification information, and each separation part of the TFT array 66 may be connected with an image-like wiring pattern! / Needless to say! /.
[0082] 本発明の構成 2又は 3に係る半導体装置である TFTROM (Read Only Memor y) 100の動作について図 10を用いて説明する。 The operation of TFT ROM (Read Only Memory) 100 which is a semiconductor device according to Configuration 2 or 3 of the present invention will be described with reference to FIG.
[0083] 図 10は、図 1に示した TFTアレイ 66を使用した TFTROM100の概念を模式的に 示す回路図である。なお、図 3に示した TFTアレイ 67を TFTROM100に用いる場 合にも同様の構成となる。 FIG. 10 is a circuit diagram schematically showing the concept of the TFTROM 100 using the TFT array 66 shown in FIG. The same configuration is used when the TFT array 67 shown in FIG.
[0084] TFTROM100は、 TFTアレイ 66、 ROWデコーダ 551、 COLUMNデコーダ 552[0084] TFTROM100 consists of TFT array 66, ROW decoder 551, COLUMN decoder 552
、出力バッファ 53、抵抗 52からなる。 Output buffer 53 and resistor 52.
[0085] TFTアレイ 66は、図 1に示した TFTアレイ 66と同じ構成を有し、マトリックス状に並 ベられた TFT201〜TFT205、ゲート線 251〜253、ビット線 27、ソース線 221〜2[0085] The TFT array 66 has the same configuration as the TFT array 66 shown in FIG. 1, and is arranged in a matrix form TFT201 to TFT205, gate lines 251 to 253, bit lines 27, source lines 221 to 2
24、ソース分離部 23を有する。 24 and source separation unit 23.
[0086] TFTROM100は、 2次元に並べられた記憶素子に予めデータが書き込まれてい て、電源の供給をー且切っても内容は消えない。行方向と列方向のアドレス線で素 子をアクセスする。アクセスされた記憶素子はその内容を出力する。 The TFTROM 100 has data written in advance in storage elements arranged in two dimensions, and the contents are not lost even if the power supply is turned off and on. The device is accessed using the address lines in the row and column directions. The accessed storage element outputs its contents.
[0087] TFT201〜 205は図 1で前述した TFT20である。 TFTs 201 to 205 are the TFTs 20 described above with reference to FIG.
[0088] ROWデコーダ 551及び COLUMNデコーダ 552は、図示しない外部回路からの 2 進数のアドレス信号入力を復号する回路である。  The ROW decoder 551 and the COLUMN decoder 552 are circuits that decode binary address signal input from an external circuit (not shown).
[0089] ゲート線 251〜253は、 ROMのアドレス線であり、ゲート電極 24を X行方向に連結 して ROWデコーダ 551の出力に接続されて!、る。 The gate lines 251 to 253 are ROM address lines, and are connected to the output of the ROW decoder 551 by connecting the gate electrodes 24 in the X row direction.
[0090] ソース線 221〜224は、 TFTROM 100のアドレス線であり、 COLUMNデコーダ 5[0090] The source lines 221 to 224 are the TFTROM 100 address lines, and the COLUMN decoder 5
52の出力に接続されている。 Connected to 52 outputs.
[0091] ビット線 27は、 ROMのデータ線であり、すべてのドレイン電極 26を連結してバッフ ァ 53の入力に接続されて!、る。 [0091] The bit line 27 is a ROM data line, and is connected to the input of the buffer 53 by connecting all the drain electrodes 26 !.
[0092] 抵抗 52は、一方が電源 VDD51に、他方がビット線 27に接続されている。ビット線 がハイインピーダンスの場合、抵抗 52は、 VDD電位に保っためのプルアップ抵抗と して機能する。 [0093] バッファ 53は、 TFT201〜205の出力であるビット線 27の電圧を外部回路にマツ チングさせるための電圧レベル変換 IC (集積回路)である。 One of the resistors 52 is connected to the power supply VDD 51 and the other is connected to the bit line 27. When the bit line is high impedance, the resistor 52 functions as a pull-up resistor to maintain the VDD potential. The buffer 53 is a voltage level conversion IC (integrated circuit) for causing the external circuit to match the voltage of the bit line 27 that is the output of the TFTs 201 to 205.
[0094] ソース線 221〜223は、一方はソース分離部 23に、もう一方は COLUMNデコー ダ 552の出力に接続されて!、る。 One of the source lines 221 to 223 is connected to the source separator 23 and the other is connected to the output of the COLUMN decoder 552 !.
[0095] 次に、 ROMの動作について説明する。図示しない外部回路からの ROWアドレス 信号入力により、 ROWデコーダ 551の出力のいずれ力 1本のゲート線がイネ一ブルNext, the operation of the ROM will be described. ROW address signal input from an external circuit (not shown) enables one of the outputs of the ROW decoder 551 to be enabled.
(有効）になる。ゲート線 251がイネ一ブルになった場合、イネ一ブルになったゲート 線 251に繋がる TFT201〜204のソース電極 21とドレイン電極 26間が ON状態にな る。他のゲート線 252、 253に繋がる TFTは OFF状態になる。 (validate. When the gate line 251 is enabled, the source electrode 21 and the drain electrode 26 of the TFTs 201 to 204 connected to the enabled gate line 251 are turned on. TFTs connected to other gate lines 252 and 253 are turned off.
[0096] 同様に、外部回路からの COLUMNアドレス信号入力により COLUMNデコーダ 5[0096] Similarly, the COLUMN decoder 5 receives a COLUMN address signal input from an external circuit.
52に接続されたソース線 221〜224のうち、いずれ力 1本のソース線がイネ一ブルに なる。 Of the source lines 221 to 224 connected to 52, one source line will be enabled.
[0097] ソース線 221がイネ一ブルになると、 COLUMNデコーダ 552は、ソース線 221を はロウ（LOW電位）、他のソース線 222〜224をハイ（HI電位）とする。  When the source line 221 is enabled, the COLUMN decoder 552 sets the source line 221 to low (LOW potential) and the other source lines 222 to 224 to high (HI potential).
[0098] ソース線 221がロウになると、 TFT201に繋がるソース分離部 23が導電性材料 32 で接続されているので、電源 VDD51から抵抗 52、ビット線 27、 TFT201、ソース線 221を経由して COLUMNデコーダ 552の出力に電流が流れ、 TFT201と接続され たビット線 27もロウになる。ビット線 27の電位は出力バッファ 53で電圧変換されて外 部回路への出力 54はロウとなる。なお、他のソース線 222〜224はハイであるので、 TFT202〜204のドレイン、ソース間には電流は流れない。  [0098] When the source line 221 goes low, the source isolation part 23 connected to the TFT 201 is connected by the conductive material 32, so that the COLUMN is connected from the power source VDD51 via the resistor 52, bit line 27, TFT201, and source line 221. A current flows through the output of the decoder 552, and the bit line 27 connected to the TFT 201 also goes low. The potential of the bit line 27 is converted by the output buffer 53, and the output 54 to the external circuit becomes low. Since the other source lines 222 to 224 are high, no current flows between the drains and sources of the TFTs 202 to 204.
[0099] 一方、 ROWアドレス信号によって TFT202が選択され、 COLUMNアドレス信号 によってソース線 202がロウとした場合、 TFT202のソース分離部 23は導電材料 32 で接続されていないので、電源 VDD51からビット線 27、 TFT202,ソース線 202経 由で COLUMNデコーダ 552の出力には電流が流れず、ビット線 27は電源 VDD51 と同電位を保つ。したがって、ビット線 27の電位はハイとなり、出力バッファ 53で電圧 変換されて外部回路への出力 54はハイとなる。  On the other hand, when the TFT 202 is selected by the ROW address signal and the source line 202 is made low by the COLUMN address signal, the source separation part 23 of the TFT 202 is not connected by the conductive material 32, and therefore the bit line 27 from the power supply VDD 51 The current does not flow to the output of the COLUMN decoder 552 via the TFT 202 and the source line 202, and the bit line 27 maintains the same potential as the power supply VDD51. Therefore, the potential of the bit line 27 becomes high, the voltage is converted by the output buffer 53, and the output 54 to the external circuit becomes high.
[0100] このように、外部回路からの ROWアドレス信号と COLUMNアドレス信号によって T FT201〜205のうちどれ力 1つの TFTが選択され、選択された TFTに繋がるソース 分離部 23が導電性材料で接続されいる場合は外部回路への出力はロウ、接続され て ヽな ヽ場合はハイになる。 [0100] In this way, one of the TFTs 201 to 205 is selected by the ROW address signal and the COLUMN address signal from the external circuit, and the source connected to the selected TFT. When the separator 23 is connected with a conductive material, the output to the external circuit is low, and when it is connected, it is high.
[0101] 図 10に示した TFTROM100の 1回の読み出し動作に係る出力データは 1ビットで ある。 1回の読み出し動作で複数ビットの出力データを得たい場合、出力データのビ ット数と同じ数の TFTアレイ 66を COLUMNデコーダ 552及び ROWデコーダ 551 に対して並列に接続すればよ!、。  [0101] The output data related to one read operation of the TFTROM 100 shown in FIG. 10 is 1 bit. To obtain multiple bits of output data in a single read operation, connect as many TFT arrays 66 as the number of output data bits to the COLUMN decoder 552 and ROW decoder 551 in parallel!
[0102] なお、半導体装置の製造工程において、ソース分離部 23に塗布されるインク 72の 量が、入力される識別情報に基づいて、段階的に変更されるようにした場合は、ソー ス分離部 23を接続する導電性材料の量によって、出力される信号強度が異なり、 1 つの TFTにおいて多値の信号を取り扱うことが可能となる。この場合、 ROWデコー ダ 551、 COLUMNデコーダ 552及び出力バッファ 53は多値の信号が取り扱えるよ うに、信号強度が検出できる構成となる。  [0102] In the semiconductor device manufacturing process, if the amount of ink 72 applied to the source separation unit 23 is changed stepwise based on the input identification information, the source separation is performed. Depending on the amount of the conductive material that connects part 23, the output signal strength differs, and it becomes possible to handle multi-value signals in one TFT. In this case, the ROW decoder 551, the COLUMN decoder 552, and the output buffer 53 are configured to detect the signal strength so that a multilevel signal can be handled.
[0103] 本発明に係る電子装置について、図 11及び図 12を用いて説明する。  An electronic device according to the present invention will be described with reference to FIG. 11 and FIG.
[0104] 図 11は、 TFTROM100を搭載した RFIDカード 9の電気的ブロック図である。ここ では複数の TFTROM 100を並列に接続した TFTROM 101を使つて複数ビットの 出力データを 1回の読み出し動作で得られるようにした。  FIG. 11 is an electrical block diagram of the RFID card 9 on which the TFTROM 100 is mounted. In this example, TFTROM 101, which has a plurality of TFTROMs 100 connected in parallel, can be used to obtain multiple bits of output data in a single read operation.
[0105] RFIDカード 9は、で前述した図 13の RFIDカードとはメモリ回路 98の構成が異なる  [0105] The configuration of the memory circuit 98 of the RFID card 9 is different from that of the RFID card of Fig. 13 described above.
[0106] メモリ回路 98は、 EEPROM99と TFTROM101からなる。 EEPROM99はリード Zライトメモリであり、 TFTROM101は読み出し専用メモリである。制御プログラムや 一時記憶するデータは EEPROM99で書き込みや読み出しが行われ、 TFTROM1 01には IDコードが書き込まれる。 TFTROM101は容易に書き換えができないので 改ざんや偽造を防止するセキュリティ性力 いシステムの実現が可能となる。 The memory circuit 98 includes an EEPROM 99 and a TFT ROM 101. EEPROM99 is a read Z write memory and TFTROM101 is a read only memory. The control program and temporarily stored data are written and read by EEPROM99, and the ID code is written to TFTROM101. Since TFTROM101 cannot be easily rewritten, it is possible to realize a system with high security that prevents tampering and counterfeiting.
[0107] 図 12は、 RFIDカード 9の構成を示す外観斜視図である。  FIG. 12 is an external perspective view showing the configuration of the RFID card 9.
[0108] コイル 92は、基板 90上に渦巻き状に形成されたプリント配線等により構成される。 I C91には、図 11における電源電圧発生用の整流器 93、電源回路 94、コイルから取 り込まれたデータを復調する復調回路 95、データを外部へコイルを介して発信する 変調回路 96、データのやり取りやコマンドのやり取りなどを制御する制御回路 97及 びメモリ回路の一部である EEPROM99が含まれている。 TFTROM101は IC91に 接続されている。 TFTROM101を IC91に内蔵しないことで IDコードを客先などで 物理的に書き込むことが可能となる。 [0108] The coil 92 is configured by a printed wiring or the like formed in a spiral shape on the substrate 90. The IC 91 includes a rectifier 93 for generating a power supply voltage in FIG. 11, a power supply circuit 94, a demodulation circuit 95 for demodulating data captured from the coil, a modulation circuit 96 for transmitting data to the outside via the coil, data Control circuit 97 that controls the exchange of commands and commands, etc. And EEPROM99, which is part of the memory circuit. TFTROM101 is connected to IC91. Since the TFTROM101 is not built in the IC91, the ID code can be physically written by the customer.
[0109] RFIDカード 9の TFTROM101への情報書き込みは、 TFTROM101が RFID力 ード 9に装着された状態で、図 4〜図 9に示した方法で配線パターンが生成されるよう にすることが好ましい。このようにすることで、改ざんや偽造がされにくい RFIDカード 9を、容易かつ迅速に作成することが可能となる。  [0109] For writing information to the TFT ROM 101 of the RFID card 9, it is preferable that the wiring pattern is generated by the method shown in FIGS. 4 to 9 in a state where the TFT ROM 101 is mounted on the RFID force card 9. . In this way, it is possible to easily and quickly create the RFID card 9 that is not easily tampered with or counterfeited.
[0110] なお、 RFIDカード 9の TFTROM101への情報書き込みは、図 4〜図 9に示した方 法に代えて、指紋や掌紋、鼻紋等のバイオメトリタス情報を直接、導電性材料にて TF TROM101を構成する TFTアレイ 66に転写することも可能である。  [0110] Note that the information writing to the TFTROM 101 of the RFID card 9 is performed by directly using biometrics information such as fingerprints, palm prints, and nose prints using a conductive material instead of the method shown in FIGS. It is also possible to transfer to the TFT array 66 constituting the TF TROM101.
[0111] すなわち本実施の形態に係る電子装置は、基材上に、ゲート電極と、ゲート絶縁層 と、半導体層で連結されたソース電極及びドレイン電極とを有する複数の薄膜トラン ジスタと、複数の前記ゲート電極を連結するゲート線と、前記ソース電極を連結するソ ース線と、前記ドレイン電極を連結するビット線とを有する薄膜トランジスタアレイを有 する半導体装置を有する電子装置の識別情報発行方法であって、予め接続が分離 された、前記ソース電極と前記ソース線との接続及び前記ドレイン電極と前記ビット線 との接続から選ばれる一方の接続を分離する分離部を、像様の導電性材料で接続 する接続工程と、前記接続工程で接続された半導体装置から出力される信号を識別 情報とする工程とを含むことを特徴とする電子装置の識別情報発行方法を構成可能 である。  That is, the electronic device according to the present embodiment includes a plurality of thin film transistors including a gate electrode, a gate insulating layer, a source electrode and a drain electrode connected by a semiconductor layer, and a plurality of thin film transistors on a substrate. An identification information issuing method for an electronic device having a semiconductor device having a thin film transistor array having a gate line connecting the gate electrodes, a source line connecting the source electrodes, and a bit line connecting the drain electrodes A separation portion for separating one connection selected from a connection between the source electrode and the source line and a connection between the drain electrode and the bit line, the connection of which has been previously separated, and an image-like conductivity An electronic device identification comprising: a connection step of connecting with a material; and a step of using a signal output from the semiconductor device connected in the connection step as identification information Broadcast issuing method it is possible to configure the.
[0112] 上記方法によれば、 TFTアレイ 66に転写された指紋や掌紋、鼻紋等の像様の導 電性材料が TFTアレイ 66の特定の分離部を電気的に接続するようになる。このよう にすることで、画像様の配線パターンを有する TFTアレイ 66から出力される信号を、 当該 TFTアレイ 66が組み込まれた電子装置の識別情報とすることができ、ワンタイム パスワードや時間制限付きカードキー等の一時利用を目的とした識別情報の発行に おいて、改ざんや偽造がされにくい識別情報の発行を容易に行うことが可能になると ともに、画像様のノ ィオメトリタス情報を視認することが容易であるので、なりすまし等 の不正利用も防止できる。 [0113] なお、上記の各実施の形態における記述内容は、本発明に係る半導体装置及び 電子装置の好適な一例であり、これに限定されるものではない。 [0112] According to the above method, the image-like conductive material such as fingerprints, palm prints, and nose prints transferred to the TFT array 66 electrically connects specific separation portions of the TFT array 66. In this way, the signal output from the TFT array 66 having an image-like wiring pattern can be used as the identification information of the electronic device in which the TFT array 66 is incorporated, with a one-time password or time limit. When issuing identification information for the purpose of temporary use, such as card keys, it is possible to easily issue identification information that is not easily tampered with or counterfeited, and it is possible to visually recognize image-like metric information. Since it is easy, unauthorized use such as impersonation can also be prevented. Note that the description content in each of the above embodiments is a preferred example of the semiconductor device and the electronic device according to the present invention, and the present invention is not limited to this.
[0114] 例えば、本実施の形態において、電子装置として RFIDカードを例にとり説明した 力 RFIDタグ、携帯電話機や PDA (Personal Digital Assistant)、デジタルス チルカメラ等の電子装置に対しても適用可能である。 [0114] For example, in the present embodiment, the description has been given by taking an RFID card as an example of an electronic device. The present invention is also applicable to an electronic device such as a RFID tag, a mobile phone, a PDA (Personal Digital Assistant), or a digital still camera. .
[0115] その他、半導体装置及びその製造方法、並びに電子装置を構成する各構成の細 部構成及び細部動作に関しても、本発明の趣旨を逸脱することのない範囲で適宜変 更可能である。 In addition, the semiconductor device and the manufacturing method thereof, and the detailed configuration and detailed operation of each component constituting the electronic device can be changed as appropriate without departing from the scope of the present invention.
産業上の利用可能性  Industrial applicability
[0116] 構成 1〜3によれば、ソース電極とソース線間もしくはドレイン電極とビット線間のど ちらか一方に分離部を設け、該分離部を導電性材料で接続するので、電子装置に 内蔵している基板に搭載された状態で分離部の接続が可能である。 [0116] According to Configurations 1 to 3, the separation part is provided between one of the source electrode and the source line or between the drain electrode and the bit line, and the separation part is connected by a conductive material. The separation part can be connected in a state of being mounted on the substrate.
[0117] しカゝも、分離部は導電性材料で接続されるので電気的に書き変えられたり、消去さ れることがない。 [0117] However, since the separation part is connected with a conductive material, it is not electrically rewritten or erased.
[0118] 構成 4によれば，入力工程で入力された配線パターンに基づき、分離部を流動性 導電材料で接続するので、フォトリソグラフィ一のごとく大規模な製造工程が不要とな り、工程が単純で原材料も少なくてすみ、手間がカゝからず低コストで提供することが 可能となる。  [0118] According to Configuration 4, since the separation part is connected with the fluid conductive material based on the wiring pattern input in the input process, a large-scale manufacturing process as in photolithography is not necessary, and the process It is simple and requires less raw materials, and it can be provided at low cost with little effort.
[0119] 構成 5によれば、分離部の接続力インクジェット方式によって行われるのでフォトリソ グラフィ一のごとく大規模な工程が不要であり、高精度、高精細なパターンに対して 塗布が可能となる。  [0119] According to Configuration 5, since it is performed by the connection force ink jet system of the separation unit, a large-scale process is not required as in photolithography, and coating can be performed on a high-precision and high-definition pattern.
[0120] 構成 6によれば、入力工程で入力された配線パターンに基づき絶縁する分離部を 流動性絶縁材料で絶縁したのち、他の分離部を導電材料で接続するので、すべて の分離部が導電材料あるいは絶縁材料で密閉されるので、その後、例えば TFTァレ ィ全体を封止するとしても封止材料が直接、電極に接することはなぐ封止材料の選 定にお 、て選択肢の幅が広がる。  [0120] According to Configuration 6, since the isolation part that is insulated based on the wiring pattern input in the input process is insulated with the fluid insulating material, and the other isolation part is connected with the conductive material, all the isolation parts are connected. Since it is hermetically sealed with a conductive material or an insulating material, after that, for example, even if the entire TFT array is sealed, there is a wide range of options in selecting a sealing material that does not directly contact the electrode. Spread.
[0121] 構成 7によれば、分離部の絶縁がインクジェット方式によっておこなわれるのでフォ トリソグラフィーのごとく大規模な工程が不要であり、高精度、高精細なパターンに対 して塗布が可能となる。 [0121] According to Configuration 7, since the separation part is insulated by the ink jet method, a large-scale process is not required as in photolithography, and high-precision, high-definition patterns can be used. Application becomes possible.
[0122] 構成 8によれば、分離部が接続された薄膜トランジスタアレイを封止材料により封止 するので、物理的外乱の影響を受けにくぐ書き込まれた情報の意図的改ざん防止 に有効となる。  [0122] According to Configuration 8, since the thin film transistor array to which the separation portion is connected is sealed with the sealing material, it is effective in preventing intentional alteration of written information that is difficult to be affected by physical disturbance.
[0123] 構成 9によれば、電子装置の記憶手段が本発明に係る製造方法で製造された半導 体であるので、物理的外乱の影響を受けにくぐ記憶手段に書きこまれる識別情報の 意図的改ざんが行われにくい電子装置を手間力からず低コストで提供することが可 能となる。  [0123] According to Configuration 9, since the storage means of the electronic device is a semiconductor manufactured by the manufacturing method according to the present invention, the identification information written in the storage means that is not easily affected by physical disturbances. This makes it possible to provide electronic devices that are difficult to be intentionally tampered with at low cost with little effort.

Claims

請求の範囲 The scope of the claims
[1] 基材上に、ゲート電極と、ゲート絶縁層と、半導体層で連結されたソース電極及びド レイン電極とを有する複数の薄膜トランジスタと、複数の前記ゲート電極を連結するゲ ート線と、前記ソース電極を連結するソース線と、前記ドレイン電極を連結するビット 線とを有する薄膜トランジスタアレイを有する半導体装置であって、前記ソース電極と 前記ソース線との接続及び前記ドレイン電極と前記ビット線との接続の少なくとも一方 の接続が分離されており、かつ導電性材料で接続可能な分離部を有することを特徴 とする半導体装置。  [1] A plurality of thin film transistors having a gate electrode, a gate insulating layer, a source electrode and a drain electrode connected by a semiconductor layer on a substrate, and a gate line connecting the plurality of gate electrodes. A semiconductor device having a thin film transistor array having a source line connecting the source electrode and a bit line connecting the drain electrode, the connection between the source electrode and the source line, and the drain electrode and the bit line A semiconductor device comprising: a separation portion that is separated from at least one of the connections and connected with a conductive material.
[2] 基材上に、ゲート電極と、ゲート絶縁層と、半導体層で連結されたソース電極及びド レイン電極とを有する複数の薄膜トランジスタと、複数の前記ゲート電極を連結するゲ ート線と、前記ソース電極を連結するソース線と、前記ドレイン電極を連結するビット 線とを有する薄膜トランジスタアレイを有する半導体装置の製造方法において、前記 薄膜トランジスタアレイの配線パターンを入力する入力工程と、前記入力工程で入力 された配線パターンに基づき、予め接続が分離された前記ソース電極と前記ソース 線間の分離部を導電性材料で接続する接続工程とを含むことを特徴とする半導体装 置の製造方法。  [2] A plurality of thin film transistors having a gate electrode, a gate insulating layer, a source electrode and a drain electrode connected by a semiconductor layer on a substrate, and a gate line connecting the plurality of gate electrodes. In the method of manufacturing a semiconductor device having a thin film transistor array having a source line connecting the source electrode and a bit line connecting the drain electrode, an input step of inputting a wiring pattern of the thin film transistor array; and A method for manufacturing a semiconductor device, comprising: a connection step of connecting a separation portion between the source electrode and the source line, the connection of which is separated in advance based on an inputted wiring pattern, with a conductive material.
[3] 基材上に、ゲート電極と、ゲート絶縁層と、半導体層で連結されたソース電極及びド レイン電極とを有する複数の薄膜トランジスタと、複数の前記ゲート電極を連結するゲ ート線と、前記ソース電極を連結するソース線と、前記ドレイン電極を連結するビット 線とを有する薄膜トランジスタアレイを有する半導体装置の製造方法において、前記 薄膜トランジスタアレイの配線パターンを入力する入力工程と、前記入力工程で入力 された配線パターンに基づき、予め接続が分離された前記ドレイン電極と前記ビット 線間の分離部を、導電性材料で接続する接続工程とを含むことを特徴とする半導体 装置の製造方法。  [3] A plurality of thin film transistors having a gate electrode, a gate insulating layer, a source electrode and a drain electrode connected by a semiconductor layer on a base material, and a gate line connecting the plurality of gate electrodes. In the method of manufacturing a semiconductor device having a thin film transistor array having a source line connecting the source electrode and a bit line connecting the drain electrode, an input step of inputting a wiring pattern of the thin film transistor array; and A method of manufacturing a semiconductor device, comprising: a connection step of connecting a separation portion between the drain electrode and the bit line, the connection of which has been previously separated based on an inputted wiring pattern, with a conductive material.
[4] 前記接続工程は、前記入力工程で入力された配線パターンに基づき、接続する前 記分離部を流動性導電材料で接続することを特徴とする請求の範囲第 2項に記載の 半導体装置の製造方法。  [4] The semiconductor device according to claim 2, wherein, in the connection step, the separation part to be connected is connected with a fluid conductive material based on the wiring pattern input in the input step. Manufacturing method.
[5] 前記接続工程は、前記入力工程で入力された配線パターンに基づき、接続する前 記分離部を流動性導電材料で接続することを特徴とする請求の範囲第 3項に記載の 半導体装置の製造方法。 [5] The connection step is based on the wiring pattern input in the input step and before the connection. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the separating portions are connected with a fluid conductive material.
[6] 前記分離部の流動性導電材料による接続は、インクジェット方式により、前記流動 性導電材料が前記分離部に塗布されることを特徴とする請求の範囲第 4項に記載の 半導体装置の製造方法。  [6] The semiconductor device manufacturing according to claim 4, wherein the connection of the separation part with the fluid conductive material is applied to the separation part by an inkjet method. Method.
[7] 前記分離部の流動性導電材料による接続は、インクジェット方式により、前記流動 性導電材料が前記分離部に塗布されることを特徴とする請求の範囲第 5項に記載の 半導体装置の製造方法。  [7] The semiconductor device manufacturing according to claim 5, wherein the connection of the separation part with the fluid conductive material is applied to the separation part by an inkjet method. Method.
[8] 前記接続工程は、前記入力工程で入力された配線パターンに基づき、絶縁する前 記分離部を流動性絶縁材料で絶縁した後、他の前記分離部を導電性材料で接続す ることを特徴とする請求の範囲第 2項に記載の半導体装置の製造方法。  [8] In the connecting step, after isolating the separating portion to be insulated with a fluid insulating material based on the wiring pattern inputted in the input step, the other separating portion is connected with a conductive material. 3. The method of manufacturing a semiconductor device according to claim 2, wherein:
[9] 前記接続工程は、前記入力工程で入力された配線パターンに基づき、絶縁する前 記分離部を流動性絶縁材料で絶縁した後、他の前記分離部を導電性材料で接続す ることを特徴とする請求の範囲第 3項に記載の半導体装置の製造方法。  [9] In the connecting step, after isolating the separating portion to be insulated with a fluid insulating material based on the wiring pattern inputted in the input step, the other separating portion is connected with a conductive material. The method for manufacturing a semiconductor device according to claim 3, wherein:
[10] 前記分離部の流動性絶縁材料による絶縁は、インクジェット方式により、前記流動 性絶縁材料が前記分離部に塗布されることを特徴とする請求の範囲第 8項に記載の 半導体装置の製造方法。  10. The semiconductor device manufacturing according to claim 8, wherein the isolation of the separation part with the fluid insulating material is applied to the isolation part by an ink jet method. Method.
[11] 前記分離部の流動性絶縁材料による絶縁は、インクジェット方式により、前記流動 性絶縁材料が前記分離部に塗布されることを特徴とする請求の範囲第 9項に記載の 半導体装置の製造方法。  [11] The semiconductor device manufacturing according to claim 9, wherein the fluid insulating material is applied to the separator by an ink jet method for the isolation of the separator by the fluid insulating material. Method.
[12] 前記分離部が接続された薄膜トランジスタアレイを封止材料で封止する封止工程を 含むことを特徴とする請求の範囲第 2項に記載の半導体装置の製造方法。  12. The method for manufacturing a semiconductor device according to claim 2, further comprising a sealing step of sealing the thin film transistor array to which the separation portion is connected with a sealing material.
[13] 前記分離部が接続された薄膜トランジスタアレイを封止材料で封止する封止工程を 含むことを特徴とする請求の範囲第 3項に記載の半導体装置の製造方法。 13. The method for manufacturing a semiconductor device according to claim 3, further comprising a sealing step of sealing the thin film transistor array to which the separation portion is connected with a sealing material.
[14] 電子情報を記憶する記憶手段を有する電子装置にお!、て、前記記憶手段は、請 求の範囲第 2項に記載の製造方法で製造された半導体装置であることを特徴とする 電子装置。 [14] In an electronic device having storage means for storing electronic information, the storage means is a semiconductor device manufactured by the manufacturing method according to claim 2 of the claim. Electronic equipment.
[15] 電子情報を記憶する記憶手段を有する電子装置にお!、て、前記記憶手段は、請 求の範囲第 3項に記載の製造方法で製造された半導体装置であることを特徴とする 電子装置。 [15] In an electronic apparatus having storage means for storing electronic information! An electronic device, which is a semiconductor device manufactured by the manufacturing method according to claim 3.
PCT/JP2005/011605 2004-07-06 2005-06-24 Semiconductor device, method for fabricating the same and electronic apparatus WO2006003844A1 (en)

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