JP2017510017A - Method for customizing thin-film electronic circuits - Google Patents

Abstract

A method for manufacturing a thin film circuit comprising: (a) at least one logic gate circuit including an output; at least one logic gate circuit including a plurality of drive transistors and a plurality of load elements; and electrical connection to the output. And (b) sequentially supplying a voltage pattern to the plurality of drive transistors, wherein the voltage pattern is a series of voltages applied individually between the gate and source of each drive transistor. (C) measuring a series of output voltage values of at least one logic gate circuit corresponding to the voltage pattern, (d) comparing the output voltage value with a series of predetermined reference output voltage values, e) If the output voltage value does not match the reference output voltage value, Applied a number of loading elements being repeated until consistent with (f) (b) see (e) is the output voltage value from the output voltage value is one.

Description

  The technology of the present disclosure relates to a method for customizing thin film electronic circuits, such as circuits based on organic semiconductors or circuits based on metal oxide semiconductors, after circuit manufacture. The technology of the present disclosure relates to a method for converting a general purpose, multipurpose thin film electronic circuit to a specific purpose thin film electronic circuit after manufacture.

  The technology of the present disclosure relates to a method for customizing or modifying a thin film logic gate circuit including a plurality of thin film transistors such as an organic semiconductor based logic gate circuit or a metal oxide semiconductor based logic gate circuit after transistor manufacture. In particular, the technique of the present disclosure relates to a method for matching a pull-down circuit and a pull-up circuit of such a logic gate circuit after transistor manufacture.

US Patent Application Publication No. 2006/0190917

Hiroshi Fuketa et al. , “1 μm-Thickness 64-Channel Surface Electromyogram Measurement Sheet with 2 V Organic Transistors for Prosthetic Hand Control”, ISSCC, 2013

  Printing has been proposed as a technique for realizing a low-cost thin-film electronic circuit using, for example, roll-to-roll printing. The disadvantage of this approach is that the resolution is low and therefore the circuit is large and the production volume is very low. As a result, the planned low cost could not be realized.

  There is a need for thin film electronic circuits that can be provided at low cost and in volume production.

  Patent Document 1 describes a process of manufacturing a circuit board that is custom-printed on a substrate on which an electronic device is provided in advance. A user has been custom printed using a design tool to perform one or more specific electronic functions based on pre-installed electronic devices and / or custom designed and directly printed devices. Design the circuit board. The custom printed circuit board is then created by direct printing of one or more conductive paths between pre-installed devices. It is an advantage of this approach that a substrate pre-fitted with electronic devices can be manufactured in a mass production volume, which can lead to cost savings.

  In thin film circuits such as organic circuits and metal oxide semiconductor circuits, it is known that the transistor manufacturing process can lead to a large spread of technical parameters, such as a large spread in carrier mobility or transistor threshold voltage, for example. Non-Patent Document 1 proposes a method for reducing mismatching of an organic amplifier array in a transistor. A post-manufacture selection and connection method using two groups of N parallel transistors has been proposed. Initially, the IV characteristics of each transistor are measured and a 2N measurement is required. Subsequently, considering these characteristics, transistors are selected from each group of N transistors based on calculations that minimize mismatch. Selected transistors are connected by inkjet printed interconnects. It is a disadvantage of this approach that the characteristics of all transistors need to be measured.

  One aspect of the invention relates to a method for customizing a thin film electronic circuit, such as a circuit based on an organic semiconductor or a circuit based on a metal oxide semiconductor, after circuit manufacture. One aspect of the invention relates to a method of changing a general purpose, multipurpose thin film electronic circuit after manufacture to a special purpose thin film electronic circuit.

  One aspect of the invention relates to a method of modifying a thin film logic gate circuit, such as a logic gate circuit based on an organic semiconductor or a logic gate circuit based on a metal oxide semiconductor, after transistor fabrication. One aspect of the invention relates to a method for matching the pull-up and pull-down currents of such a logic gate circuit after transistor fabrication. Those skilled in the art understand what is meant by the pull-up and pull-down currents of the logic gate circuit.

A method of manufacturing a thin film circuit according to the present disclosure includes:
(A) obtaining a thin film circuit including at least one logic gate circuit having an output, the at least one logic gate circuit including a plurality of drive transistors and a plurality of load elements, and at least one load element; Is electrically connected to the output,
Obtaining a thin film circuit;
(B) sequentially supplying a series of predetermined voltage patterns (test patterns) to a plurality of drive transistors,
The voltage pattern includes a series of voltages applied individually between the gate and source of individual drive transistors,
Supplying sequentially,
(C) measuring a series of output voltage values of at least one logic gate circuit corresponding to the series of predetermined voltage patterns;
(D) comparing the series of output voltage values with a series of individual predetermined reference output voltage values;
(E) applying the number of load elements electrically connected to the output if the output voltage value does not match an individual predetermined reference output voltage value; and
(F) repeating steps (b) to (e) until the series of output voltage values match a series of predetermined reference output voltage values;
It is a manufacturing method containing.

  For example, a match between a measured output voltage value and an individual predetermined reference output voltage value may mean that both correspond to (or are interpreted as such) the same logic level. For example, both are interpreted as a logical value 1 or both are interpreted as a logical value 0. Thus, inconsistency means that both are interpreted as different logic levels.

  The predetermined reference output voltage value corresponds to the output voltage value expected when the logic gate circuit is operating correctly and a series of predetermined voltage patterns (test patterns) are provided. Therefore, when a series of output voltage values matches a series of predetermined reference output voltage values, the logic gate circuit operates properly and terminates.

  In an embodiment of the present disclosure, a predetermined portion (subset) of the plurality of drive transistors has a drain electrically connected to the output of at least one logic gate circuit. The remaining drive transistors are electrically disconnected from the output (not electrically connected). All drive transistors may have a drain electrically connected to the output, or a predetermined selection from the plurality of drive transistors may have a drain electrically connected to the output, or multiple The drive transistor may not have a drain electrically connected to the output.

  Predetermined (expected, expected) thin film circuit functionality is obtained by adapting the circuit after thin film transistor fabrication, regardless of variations and potentially large spread in technology parameters and / or transistor parameters It can be an advantage of the disclosed method. It is an advantage of the method of the present disclosure that applying the circuit after manufacturing the thin film transistor is based on characterizing the functionality of the circuit without having to measure the characteristics of each transistor individually. The functionality of the circuit is characterized by measuring a series of output voltage values for a series of predetermined voltage patterns applied.

  In the method of the present disclosure, applying the number of load elements electrically connected to the output desirably includes electrically connecting a single additional load element to the output or a single load element. Electrically disconnecting from the output. In such an embodiment, the number of load elements connected to the output is applied one by one until the series of output voltage values matches the series of predetermined reference voltage values. By applying one by one, the risk of connecting or disconnecting too many load elements can be avoided.

  In the method of the present disclosure, the plurality of load elements may be load transistors including at least one load transistor having a source electrically connected to its output.

  The thin film circuit may include a plurality of logic gate circuits.

  For example, the plurality of logic gate circuits may be a part of a write-once read many memory. The step of sequentially supplying a series of predetermined voltage patterns between the gates and sources of the plurality of drive transistors includes the step of sequentially turning on only one of the plurality of drive transistors and each of the subsequent plurality of drive transistors. May be included. Thus, measuring a series of output voltage values may include reading data stored in the memory.

  The write-once read many memory may be part of an instruction generator circuit, for example, in which case the write-once read many memory stores instructions to a general purpose microprocessor.

  The write-once read many memory may be part of a customized code generator of an RFID circuit, for example, in which case the write-once read many memory stores an identification code. The step of providing a series of predetermined voltage patterns between the gates and sources of the plurality of drive transistors can be initiated by powering the RFID circuit. Thereafter, measuring the series of output voltage values may include reading the identification code.

  The disclosed method may match the pull-up current with the pull-down current of at least one logic gate circuit after obtaining the thin film circuit and before providing the series of predetermined voltage patterns. Estimating the number of load elements required based on statistical data and estimating the number of load elements electrically connected to the output of at least one logic gate circuit; The method may further include applying to the number to be applied.

  The statistical data is, for example, a parameter selected from transistor threshold voltage, transistor threshold voltage spread, carrier mobility, carrier mobility spread, gate capacitance, gate capacitance spread, gate width, gate width spread, gate length and gate length spread. Measurements can be included. These data can be measured, for example, during or immediately after fabrication of the thin film transistor.

  In an embodiment of the present disclosure, applying the number of load elements electrically connected to the output of at least one logic gate circuit connects additional load elements to the output of at least one logic gate circuit. Steps may be included. Connecting the additional load element to the output may include printing an electrical connection between the load element and the output, such as, for example, inkjet printing an electrically conductive material.

  In an embodiment of the present disclosure, applying the number of load elements electrically connected to the output of at least one logic gate circuit includes, for example, laser processing (eg, laser cutting) between the load element and the output. And disconnecting the load element from the output of the at least one logic gate circuit by disconnecting the electrical connection.

  In embodiments of the present disclosure, the load element may be selected from, for example, an n-type depletion load thin film transistor, an n-type enhancement load thin film transistor, a p-type depletion load thin film transistor, a p-type enhancement load thin film transistor, and a resistor, but the present disclosure is not limited thereto. .

  The present disclosure provides a method for post-fabrication configuration of a thin film electronic circuit, the method comprising the steps of manufacturing a multipurpose thin film electronic circuit including a plurality of electronic devices and a plurality of electrical connections, followed by a multipurpose circuit. Pre-determined with expected / expected / required circuit performance by establishing at least one further electrical connection and / or by removing at least one electrical connection Converting to a special purpose thin film circuit.

  In embodiments of the present disclosure, a general purpose circuit may include redundant electronic elements, such as redundant electronic input devices and / or redundant electronic output devices.

  In embodiments of the present disclosure, converting a multipurpose thin film circuit to a predetermined specific purpose thin film circuit is preferably performed using relatively inexpensive equipment, materials and processes. For example, establishing at least one additional electrical connection can be performed by printing an ink containing metal (eg, ink jet printing). For example, removing at least one electrical connection can be performed by laser (laser cutting). However, the present disclosure is not limited thereto and other suitable methods may be used to establish and / or remove electrical connections.

  The method of the present disclosure can be advantageously used to optimize circuit performance and reduce production loss due to large parameter spread. It is an advantage of the disclosed method that it can lead to increased robustness with respect to large device parameter spread.

  This well-establishment technology for mass production of thin film transistors can be used to produce thin film circuits with large volume and high production, and that simultaneous customization of thin film electronic circuits is achieved. This is an advantage of the disclosed method. It is an advantage of this approach that low cost manufacturing can be achieved for very large production volumes, each of which is greater than the volume of individual functions or special purpose circuits.

  Embodiments of the present disclosure that product definitions (customization, realization of special purpose thin film circuits) can be made at a later stage in the manufacturing process using inexpensive methods such as local ink jet printing of inks containing metals, for example. Is the advantage.

  Several objects and advantages of various inventive aspects have been described above. Of course, it is to be understood that not all such objectives or advantages may be achieved in accordance with any particular embodiment of the present disclosure. Thus, for example, those skilled in the art will recognize one or more advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein. It will be appreciated that the present disclosure may be embodied or implemented to achieve or optimize. Furthermore, it is to be understood that this summary is merely an example and is not intended to limit the scope of the present disclosure. When the present disclosure is read in conjunction with the accompanying drawings, it should be understood that both the structure and method of operation, together with the features and advantages thereof, can be better understood with reference to the following detailed description. .

FIG. 1A shows a block diagram of a P ² ROM instruction generator chip and an enlarged view of a unipolar n-type printable WORM memory. FIG. 1 (b) adds five load transistors for a NOR gate, for example by an enlarged view of a row of 16 select transistors and inkjet printing (IJP) of conductive ink, for example, according to the disclosed method. Show that it is possible. FIG. 2 (a) shows the V _out vs. V _in simulation curve for a 16-bit NOR gate with a single depletion load load transistor. FIG. 2 (b) shows the V _out vs. V _in simulation curve for a 16-bit NOR gate with multiple load transistors. FIG. 3 (a) shows the output characteristics of a typical solution process oxide n-type transistor. FIG. 3B shows the output characteristics of a typical vapor deposition process pentacene p-type transistor. FIG. 3 (c) shows the conversion characteristics of the hybrid complementary technology at different supply voltages. FIG. 4 shows a detailed layout of a P ² ROM instruction generator with connections printed after circuit manufacture according to the disclosed method. FIG. 5 shows the measured signal of the P ² ROM instruction generator when configured (printed after manufacture according to the present disclosure) to execute the running averager algorithm. FIG. 6 shows signals measured on both the P ² ROM and the processor core chip while running the running averager algorithm. The pulse at the top of the figure corresponds to the command “store in output register”. FIG. 7 schematically shows a block diagram of a 64-bit code generator of an RFID transponder chip.

  In the different figures, the same reference signs refer to the same or analogous elements.

  In the following detailed description, numerous specific details are provided to provide a thorough understanding of the present disclosure and how it may be implemented in specific embodiments. However, it will be understood that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures and techniques have not been described in detail so as not to obscure the present disclosure. Although the present disclosure will be described with respect to particular embodiments and with reference to certain figures, the disclosure is not limited thereto. The figures included and described herein are schematic and do not limit the scope of the disclosure. It should also be noted that the size of some elements in the figures may be exaggerated or not drawn to scale for illustrative purposes.

  The present disclosure will be described with respect to particular embodiments and with reference to certain drawings but the disclosure is not limited thereto but only by the claims. The drawings depicted are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and relative dimensions do not necessarily correspond to actual reductions in the practice of the present disclosure.

  Further, terms such as top, bottom, top, bottom in the specification and claims are used for explanatory purposes and are not necessarily used to describe relative positions. The terms so used can be interchanged under appropriate conditions, and the embodiments of the present disclosure described herein are in other arrangements than those described or illustrated herein. It should be understood that it is operable.

  In the context of this disclosure, “after manufacture” or “after circuit manufacture” means after manufacture of a thin film semiconductor device such as a thin film transistor.

  In the context of this disclosure, “write once read many memory” means a memory in which information is written after manufacture and once written, the information is not further modified and the memory can be read many times. Information writing need not be performed in a single writing process. It can also be done in several successive writing steps.

  Although the present disclosure provides methods for post-fabrication of thin film electronic circuits, such as thin film electronic circuits based on organic semiconductors or thin film electronic circuits based on metal oxide semiconductors, the present disclosure is not limited thereto. Not. A method according to the present disclosure includes fabricating a multipurpose thin film electronic circuit that includes a plurality of electronic devices and, for example, a plurality of electrical connections between the electronic devices, and then establishes at least one additional electrical connection. And / or converting the multipurpose circuit to a predetermined special purpose thin film circuit by removing at least one electrical connection. In embodiments of the present disclosure, a general purpose circuit may include redundant electronic elements, such as redundant electronic input devices and / or redundant electronic output devices.

  The present disclosure provides a method for customizing thin film logic gate circuits, such as logic gate circuits based on organic semiconductors or logic gate circuits based on metal oxide semiconductors, after transistor fabrication. In particular, the present disclosure comprises a method for matching the pull-down current and pull-up current of such a logic gate circuit after circuit manufacture.

  The method according to the present disclosure is further described in the context of some specific examples, showing the possibility of managing the ratio of the number of load transistors to the number of drive transistors in a unipolar NOR gate. Although the method is illustrated for the example of a commercialized instruction generator for a general purpose chipset, the present disclosure is not so limited. The method may be used for other applications, such as a customized code generator for an RFID system, for example, but the disclosure is not limited thereto. The disclosed method may be used in other configurations and for other applications.

1A is a block diagram of a P ² ROM (Print Programmable Read Only Memory) instruction generator chip 100 and a unipolar n-type printable WORM (Write Once Read Many) memory. An enlarged view of 200 is shown. The memory 200 includes a fixed pull-up network 210 and a programmable pull-down network 220 including load transistors (Opc (0), Opc (1),...) For the respective data lines 300 and 301. In the example shown, the pull-up network is based on an n-type transistor with a zero V _GS load connected. However, in alternative approaches, other loads may be used, for example, resistor loads, diode-connected n-type transistors or p-type transistors. P-type mounting and complementary mounting are also possible.

  Programming the memory 200 (ie, writing data to the memory) provides a predetermined select transistor (Sel0, Sel1) with an electrical connection between the select transistor and the data lines 300, 301 and other This can be done by disconnecting the select transistor from the data line. Providing an electrical connection can be accomplished by ink jet printing an electrically conductive material between a predetermined select transistor and a data line. Printing the electrically conductive material can be done, for example, in the area labeled “IJP” in FIG.

  In another alternative approach (not shown in the figure), all select transistors may be connected to the data line after manufacture, and the memory removes the predetermined connection, eg, by laser patterning (ie, It may be programmed by disconnecting a predetermined select transistor.

  FIG. 1 (b) illustrates an example where the ratio of the number of load transistors (Opc) to the number of drive transistors or select transistors in the unipolar NOR gate 10 can be adapted using the method according to the present disclosure after circuit fabrication. FIG. 1B shows a general circuit layout of the NOR gate 10. Specifically, in the example shown, select transistors Sel0,. . . Sel 15 can be initially electrically disconnected from data line 300 (corresponding to the output of NOR gate 10), for example, and the predetermined number of these transistors is determined by the electrically conductive material after circuit fabrication. 40 can be electrically connected to the circuit (to data line 300), for example, by local printing, such as inkjet printing. If the NOR gate 10 is part of a memory (as in FIG. 1 (a)), the connection to a predetermined select transistor or drive transistor output is to program the memory, i.e. to the memory. Corresponds to writing data. The local print (indicated by “IJP” meaning “ink jet printing” in FIG. 1 (b)) is made in a range having a planar structure of electrodes on the electronic surface. Is desirable. If no conductive material is provided, the select transistor remains electrically disconnected.

  In the method according to the present disclosure, the same inkjet printing process can be applied to at least a part of the load transistor Opc. The ratio of the connected load transistor to the connected drive transistor (select transistor) determines the performance of the NOR gate. As shown in FIG. 1B, the pull-up network is not fixed in the embodiment of the present disclosure, and a plurality of load transistors (Opc) are provided in each data line 300 (up to six load transistors in the example). It has been. After transistor fabrication, only one load transistor or a limited number of load transistors are connected to the data line 300 (as shown in FIG. 1B). In the method of the present disclosure, a further load transistor can be connected to the data line 300, for example by ink jet printing.

  In another embodiment, the select transistor and / or load transistor may be initially electrically connected to the circuit, and a predetermined number of these transistors is disconnected by a method of cutting metal wiring, such as laser cutting. Can be done. In other embodiments, a portion of the transistor can be initially electrically connected to the circuit, and another portion of the transistor can be initially disconnected.

  The ratio of the connected load transistor to the connected drive transistor can be changed by connecting and / or disconnecting a dedicated transistor after circuit manufacture using the method according to the present disclosure.

  In the disclosed method, the active load (pull-up network) is not fixed and can be adapted or modified after transistor fabrication. Such post-manufacture modifications can greatly reduce the impact of technology variations (and corresponding parameter variations in the select transistor) on circuit functionality. Variations in technology affect, for example, transistor leakage current, and therefore these variations affect the pull-down current of the memory data line 300 when the pull-down is not active (ie, when the drive transistor is off). . Such post-manufacture modifications may be aimed, for example, to match the pull-up current with the pull-down current so that the output can be pulled up fast enough when the pull-down is not active.

  The variation of the parameters of the select transistors (Sel0, Sel1,...) And the number of select transistors connected to the output line (determined for example by a specific code in the memory, for example) are both memory data bits. Affects line pull-down current. As a result of these effects, the active pull-down current is not known in advance (ie, at the circuit design stage), so the pull-up current can be easily matched to the pull-down current at the circuit design stage. Absent. Using the method according to the present disclosure, the pull-up current can be matched to the pull-down current by changing the number of load transistors after circuit design and transistor fabrication.

FIG. 2 shows a simulation curve showing the importance of controlling the load / drive ratio of the NOR gate. FIG. 2 (a) shows V _out vs. V _in simulation curves for a 16-bit NOR gate with a single depletion load load transistor for 1 to 16 inputs (1 to 16 select transistors). Conversion characteristics). FIG. 2 (b) shows the V _out vs. V _in simulation curve (conversion characteristics) for a 16-bit NOR gate with 16 inputs and multiple (1 to 6) load transistors. For a 16-input NOR gate, only one depletion load load transistor causes the NOR gate to lose functionality from the 12-input on state (FIG. 2 (a)). FIG. 2 (b) reveals what happens when additional (1 to 6) load thin film transistors are provided. The voltage conversion curve compensates for 16 inputs, which makes the circuit more stable.

  In the method of the present disclosure, the pull-up current of the logic gate circuit is matched to the pull-down current after fabrication of the transistor based on measurement of circuit functionality and / or based on technology and design characteristics. Matching the pull-up current to the pull-down current is accomplished by connecting (eg, by inkjet printing) or disconnecting (eg, by laser cutting) the required number of load transistors to the data line (logic gate output). Made.

  In the method according to the present disclosure, a thin film circuit is manufactured, the thin film circuit including at least one logic gate circuit having an output. The at least one logic gate circuit includes a plurality of drive transistors, the drain of which may or may not have a drain electrically connected to the output, and further includes a plurality of load elements. At least one load element is electrically connected to the output of the logic gate. The remaining (ie, unconnected) load elements are redundant load elements and, if necessary to obtain the predetermined performance (predetermined functionality) of the logic gate circuit, Can be connected to output.

  In the disclosed method, for example, to check the functionality of a thin film circuit, a series of predetermined voltage patterns (input voltage patterns) are supplied to a plurality of drive transistors, i.e., the voltage pattern is a plurality of drive transistors. Applied between gate and source. The series of predetermined voltage patterns may include a single input voltage combination for a plurality of drive transistors, or may include a series of input voltage combinations for a plurality of drive transistors.

  Next, a series of output voltage values corresponding to the series of predetermined voltage patterns are measured for at least one logic gate circuit, and the measured series of output voltage values is a series of predetermined voltage values. Compared to the reference output voltage value (ie, the expected output voltage value based on the required functionality of the circuit).

  If the measured series of output voltage values correspond to (ie, match) the series of predetermined reference output voltage values, no further action is taken. If the measured series of output voltage values is different (ie, not matched) from the series of predetermined reference output voltage values, the number of load elements electrically connected to the output is adapted. I.e. increased or decreased.

  A single load element is further connected to the output or disconnected from the output. Depending on the applied circuit configuration, providing a series of predetermined voltage patterns, measuring a series of output voltage values, and converting the series of measured output voltage values to an expected output voltage value. The step of comparing is repeated. Thereafter, again, depending on the result of this comparison, the single load element can be further connected or disconnected. These steps are performed until a series of measured output voltage values correspond to (i.e. match) the predetermined output voltage values, i.e. until the required functionality of the circuit is obtained. Repeated.

  For example, if the logic gate circuit is part of a memory containing data bits, the data bits are first printed in the memory after the transistor manufacturing process by ink jet printing, thereby outputting a predetermined drive transistor. Can be connected to. Next, according to the method of the present disclosure, a series of predetermined voltage patterns are applied and a series of output voltage values are measured. This corresponds to reading data stored in the memory. For example, if a high value (logic 1) is expected, there may be a bit that can be read as a logic 0 (measured as low), for example. This may be due to an active load that does not provide sufficient pull-up current at the output to obtain a high value. In this case, an additional load transistor is connected to the data line (eg, by inkjet printing) until a high output is obtained.

  As an alternative to inkjet printing based implementations, all data bits can be entered into memory by laser patterning, eg, laser cutting, after transistor fabrication. Thereafter, according to the method of the present disclosure, all memory bits are read and verified. If a low value (logic 0) is expected, there may be bits that can be read as logic 1 (measured as high). This may be due to an active load that provides too much pull-up current. The connection between the load transistor and the data line can then be removed by laser patterning until the required low output is obtained.

  In an embodiment of the present disclosure, the pull-up current is measured after circuit manufacture and before measuring its functionality by applying a series of predetermined voltage patterns and measuring a series of output voltage values. The required number of load transistors required to match with the pull-down current can be estimated based on statistical data, and this estimated number of load transistors can be estimated before testing its functionality. It can be connected to the output of a logic gate circuit. Statistical data that can be considered include, for example, transistor threshold voltage, transistor threshold voltage spread, carrier mobility, carrier mobility spread, gate capacitance, gate capacitance spread, gate width, gate width spread, gate length and gate length spread (from Measurement of selected parameters), but the present disclosure is not limited thereto.

  In this approach, technical parameters and their local variations are measured after or during the manufacturing process of the thin film circuit. Based on these measured values and information on the required data in the memory (i.e. the number of connected drive transistors), the inactive pull-down current, i.e. the pull-down current when the drive transistor is OFF, is calculated. The From this inactive pull-down current, a matching pull-up current can be derived. A matched pull-up transistor configuration is then realized using ink jet printing or laser patterning. The pull-up transistor configuration of the logic gate circuit can then be further adapted based on its functionality evaluation as described above.

  The foregoing description relates to unipolar n-type TFT technology. However, the present disclosure is not limited thereto, and the method of the present disclosure can also be used in the case of, for example, unipolar p-type TFT technology. In that case, the pull-up connection and the pull-down connection are interchanged with each other in contrast to the case of unipolar n-type TFT technology.

  In an embodiment of the present disclosure, a specific layout can be used to establish an electrical connection by local (inkjet) printing. A planar structure of the comb electrode 20 (schematically shown in FIG. 1 (b)) is preferably used. This allows for efficient use of the area. The comb electrode 20 is preferably provided on a non-conductive layer or surface. Optionally, well structure 30 provides a layer of dielectric material, such as a layer of negative photoresist, and removes the layer of dielectric material in a locally predetermined region, thereby forming the well structure Can be formed by forming 30 in a predetermined area. This is particularly advantageous in embodiments where the conductive material, eg, conductive ink, repels the surface to be printed. The presence of the well structure 30 in the predetermined region facilitates confining the electrically conductive ink within that region. FIG. 1 (b) also shows an enlarged view of the well structure 30 and the comb-shaped electrode 20 before providing the electrically conductive ink and after providing the electrically conductive ink. In the example shown, the pattern of the well structure 30 has a square shape, and the electrically conductive ink 40 has a circular shape. However, the present disclosure is not so limited and other suitable shapes may be used. In the example shown in FIG. 1B, the conductive ink pattern only fills a part of the well structure. However, it can also fill smaller or larger portions of the well structure, for example, it can completely fill the well structure 30.

The disclosed method, process variations (e.g., difference in V _T) and as it can be used to compensate for post-production for the compensation or the gate voltage variation after manufacturing for, these fluctuations will increase the leak It can be.

The method of the present disclosure is not limited to unipolar depletion load NORs as described above. For example, it can also be used for enhancement loads NORs (or diode loads). After all, in order to more robust to fluctuations in V _T, it may include both load transistors. The method of the present disclosure can also be used to add or remove a pseudo-pMOS or pseudo-nMOS load from a resistive load or complementary technology perspective.

The 8-bit thin film microprocessor is manufactured using hybrid oxide organic complementary thin film technology and includes memory configured after manufacture by inkjet printing according to the method of the present disclosure. The n-type transistor is based on a solution process n-type metal oxide semiconductor, and the p-type transistor uses an organic semiconductor. Compared to previous ones that utilize unipolar logic gates, the use of higher mobility and complementary logic in n-type semiconductors allows speed improvements of more than 50 times. It also adds robustness to the design, enabling a more complex and complete standard cell library. The microprocessor consists of two parts: a processor core chip and an instruction generator. The instructions are stored in a write once read many (WORM) memory that is formatted by a post-manufacturing inkjet printing process according to the disclosed method. This memory is further referred to as a print programmable read only memory (P ² ROM). The entire process was performed at a temperature compatible with the plastic wheel substrate, that is, 250 ° C. or lower.

The typical output characteristics of a hybrid organic / oxide complementary transistor are shown in FIG. FIG. 3 (a) shows the output characteristics of a typical solution process oxide n-type transistor, and FIG. 3 (b) shows the output characteristics of a typical deposited pentacene p-type transistor. The use of this technology for composite design has already been proven with bidirectional RFID tags and with flexible substrates. The pn transistor ratio to the logic gate is selected to be 3: 1 so that the minimum device size for oxide n-TFT is equal to 50/5 μm / μm and the minimum device size for organic p-TFT is 150 Equal to / 5 μm / μm. Normal inverter characteristics are shown in FIG. The realization of the circuit is based on a bottom gate top S / D contact oxide n-TFT and a bottom S / D contact top gate organic p-TFT and is fabricated on a Si / SiO ₂ substrate.

The thin film microprocessor is divided into two independent chips, a processor core chip and a general purpose instruction generator or P ² ROM. The P ² ROM chip is a one-time programmable ROM memory configured by using ink-jet printing of conductive ink according to the present disclosure. In this example, the conductive ink includes silver. Using this approach, the general purpose instruction generator is converted to a special purpose instruction generator. A block diagram of the general-purpose instruction generator is depicted in FIG. It consists of a 4-bit program counter (PC), a 4-16 decoder that instantly selects each instruction line, printable WORM memory, and the next opcode (operation code) that drives the microprocessor every clock cycle. It consists of a 9-bit register that is updated. Each printed connection results in a logical value 1, while a non-printed connection results in a logical value 0. The printable WORM memory is designed as a unipolar n-TFT NOR with a ratio of 1:10 between drive and load transistors. The drive transistor has a size of 140/5 μm / μm, while the load transistor has a size of 1400/5 μm / μm. In order to ensure good NOR characteristics for cases where multiple select transistors are connected and required, up to five more load transistors can be obtained by inkjet printing, as illustrated in FIG. 1 (b). Can also be added.

FIG. 4 shows the layout of the P ² ROM instruction generator chip divided into a hybrid complementary part and a unipolar n-TFT part. To evaluate the P ² ROM chip, an instruction to run the running averager algorithm (OUT _new = 0.5 round (in + out _old )) was printed. The first 12 lines were printed for the running averager algorithm. The other four lines of the instruction generator are not printed, thus resulting in a NOOP (no operation) command. The instruction runs the algorithm twice before storing the value in the output register. Since the LSR instruction is executed only after storage in the output register, the output code is a 7-bit code that is one bit more accurate than the 6-bit input. FIG. 5 depicts the correct operation of the P ² ROM chip at a supply voltage of 10V and a maximum clock frequency of 650 Hz. It generates register select bits and operation codes that drive the processor core chip to execute the running averager algorithm. The order of instructions is also shown in detail in FIG.

Finally, the processor core and P ² ROM chip were connected. FIG. 6 shows the measured results when both chips are connected at a clock frequency of 500 Hz. As the input switches from 0 to 7 (hexadecimal), the output averages between 7, C and E and remains constant at E (hexadecimal).

  FIG. 7 shows an example block diagram of a 64-bit code generator 50 of an RFID transponder chip. The 64-bit code generator 50 includes a clock generator 51, a 3-bit binary counter 52, an 8: 1 multiplexer 53, an 8-bit line select block 54, a 64-bit WORM memory 55 for storing a customized identification code, and an output register 56. . The identification code can be written into a memory, for example, after circuit manufacture, for example by ink jet printing or laser cutting as described above. When the transponder chip is powered, the clock signal 60 is generated by the clock generator 51. The clock signal 60 is used to provide a clock to the output register 56, the 3-bit binary counter 52 and the 8-bit line select block 54. The 8-bit line select block 54 has an internal 3-bit binary counter and a 3-8 decoder. This block selects the 8-bit row of memory 55 containing the code (this is done, for example, by switching on the corresponding drive transistor). The 3-bit binary counter 52 drives an 8: 1 multiplexer 53 that selects an 8-bit string in the memory 55. The data bits at the intersection of the selected row and the selected column are transferred to the output register 56 via the 8: 1 multiplexer 53, which outputs this bit on the rising edge of the clock signal (see FIG. (Not shown in 7). The 3 bits of the 3 bit binary counter 52 are also used in the 8 bit line select block 54 to select a new row after all 8 bits of the row have been transferred to the output register. In this way, all bits of the identification are read after the circuit is powered.

  The method of the present disclosure can be used to modify the thin film logic gate circuit of the memory 55. Each column of memory 55 may include, for example, a NOR gate circuit 10 as shown in FIG. 1B, where each select transistor (drive transistor) corresponds to a different row of the memory matrix. Selecting a row sequentially after manufacturing the circuit and writing the identification code into the memory (ie, sequentially switching each single select transistor of the NOR gate circuit 10 and subsequent select transistors on), and By measuring the output voltage value for each NOR gate circuit 10, i.e. for each column of the memory matrix, the memory is read as described above. Each output voltage value is interpreted as a logic level, ie, a logic value 1 or a logic value 0. If the bit (logic level) read from the memory does not correspond to the expected or expected bit (expected logic level) of the identification code, a further load element will send to the corresponding NOR gate circuit 10. The load element can be connected or disconnected from the corresponding NOR gate circuit 10.

  The use of a particular term in describing a feature or form of the present disclosure is intended to be limited to include any particular characteristic of the feature or form of the present disclosure to which that term relates. It should be noted that it should not be interpreted to mean that it has been redefined in the book.

  While the foregoing detailed description has shown, described, and pointed out novel features of the present invention as applied to various embodiments, various omissions, substitutions and changes in the form and details of the device or process may be found here. It will be understood that this can be done by those skilled in the art without departing from the invention.

Claims (15)

In a method for manufacturing a thin film circuit, the method comprises:
(A) obtaining a thin film circuit including at least one logic gate circuit having an output, the at least one logic gate circuit including a plurality of drive transistors and a plurality of load elements, and at least one load element; Is electrically connected to the output,
Obtaining a thin film circuit;
(B) sequentially supplying a series of predetermined voltage patterns to the plurality of drive transistors,
The voltage pattern includes a series of voltages applied individually between the gate and source of individual drive transistors,
Supplying sequentially,
(C) measuring a series of output voltage values of at least one logic gate circuit corresponding to the series of predetermined voltage patterns;
(D) comparing the series of output voltage values with a series of individual predetermined reference output voltage values;
(E) applying the number of load elements electrically connected to the output if the output voltage value does not match an individual predetermined reference output voltage value; and (f) ( repeating steps b) to (e) until the series of output voltage values matches a series of predetermined reference output voltage values;
Including methods.   The method of claim 1, wherein a predetermined portion of the plurality of drive transistors has a drain electrically connected to an output of at least one logic gate circuit.   3. A method according to any one of claims 1 and 2, wherein the plurality of load elements are load transistors, wherein at least one load transistor has a source electrically connected to the output.   4. The method according to any one of claims 1 to 3, wherein the thin film circuit comprises a plurality of logic gate circuits. The multiple logic gate circuits are part of the write once read many memory,
Sequentially supplying a series of predetermined voltage patterns to the plurality of drive transistors includes sequentially turning on only one of the plurality of drive transistors and each of the following plurality of drive transistors, and a series of outputs. Measuring the voltage value includes reading data stored in the memory,
The method of claim 4. The write once read many memory is part of the instruction generator circuit,
Write Once Read Many Memory stores instructions for general purpose microprocessors,
The method of claim 5. The write once read many memory is part of the customized code generator of the RFID circuit, the write once read many memory stores the identification code,
Supplying a series of predetermined voltage patterns to the plurality of drive transistors is initiated by powering the RFID circuit, and measuring the series of output voltage values includes reading an identification code. ,
The method of claim 5. After acquiring the thin film circuit and before supplying a series of predetermined voltage patterns,
Estimating, based on statistical data, the number of load elements required to match the pull-up current with the pull-down current of at least one logic gate circuit;
Applying the number of load elements electrically connected to the output of the at least one logic gate circuit to the estimated number of load elements;
The method according to claim 1. The statistical data is selected from transistor threshold voltage, transistor threshold voltage spread, carrier mobility, carrier mobility spread, gate capacitance, gate capacitance spread, gate width, gate width spread, gate length, and gate length spread. 9. The method of claim 8, comprising measuring a parameter. Applying the number of load elements electrically connected to the output of at least one logic gate circuit comprises connecting one additional load element to the output of at least one logic gate circuit;
10. A method according to any one of claims 1-9. The method of claim 10, wherein connecting one additional load element to the output of at least one logic gate circuit comprises printing an electrical connection between the load element and the output.   The method of claim 11, wherein printing comprises inkjet printing an electrically conductive material.   2. The step of applying the number of load elements electrically connected to the output of at least one logic gate circuit comprises disconnecting one load element from the output of at least one logic gate circuit. The method according to any one of 9 to 9. 14. The method of claim 13, wherein disconnecting one load element from the output comprises disconnecting an electrical connection between the load element and the output by laser cutting. The load element is selected from an n-type depletion load thin film transistor, an n-type enhancement load thin film transistor, a p-type depletion load thin film transistor, a p-type enhancement load thin film transistor, and a resistor.
15. A method according to any one of claims 1 to 14.