WO2005076331A1 - Method of fabricating metal-oxide semiconductor integrated circuit devices. - Google Patents

Method of fabricating metal-oxide semiconductor integrated circuit devices. Download PDF

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Publication number
WO2005076331A1
WO2005076331A1 PCT/IB2005/000248 IB2005000248W WO2005076331A1 WO 2005076331 A1 WO2005076331 A1 WO 2005076331A1 IB 2005000248 W IB2005000248 W IB 2005000248W WO 2005076331 A1 WO2005076331 A1 WO 2005076331A1
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Prior art keywords
dielectric layer
gate electrode
substrate
oxide semiconductor
integrated circuit
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PCT/IB2005/000248
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French (fr)
Inventor
Peter Stolk
Youri Ponomarev
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Koninklijke Philips Electronics N.V.
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Publication of WO2005076331A1 publication Critical patent/WO2005076331A1/en

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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L21/28176—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
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    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
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    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
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    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Definitions

  • This invention relates to a method of and apparatus for fabricating metal-oxide semiconductor (MOS) integrated circuit devices, and in particular complementary metal- oxide semiconductor (CMOS) integrated circuit devices.
  • MOS metal-oxide semiconductor
  • CMOS complementary metal- oxide semiconductor
  • CMOS complementary metal-oxide-semiconductor
  • thin dielectric layers are used to separate a poly- silicon gate electrode from the substrate.
  • These dielectric layers are made of oxynitride consisting of silicon dioxide in which nitrogen is implanted.
  • a passivation annealing step is usually carried out in the final steps of the CMOS manufacturing process.
  • a forming gas step is implemented at about 400°C for 30 minutes so as to drive in hydrogen to an interface between the dielectric layer and the substrate.
  • CMOS and beyond it is anticipated that conventional gate stacks, including an oxynitride dielectric layer and a poly-silicon gate electrode, will be replaced by new materials.
  • the oxynitride layer will be replaced by high permittivity dielectric layers, which are dielectric material having typically a relative permittivity (or dielectric constant) higher than 15.
  • Said high permittivity dielectric layers will be hereinafter referred to as high-k dielectric layers. They are oxides in which elements such as Zirconium Zr, Hafnium Hf, Aluminium Al, and/or Lanthane La are embedded to increase the dielectric constant.
  • the conventional poly-silicon gate electrodes will be replaced by metallic gate electrodes (e.g.
  • future technologies may comprise any combination of an oxynitride or high-k dielectric layer with a poly-silicon or metallic gate electrode on top.
  • metallic gate electrodes and high-k dielectric layers introduces a problem regarding the passivation of dielectric defects.
  • the implementation of high-k dielectric layers and/or metallic gate electrodes may limit the efficiency of forming gas anneal in passivating dielectric defects.
  • the fabrication method in accordance with the invention is characterized in that it comprises the steps of: forming a dielectric layer on a substrate, forming a gate electrode on said dielectric layer, implanting passivating impurities in the substrate, - performing a thermal treatment, the passivating impurities being adapted to passivate dielectric defects within the dielectric layer during said thermal treatment.
  • the implantation of passivating impurities increases the efficiency and the controllability of the passivation process.
  • the gate electrode is a metallic gate electrode and the step of implanting passivating impurities in the substrate is performed through the metallic gate electrode and the dielectric layer.
  • metals are known to efficiently absorb hydrogen, thereby blocking the diffusion of hydrogen towards the dielectric layer.
  • Implanting passivating impurities compensates for this, and allows dielectric defects to be passivated.
  • the passivating impurities are chosen among hydrogen, deuterium, fluorine, nitrogen or chlorine.
  • the dielectric layer is of the high permittivity type including, for example, Hafnium silicate HfSi x O y .
  • FIG. 1 is a schematic illustration of an embodiment of the process flow of a fabrication method according to the present invention
  • Figure 2 is a schematic illustration of another embodiment of the process flow of a fabrication method according to the present invention
  • Figure 3 is a schematic illustration of still another embodiment of the process flow of a fabrication method according to the present invention.
  • the present invention relates to a method of and apparatus for fabricating metal-oxide semiconductor integrated circuit devices, which is an alternative to forming gas anneals, and which is adapted to passivate dielectric defects.
  • the method in accordance with the invention comprises a step of implanting a controlled amount of hydrogen ions or atoms into the silicon substrate at any stage in the process flow to provide a source of hydrogen for the passivation of dielectric defects.
  • passivating impurities other than hydrogen ions may be used as well, such as, for example, deuterium, fluorine, nitrogen or chlorine ions or atoms.
  • the advantage of implanting hydrogen ions or atoms compared to forming gas anneals is that the hydrogen can be introduced in the substrate close to the dielectric interface, without having to diffuse through the interconnects and inter-metal dielectric layers on top of a silicon wafer.
  • Said implantation step may be particularly beneficial in the case of a metallic gate electrode integration. It may also serve as an alternative passivation procedure in conventional gate stacks including an oxynitride dielectric layer and a poly-silicon gate electrode.
  • Figure 1 is a schematic illustration of the process flow of a detailed embodiment of a method of fabricating a metal-oxide semiconductor transistor in accordance with the invention.
  • a conventional CMOS process is performed, resulting in the structure of Figure 1 A comprising a NMOS region 101 and a PMOS region 102 within a substrate 104, said region being separated by field isolation 103.
  • a thin dielectric layer 111 is deposited or grew on the substrate.
  • Said dielectric layer is, for example, a high-k dielectric layer including Hafnium, such as Hafnium silicate HfSi x O y .
  • Said dielectric layer has typically a 2 to 3 nanometer thickness.
  • a gate electrode 112 is formed on the thin dielectric layer.
  • Said gate electrode is, for example, a metallic gate electrode and includes, for example, Molybdenum Mo for the PMOS substrate, or Tantale-Silicon nitride TaSiN for the NMOS substrate.
  • Said second and third steps result in a gate stack as illustrated in Figure 2B.
  • an ion or atom implantation step 121 is performed through the existing gate stack, as shown in Figure lC.
  • Said implantation step comprises, for example, implanting hydrogen ions at an energy of around 30 keN with a dose of about 10 13 atomes/cm 2 .
  • Fluorine can be implanted at an energy of 70 keN with a dose of about 10 13 atomes/cm 2 .
  • the transistor fabrication is finalized, as shown in Figure ID.
  • This fifth step includes, for example, the following sub-steps of: - gate etching; source 131 or 133 and drain 132 or 134 extension implantation; spacer 135 formation; deep source and drain implantation; thermal annealing for impurity activation and defect removal; and - suicide 136 formation; said sub-steps being performed according to a principle known to a person skilled in the art.
  • the thermal annealing step is performed in order to diffuse hydrogen into the dielectric layer so as to facilitate passivation and to remove defects in the substrate generated by the hydrogen implantation step.
  • the annealing step duration is, for example, around 2 seconds and is applied, for example, at a temperature of about 1000°C.
  • an inter-metal dielectric layer is deposited, contacts are made, and metallization is finalized according to a principle known to a person skilled in the art.
  • FIG. 2 is a schematic illustration of the process flow of another exemplary embodiment of a fabrication process according to the present invention.
  • the structure of Figure 2A comprises a NMOS region 101 and a PMOS region 102 within a substrate 104.
  • An ion or atom implantation stepl21, illustrated in Figure 2B, is then performed through the existing gate stack, as before.
  • a thin dielectric layer 111 is deposited or grown on the substrate, followed by a gate electrode 112 formation, as illustrated in Figure 2C.
  • FIG. 3 is a schematic illustration of the process flow of still another exemplary embodiment of a fabrication process according to the present invention.
  • the structure of Figure 3 A comprises a NMOS region 101 and a PMOS region 102.
  • a thin dielectric layer 111 is formed on the substrate, followed by a gate electrode 112 formation, as illustrated in Figure 3B.
  • the transistor fabrication is finalized, as shown in Figure 3C, including the sub-steps of gate etching, source 131 or 133 and drain 132 or 134 extension implantation, spacer 135 formation and suicide 136 formation.
  • An ion or atom implantation step 121 illustrated in Figure 3D, is then performed through the existing gate stack, as before.
  • An annealing step is finally performed after the implantation step in order to diffuse hydrogen into the dielectric layer so as to facilitate passivation and to remove defects in the substrate generated by the ion implantation.
  • the thermal steps associated with suicide formation can be sufficient for passivation and defect annealing.
  • the fabrication process in accordance with this embodiment is particularly efficient. As a matter of facts, the later the passivating impurities are introduced in the process, the better it is because this limits the changes of de-passivation during further processing.

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Abstract

The present invention relates to a method of fabricating metal-oxide semiconductor integrated circuit devices. Said fabrication method comprises the steps of: - forming a dielectric layer (111) on a substrate, - forming a gate electrode (112) on said dielectric layer, - implanting passivating impurities (121) in the substrate, and - performing a thermal treatment, the passivating impurities being adapted to passivate dielectric defects within the dielectric layer during said thermal treatment. The gate electrode is, for example, a metallic gate electrode. The step of implanting passivating impurities in the substrate is performed, for example, through the metallic gate electrode and the dielectric layer. The passivating impurities are chosen, for example, among hydrogen, deuterium, fluorine, nitrogen or chlorine.

Description

Method of fabricating metal-oxide semiconductor integrated circuit devices
FIELD OF THE INVENTION This invention relates to a method of and apparatus for fabricating metal-oxide semiconductor (MOS) integrated circuit devices, and in particular complementary metal- oxide semiconductor (CMOS) integrated circuit devices.
BACKGROUND OF THE INVENTION In a conventional CMOS technology, thin dielectric layers are used to separate a poly- silicon gate electrode from the substrate. These dielectric layers are made of oxynitride consisting of silicon dioxide in which nitrogen is implanted. To passivate any electrically active defect or interface state associated with the thin dielectric layers, a passivation annealing step is usually carried out in the final steps of the CMOS manufacturing process. Conventionally, a forming gas step is implemented at about 400°C for 30 minutes so as to drive in hydrogen to an interface between the dielectric layer and the substrate. For future technologies (i.e. 65 nm CMOS and beyond), it is anticipated that conventional gate stacks, including an oxynitride dielectric layer and a poly-silicon gate electrode, will be replaced by new materials. The oxynitride layer will be replaced by high permittivity dielectric layers, which are dielectric material having typically a relative permittivity (or dielectric constant) higher than 15. Said high permittivity dielectric layers will be hereinafter referred to as high-k dielectric layers. They are oxides in which elements such as Zirconium Zr, Hafnium Hf, Aluminium Al, and/or Lanthane La are embedded to increase the dielectric constant. In addition, the conventional poly-silicon gate electrodes will be replaced by metallic gate electrodes (e.g. Titanium nitride TiN, Tantale-Silicon nitride TaSiN, Molybdene Mo, Ruthenium Ru) or suicided poly-silicon (Cobalt suicide CoSi or Nickel silicide NiSi). Depending on the CMOS application, future technologies may comprise any combination of an oxynitride or high-k dielectric layer with a poly-silicon or metallic gate electrode on top. However, the implementation of metallic gate electrodes and high-k dielectric layers introduces a problem regarding the passivation of dielectric defects. As a consequence, the implementation of high-k dielectric layers and/or metallic gate electrodes may limit the efficiency of forming gas anneal in passivating dielectric defects. SUMMARY OF THE INVENTION It is an object of the invention to propose a method of and apparatus for fabricating metal-oxide semiconductor integrated circuit devices, which is more efficient than the one of the prior art. To this end, the fabrication method in accordance with the invention is characterized in that it comprises the steps of: forming a dielectric layer on a substrate, forming a gate electrode on said dielectric layer, implanting passivating impurities in the substrate, - performing a thermal treatment, the passivating impurities being adapted to passivate dielectric defects within the dielectric layer during said thermal treatment. The implantation of passivating impurities increases the efficiency and the controllability of the passivation process. According to an embodiment of the invention, the gate electrode is a metallic gate electrode and the step of implanting passivating impurities in the substrate is performed through the metallic gate electrode and the dielectric layer. As a matter of facts, metals are known to efficiently absorb hydrogen, thereby blocking the diffusion of hydrogen towards the dielectric layer. Implanting passivating impurities compensates for this, and allows dielectric defects to be passivated. According to another embodiment of the invention, the passivating impurities are chosen among hydrogen, deuterium, fluorine, nitrogen or chlorine. Still according to another embodiment, the dielectric layer is of the high permittivity type including, for example, Hafnium silicate HfSixOy. These and other aspects of the invention will be apparent from and will be elucidated with reference to the embodiments described hereinafter.
BRIEF DESCRIPTION OF THE DRAWINGS The present invention will now be described in more detail, by way of example, with reference to the accompanying drawings, wherein: - Figure 1 is a schematic illustration of an embodiment of the process flow of a fabrication method according to the present invention; Figure 2 is a schematic illustration of another embodiment of the process flow of a fabrication method according to the present invention; and Figure 3 is a schematic illustration of still another embodiment of the process flow of a fabrication method according to the present invention.
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of and apparatus for fabricating metal-oxide semiconductor integrated circuit devices, which is an alternative to forming gas anneals, and which is adapted to passivate dielectric defects. The method in accordance with the invention comprises a step of implanting a controlled amount of hydrogen ions or atoms into the silicon substrate at any stage in the process flow to provide a source of hydrogen for the passivation of dielectric defects. It will be apparent to a person skilled in the art that passivating impurities other than hydrogen ions may be used as well, such as, for example, deuterium, fluorine, nitrogen or chlorine ions or atoms. The advantage of implanting hydrogen ions or atoms compared to forming gas anneals is that the hydrogen can be introduced in the substrate close to the dielectric interface, without having to diffuse through the interconnects and inter-metal dielectric layers on top of a silicon wafer. Said implantation step may be particularly beneficial in the case of a metallic gate electrode integration. It may also serve as an alternative passivation procedure in conventional gate stacks including an oxynitride dielectric layer and a poly-silicon gate electrode.
Figure 1 is a schematic illustration of the process flow of a detailed embodiment of a method of fabricating a metal-oxide semiconductor transistor in accordance with the invention. In a first step, a conventional CMOS process is performed, resulting in the structure of Figure 1 A comprising a NMOS region 101 and a PMOS region 102 within a substrate 104, said region being separated by field isolation 103. In a second step, a thin dielectric layer 111 is deposited or grew on the substrate. Said dielectric layer is, for example, a high-k dielectric layer including Hafnium, such as Hafnium silicate HfSixOy. Said dielectric layer has typically a 2 to 3 nanometer thickness. In a third step, a gate electrode 112 is formed on the thin dielectric layer. Said gate electrode is, for example, a metallic gate electrode and includes, for example, Molybdenum Mo for the PMOS substrate, or Tantale-Silicon nitride TaSiN for the NMOS substrate. Said second and third steps result in a gate stack as illustrated in Figure 2B. In a fourth step, an ion or atom implantation step 121 is performed through the existing gate stack, as shown in Figure lC. Said implantation step comprises, for example, implanting hydrogen ions at an energy of around 30 keN with a dose of about 1013 atomes/cm2. As another example, Fluorine can be implanted at an energy of 70 keN with a dose of about 1013 atomes/cm2. In a fifth step, the transistor fabrication is finalized, as shown in Figure ID. This fifth step includes, for example, the following sub-steps of: - gate etching; source 131 or 133 and drain 132 or 134 extension implantation; spacer 135 formation; deep source and drain implantation; thermal annealing for impurity activation and defect removal; and - suicide 136 formation; said sub-steps being performed according to a principle known to a person skilled in the art. The thermal annealing step is performed in order to diffuse hydrogen into the dielectric layer so as to facilitate passivation and to remove defects in the substrate generated by the hydrogen implantation step. In the above embodiment, the annealing step duration is, for example, around 2 seconds and is applied, for example, at a temperature of about 1000°C. Finally, an inter-metal dielectric layer is deposited, contacts are made, and metallization is finalized according to a principle known to a person skilled in the art.
It will be apparent to a person skilled in the art that other implementations are possible. As a matter of fact, the implantation step can be performed earlier or later in the process flow to provide a source of hydrogen for the passivation of dielectric defects. Figure 2 is a schematic illustration of the process flow of another exemplary embodiment of a fabrication process according to the present invention. The structure of Figure 2A comprises a NMOS region 101 and a PMOS region 102 within a substrate 104. An ion or atom implantation stepl21, illustrated in Figure 2B, is then performed through the existing gate stack, as before. In next steps, a thin dielectric layer 111 is deposited or grown on the substrate, followed by a gate electrode 112 formation, as illustrated in Figure 2C. An optional annealing step, which is applied for example 20 minutes at 350°C, is performed to diffuse the passivating impurities into the dielectric layer. In a following step, the transistor fabrication is finalized, as shown in Figure 2D, including the sub-steps of gate etching, source 131 or 133 and drain 132 or 134 extension implantation, spacer 135 formation, thermal activation and suicide 136 formation. Figure 3 is a schematic illustration of the process flow of still another exemplary embodiment of a fabrication process according to the present invention. The structure of Figure 3 A comprises a NMOS region 101 and a PMOS region 102. In first and second steps, a thin dielectric layer 111 is formed on the substrate, followed by a gate electrode 112 formation, as illustrated in Figure 3B. In a following step, the transistor fabrication is finalized, as shown in Figure 3C, including the sub-steps of gate etching, source 131 or 133 and drain 132 or 134 extension implantation, spacer 135 formation and suicide 136 formation. An ion or atom implantation step 121, illustrated in Figure 3D, is then performed through the existing gate stack, as before. An annealing step is finally performed after the implantation step in order to diffuse hydrogen into the dielectric layer so as to facilitate passivation and to remove defects in the substrate generated by the ion implantation. Alternatively, the thermal steps associated with suicide formation can be sufficient for passivation and defect annealing. The fabrication process in accordance with this embodiment is particularly efficient. As a matter of facts, the later the passivating impurities are introduced in the process, the better it is because this limits the changes of de-passivation during further processing.
Any reference sign in the following claims should not be construed as limiting the claim. It will be obvious that the use of the verb "to comprise" and its conjugations do not exclude the presence of any other steps or elements besides those defined in any claim. The word "a" or "an" preceding an element or step does not exclude the presence of a plurality of such elements or steps.

Claims

1 A method of fabricating metal-oxide semiconductor integrated circuit devices, said method comprising the steps of: forming a dielectric layer on a substrate, forming a gate electrode on said dielectric layer, implanting passivating impurities in the substrate, and performing a thermal treatment, the passivating impurities being adapted to passivate dielectric defects within the dielectric layer during said thermal treatment.
2 A method as claimed in claim 1, wherein the gate electrode is a metallic gate electrode.
3 A method as claimed in claim 2, wherein the step of implanting passivating impurities in the substrate is performed through the metallic gate electrode and the dielectric layer.
4 A method as claimed in claim 1, wherein the passivating impurities are chosen among hydrogen, deuterium, fluorine, nitrogen or chlorine.
5 A method as claimed in claim 1, wherein the dielectric layer is of the high permittivity type.
6 A method as claimed in claim 3, wherein the high permittivity dielectric layer includes Hafnium silicate HfSixOy.
7 An apparatus for fabricating metal-oxide semiconductor integrated circuit devices characterized in that it comprises: means for forming a dielectric layer on a substrate, - means for forming a gate electrode on said dielectric layer, means for implanting passivating impurities in the substrate, and means for performing a thermal treatment, the passivating impurities being chosen such that they passivate dielectric defects within the dielectric layer during said thermal treatment. 8 A metal oxide semiconductor integrated circuit device fabricated by the method according to any one of claims 1 to 6.
PCT/IB2005/000248 2004-02-02 2005-01-31 Method of fabricating metal-oxide semiconductor integrated circuit devices. WO2005076331A1 (en)

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