TW200534339A - Method and apparatus for fabricating ultra-shallow junction metal-oxide semiconductor integrated circuit devices - Google Patents

Method and apparatus for fabricating ultra-shallow junction metal-oxide semiconductor integrated circuit devices Download PDF

Info

Publication number
TW200534339A
TW200534339A TW093137840A TW93137840A TW200534339A TW 200534339 A TW200534339 A TW 200534339A TW 093137840 A TW093137840 A TW 093137840A TW 93137840 A TW93137840 A TW 93137840A TW 200534339 A TW200534339 A TW 200534339A
Authority
TW
Taiwan
Prior art keywords
source
drain
substrate
region
gate
Prior art date
Application number
TW093137840A
Other languages
Chinese (zh)
Inventor
Frederic Salvetti
Etienne Robilliart
Alexandre Dray
Francois Wacquant
Damien Lenoble
Ramiro Palla
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Publication of TW200534339A publication Critical patent/TW200534339A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Ceramic Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method and apparatus for fabricating a metal oxide semiconductor integrated circuit device, the method comprising sequentially: (a) providing a gate (106) on a substrate (100); (b) providing a spacer (108) on a sidewall of said gate (106); (c) forming a source/drain region (110) in said substrate (100); (d) substantially completely removing said spacer (108); (e) forming a source/drain extension region (114) in said substrate (100); (f) forming a source drain pocket region (116) in said substrate (100), beneath said gate (106); and (g) performing an annealing process to substantially simultaneously electrically activate said source/drain region (110), said source/drain extension region (114) and said source/drain pocket region (116).

Description

200534339 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種用於製造一超淺接合面金屬氧化物半 導體積體電路元件的方法與裝置，更明確地說，係關於一 種用於製造一具有超淺、低片阻源極/汲極接合面、以及改 良短通道效能的金屬氧化物半導體積體電路元件的方法與 裝置。 一 【先前技術】 超大型積體電路（VLSI)的發展係沿著大晶圓尺寸與小線 寬的方向進行。此發展趨勢會強化積體電路的功能並且降 低Ik成本。當細小積體電路的金屬氧化物半導體電晶體 的元件尺寸時，通道長度便會隨之縮減，以提高該電晶體 的運作速度。 當遠等金屬氧化物半導體（MOS)電晶體的尺寸縮小至 0·1 μιη以下時，為達到持續改良積體電路密度與效能的目 的’便會浮現大量新的技術問題。其中一項問題係需要新 的技術來形成超淺接合面，用以提供足夠低的片阻。 當元件尺寸被微型化之後，由於通道長度縮減的關係， 該源極/汲極區的空乏層與該通道便經常會發生重疊。通道 長度越短’該源極/汲極區的重疊比例便越大。結果便會縮 減實際的通道長度，此現象稱為短通道效應。 若欲解決上述的問題，可形成一輕度摻雜汲極（LDD)。不 過，當線寬小於0.25微米時，該LDD的深度便必須進一步縮 減。因此，阻值會提高，而元件的速度便會因而下降，當 98158.doc 200534339 Λ 口等並不樂見此現象。所以，為避免發生此問題，可 形成一具較高摻雜質濃度的源極/汲極擴充區，用以取代該 輕度摻雜區。 ί考。亥專圖式中的圖1 a，於先前技術的金屬氧化物半導 體兀件製程中，會於一具有一介電層11的基板12之上形成 一閘極10。接著，便會於該基板10之上實施離子植入，用 以形成該等輕度摻雜汲極（LDD)區14，如該等圖式的圖lb 中概略所示。接著，會於該閘極10的側護壁之上形成一分籲 隔體16，如圖lc所示，並且實施源極/汲極植入製程，用以 於該基板中形成一源極/汲極區18，如該等圖式的圖丨4所 不。最後，於該矽晶圓進行熱製程（例如退火）以修復晶體結 構並且引入該等摻雜質之後，便可於該元件的源極區、汲 極區、以及閘極區之上形成複數個矽化物接點2〇，用以產 生如該等圖式的圖1 e概略所示般的結構。 上述的先前技術製程包含至少兩道退火步驟，換言之， 分隔體退火沉積以及矽化物退火反應與相位轉變。上述用 · 於活化的源極/汲極退火進一步效能係會造成該等擴充區 過度擴政，更明確地說，會瓖該源極/汲極擴充區產生橫向 擴散’伴隨著提南接合面深度，進而讓該元件受到短通道 效應的影響。 為避免發生此現象，已經有人提出於進行擴充區植入前 增加一偏移分隔體。不過，如此便會讓處理流程複雜化， 並且降低總處理S。即使解決其中一項問題，但是，因為 有效通道長度增加的關係’該擴充接合面的深度依然不符 98158.doc 200534339 障下降效應並且導 需要’如此便會造成大量的汲極誘發屏 致不佳的元件製造率。 【發明内容】 所以，本發明的目的係提供 導體積體電路元件的方法與裝 擴充區以及對珠源極與汲極擴 化控制效果會優於先前技術。 一種用於製造金屬氧化物半 置，其中對超淺源極與汲極 充區來說，其摻雜輪廓與活 根據本發明’提供一種用制 一 裡用於裹仏孟屬虱化物半導體積體 電路元件的方法，該方法包括下面的步驟·· a) 於一基板之上提供一閘極； b) 於該閘極的一側護壁之上提供一分隔體，· c) 於该基板中形成一源極/汲極區； d) 實質完全移除該分隔體； e) 於該基板中形成一源極/汲極擴充區； f) 於該基板中，該閘極的下方形成_源極汲極袋狀區； 以及 g)實施一退火製程，用以電活化該源極/汲極區、該源極 /沒極擴充區、以及該源極/汲極袋狀區。 本發明還可延伸至一種用於利用上述方法來製造金屬氧 化物半導體積體電路元件的裝置，該元件於一基板上包括 一閘極，該裝置包括·· a)提供構件，用以於該閘極的一側護壁之上提供一分隔 體； b)形成構件，用以於該基板中形成一源極/汲極區； 98158.doc 200534339 c) 移除構件，用以實質完全移除該分隔體； d) 形成構件，用以於該基板中形成一源極/没極擴充區； Ο形成構件，用以於該基板中，該閘極的下方形成一源 極/汲極袋狀區；以及 f)實施構件，用以實施退火製程，以便活性化該源極/汲 極區、該源極/汲極擴充區、以及該源極/汲極袋狀區。 本發明還可進一步延伸至一種以上述方法製造而成的金 屬氧化物半導體積體電路元件。 於本發明的較佳具體實施例中，在移除該分隔體之前， 會先於该閘極以及該等源極/汲極區的裸露部份之上形成 一矽化物層。 較佳的係，藉由實施一斜角植入製程來形成該源極/汲極 袋狀區。於本發明的其中一具體實施例中，會利用一第一 植入步驟來形成該源極/汲極擴充區，並且利用一第二、斜 角植入步驟來形成該源極/汲極袋狀區。於本發明的替代示 範具體實施例中，可利用單一斜角植入步驟來形成該源極/ 及極擴充區及泫源極/汲極袋狀區，於此情況中，最好可於 忒植入步驟前方先實施一前置非晶化植入步驟。 舉例來說，該退火製程可能包括一超快速退火製程，以 便不會損及該矽化物層或是使其呈現相變情形；或是包括 一慣用的尖峰退火製程。於該退火步驟之後，便可於該閘 極的忒等側濩壁之上提供複數個低溫分隔體，以允許形成 複數個無邊界接點。 茶考下文所述的具體實施例即可明白且闡述本發明的這 98158.doc 200534339 些及其它方面。 【實施方式】 積的提供一種用於製造-金屬氧化物半導體 "二：”法與裝置，其中源極/沒極擴充區的擴散 !·月开m會被限制在需要其電活化作用的地方。 吾等已經設計出該改良配置。 參考該等圖式的圖2,圖中提供一基板1〇〇，其中已經植 :N井與P井。絲板1〇〇具備一介電層⑽，其上會根據熟 習本技術的人士所熟知的々 ^ 们原理，儿積一由多晶矽製成的全片 ，如圖23所示。舉例來說，該介電層包含一氧化物（舉 例來說，si〇2)、-氮氧化物（舉例來說，si〇2+si3⑹、或 是一高介電常數的材料（舉例來說，Hf02)。 就在該沉積步驟後面，會姓刻該多晶石夕層104，用以形成 一閘極106，如圖2b所示。 如該等圖式中的圖2c所示，於下一道步驟中，會藉由下 面方式於該閘極106的該側護壁之上形成一分隔體1〇8 :(例 如）於該基板之上形成一氮化矽層並且覆蓋該閘極1〇6，然 後於該氮化矽層之上實施一各向異性的蝕刻製程。 接著，可於該基板100之上實施源極/汲極植入，穿過該 ”包層102，用以於該基板100中靠近分隔體1〇8的外緣處形 成一重度摻雜源極/汲極區1丨〇(圖2d)。該植入步驟會適應於 以相應於第一類型離子的第一預設能量來植入該類型的離 子用以形成一重度摻雜區。舉例來說，可以約1 〇 keV的 月包量來楂入砷（As)離子。熟習本技術的人士將會發現，必 98158.doc -10- 200534339 要時，可在植入前增加一犧牲層。 可只鈿一犧牲氧化物蝕刻步驟，用以移除未被該閘極1〇4 與該分隔體108覆蓋的介電層1〇2(圖2e)。 /接著，可於該閘極106與該源極/汲極區11〇的裸露表面上 形成自動對齊石夕化物層112，如該等圖式的圖2f所示。舉例 來說，可藉由下面方式來形成自動對齊矽化物層丨12 ··於覆 1孩閘極106的基板1 〇〇之上形成一金屬層（例如鈦），接著 執行熱處理製程，用以讓該閘極丨〇6與該源極/汲極區丨1 〇和 忒金屬層進行反應以形成自動對齊矽化物層丨丨2。多餘的未 反應金屬層會被移除。 於此階段中，可利用數種不同的方法來完成其餘製程， 現在將針對此部份來更詳細說明本發明的兩個示範具體實 施例。 簽考該等圖式的圖3，根據本發明的第一示範具體實施 例叾元王移除用於控制該源極/汲極植入製程且避免發生 石夕化物橋接作用的該等分隔體1〇8(圖3a)。 接著，可於該基板1〇〇之上實施一植入製程，用以於該基 板100中先前被該分隔體108覆蓋的位置處形成一源極/汲 極擴充區114(也就是，輕度摻雜區），如該等圖式的圖补所 示。該植入步驟會適應於以相應於第一類型離子的第二預 。又月b i來植入該類型的離子，用以形成一輕度換雜區。舉 例來說，可以約1 keV的能量來植入硼（B)離子。 接著，可於該基板100之上實施一斜角植入製程，用以於 該基板100中，該閘極106的側邊下方處形成複數個源極/汲 98158.doc •11- 200534339 極袋狀區116，如該蓉式沾固。以 寺圖式的圖3c所示。該斜角植入步驟會 適應於以相應於第二類型離子的 ― 丁的弟二預设能ϊ來植入該類 型的離子，用以形成一會声狹M r^ 、200534339 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a method and device for manufacturing an ultra-shallow junction metal oxide semiconductor integrated circuit element, and more specifically, it relates to a method for manufacturing A method and device for metal oxide semiconductor integrated circuit elements with ultra-shallow, low chip resistance source / drain junctions and improved short-channel performance. I. [Previous Technology] The development of very large scale integrated circuits (VLSI) is carried out along the direction of large wafer size and small line width. This development trend will strengthen the function of integrated circuits and reduce Ik costs. When the element size of the metal oxide semiconductor transistor of the small integrated circuit is reduced, the channel length is reduced accordingly to increase the operation speed of the transistor. When the size of distant metal-oxide-semiconductor (MOS) transistors is reduced to below 0.1 μm, in order to achieve the goal of continuously improving the density and performance of integrated circuits, a large number of new technical problems will emerge. One problem is the need for new technologies to form ultra-shallow junctions to provide sufficiently low sheet resistance. After the component size is miniaturized, the empty layer in the source / drain region often overlaps with the channel due to the reduction of the channel length. The shorter the channel length, the greater the overlap ratio of the source / drain regions. As a result, the actual channel length is reduced. This phenomenon is called the short channel effect. To solve the above problems, a lightly doped drain (LDD) can be formed. However, when the line width is less than 0.25 microns, the depth of the LDD must be further reduced. Therefore, the resistance value will increase, and the speed of the component will decrease accordingly. This phenomenon is not welcome when 98158.doc 200534339 Λ mouth and so on. Therefore, to avoid this problem, a source / drain extension region with a higher dopant concentration can be formed to replace the lightly doped region. ί 考. FIG. 1 a in the specific drawings is a gate electrode 10 formed on a substrate 12 having a dielectric layer 11 in the prior art metal oxide semiconductor device manufacturing process. Next, an ion implantation is performed on the substrate 10 to form the lightly doped drain (LDD) regions 14 as shown schematically in FIG. 1b of the drawings. Next, a minute spacer 16 is formed on the side guard wall of the gate electrode 10, as shown in FIG. 1c, and a source / drain implantation process is performed to form a source / drain in the substrate. Polar region 18, as shown in Figure 4 of these diagrams. Finally, after the silicon wafer is thermally processed (such as annealing) to repair the crystal structure and the dopants are introduced, a plurality of elements can be formed on the source region, the drain region, and the gate region of the device. The silicide contact 20 is used to produce a structure as schematically shown in FIG. 1e of the drawings. The aforementioned prior art process includes at least two annealing steps, in other words, spacer annealing deposition and silicide annealing reaction and phase transition. The further effectiveness of the above-mentioned source / drain annealing for activation will cause excessive expansion of these expansion areas, and more specifically, it will cause the source / drain expansion area to spread laterally. Depth, which in turn exposes the element to short-channel effects. To avoid this, it has been proposed to add an offset divider before implanting the expansion area. However, this complicates the processing flow and reduces the total processing S. Even if one of the problems is solved, because of the increase in effective channel length, 'the depth of the expanded joint surface still does not match. Component manufacturing rate. [Summary of the Invention] Therefore, the object of the present invention is to provide a method and a method for mounting a bulk circuit element and an expansion region, and the effect of controlling the expansion of the bead source and the drain is better than that of the prior art. A method for manufacturing a metal oxide half-set, in which the doping profile and activity of an ultra-shallow source and drain charge region are in accordance with the present invention. A method for a bulk circuit element, which includes the following steps: a) providing a gate electrode on a substrate; b) providing a separator on a side wall of the gate electrode, c) in the substrate Forming a source / drain region; d) substantially completely removing the separator; e) forming a source / drain extension region in the substrate; f) forming a source under the gate in the substrate The electrode-drain pocket region; and g) performing an annealing process for electrically activating the source / drain region, the source / impulse extension region, and the source / drain pocket region. The present invention may also be extended to a device for manufacturing a metal oxide semiconductor integrated circuit element using the above method, the element including a gate on a substrate, the device including ... a) providing a component for the A partition is provided on one side of the gate; b) forming a member for forming a source / drain region in the substrate; 98158.doc 200534339 c) removing the member for substantially completely removing the A separator; d) a forming member for forming a source / non-electrode expansion region in the substrate; 0 forming member for forming a source / drain pocket region under the gate in the substrate And f) an implementing member for performing an annealing process to activate the source / drain region, the source / drain extension region, and the source / drain pocket region. The present invention can be further extended to a metal oxide semiconductor integrated circuit element manufactured by the above method. In a preferred embodiment of the present invention, before removing the separator, a silicide layer is formed on the gate and exposed portions of the source / drain regions. Preferably, the source / drain pocket region is formed by performing an oblique implantation process. In a specific embodiment of the present invention, a source / drain expansion region is formed using a first implantation step, and a source / drain pocket is formed using a second, beveled implantation step. Like area. In an alternative exemplary embodiment of the present invention, a single bevel implantation step may be used to form the source / and-electrode extension region and the source / drain pocket region. In this case, it may be better to A pre-amorphization implantation step is performed before the implantation step. For example, the annealing process may include an ultra-fast annealing process so as not to damage the silicide layer or cause it to undergo a phase change; or it may include a conventional spike annealing process. After the annealing step, a plurality of low-temperature separators can be provided above the 濩 and other side walls of the gate to allow the formation of a plurality of unbounded contacts. Tea can understand and explain these 98158.doc 200534339 and other aspects of the present invention by studying the specific embodiments described below. [Embodiment] Provide a method for manufacturing-metal oxide semiconductor "two:" method and device, in which the diffusion of the source / non-polar extension region! · Moon open m will be limited to the need for its electrical activation We have devised this improved configuration. With reference to Figure 2 of these drawings, a substrate 100 is provided in the figure, where N and P wells have been implanted. The wire plate 100 has a dielectric layer. Based on the principles well known to those skilled in the art, a monolithic wafer made of polycrystalline silicon is shown in Figure 23. For example, the dielectric layer contains an oxide (for example Say, SiO2), -Nitrogen oxide (for example, SiO2 + si3⑹), or a high dielectric constant material (for example, Hf02). Just after the deposition step, the name will be engraved The polycrystalline stone layer 104 is used to form a gate 106, as shown in FIG. 2b. As shown in FIG. 2c of the drawings, in the next step, the gate 106 is formed in the following manner. A separator 108 is formed on the side protective wall: (for example) a silicon nitride layer is formed on the substrate and covers the gate 106, and then an anisotropic etching process is performed on the silicon nitride layer. Next, a source / drain implantation may be performed on the substrate 100 and passed through the "cladding layer 102" for A heavily doped source / drain region 1 (see FIG. 2d) is formed at the outer edge of the substrate 100 near the separator 108 (FIG. 2d). A predetermined energy is used to implant this type of ions to form a heavily doped region. For example, arsenic (As) ions can be introduced at a monthly volume of about 10 keV. Those skilled in the art will find If necessary, a sacrificial layer can be added before implantation. Only a sacrificial oxide etching step can be performed to remove the gate electrode 104 and the separator 108 that are not covered by the sacrificial oxide etching step. The dielectric layer 10 (Fig. 2e). / Next, an automatic alignment fossil material layer 112 can be formed on the exposed surfaces of the gate 106 and the source / drain region 110, as shown in the drawings. As shown in Fig. 2f. For example, the self-aligned silicide layer can be formed in the following manner. 12 ··· On the substrate 100 covering the gate 106 A metal layer (such as titanium) is formed, and then a heat treatment process is performed to allow the gate electrode 〇06 to react with the source / drain region 010 and the hafnium metal layer to form an auto-aligned silicide layer 丨 2. The excess unreacted metal layer will be removed. At this stage, several different methods can be used to complete the remaining processes. Now, two exemplary embodiments of the present invention will be described in more detail for this part. Figure 3 of the drawings, according to the first exemplary embodiment of the present invention, the king Yuan removes the separators 1 which are used to control the source / drain implantation process and avoid stone bridging. 8 (Figure 3a). Next, an implantation process can be performed on the substrate 100 to form a source / drain expansion region 114 at a position previously covered by the separator 108 in the substrate 100. (Ie, lightly doped regions), as shown in the figure's complement. This implantation step will be adapted to a second prediction corresponding to the first type of ions. This type of ion is implanted again to form a mildly doped region. For example, boron (B) ions can be implanted at an energy of about 1 keV. Next, an oblique implantation process can be performed on the substrate 100 to form a plurality of source electrodes at the bottom of the substrate 100 below the sides of the gate electrode 106158.doc • 11- 200534339 The shaped region 116 is as solid as the lotus root. This is shown in Figure 3c with a temple pattern. The oblique implantation step is adapted to implant the type of ions with the predetermined energy of the second type of ions, Ding, to form a narrow sound band M r ^,

更度4雜區。舉例來說，可以約50keV 的能量來植人相子。熟習本技術的人士將會發現可利用4 more miscellaneous areas. For example, it can be planted with energy of about 50keV. Those skilled in the art will find available

As離子作為第-類型離子且利㈣離子作為第二類型離子， 而As離子與B離子以外的離子則可使用於不同的植入步驟 中〇 可實施一直接表面退火（DSA)製程（對矽化物112而言其 並不具破壞性），用以實質同時退火且電活化該等袋狀區 116、該源極/汲極區11〇、以及該源極/汲極擴充區ιΐ4(圖 3d)。此退火製程非常快速，所以，該矽化物應該不會受到 損害而且應該不會受到相變作用的影響。 最後，必要時，可根據慣用製程來沉積一低溫分隔體 118(圖3e) ’以便形成複數個無邊界接點。 利用此製程順序，便可獨立於該源極/汲極區丨丨〇(雖然實 質上係與其同時）來明確退火且活化該等源極/汲極擴充區 114 〇 參考該等圖式的圖4，根據本發明的第二示範具體實施 例’會兀全移除用於控制該源極/沒極植入製程且避免發生 石夕化物橋接作用的該等分隔體1〇8(圖4a)。 接著可貫施一前置非晶化製程植入PAi步驟。於此步驟 中’會將離子植入該半導體基板100之中，用以於該基板1〇〇 中形成複數個非常深的非晶區12〇。舉例來說，可植入Si、 Ge或Ar離子，用以破壞晶格鍵結，並且於該基板1〇〇中產生 98158.doc -12- 200534339 一無晶或非晶矽區1 20，如該等圖式的圖4b所示。 接著，可於該基板1 00之上實施一植入製程，用以和以前 一樣地於該基板1〇〇中先前被該分隔體1〇8覆蓋的位置處形 成一源極/汲極擴充區1 1 4，接著，可於該基板i 之上實施 一斜角植入製程，用以和以前一樣地於該基板1〇〇中形成複 數個源極/汲極袋狀區116，該等袋狀區116會延伸於該閘極 106的側邊下方處，如該等圖式的圖4c所示。 可實施一直接表面退火（DSA)製程（對該矽化物而言其並 不具破壞性），用以和以前一樣地實質同時退火且電活化該 等袋狀區116、該源極/汲極區ι10、以及該源極/汲極擴充區 114(圖4d)。由於此DSA製程的關係，可修復該等非晶區12〇 中的缺陷，而且該等非晶區12〇會消失。或者，可實施慣用 的尖峰退火製程，用以實質同時退火且電活化該等袋狀區 116、該源極/汲極區110 '以及該源極/汲極擴充區114。舉 例來說’該尖峰退火步驟的持續時間低於一秒，而且施用 的溫度（例如）等於或高於lOOOt：。 最後，必要時，可根據慣用製程來沉積一低溫分隔體 118(圖4e)，以便形成複數個無邊界接點。 應注意’以上提及的具體實施例係用以說明本發明而非 限制本發明，熟習本技術者將能夠設計多種替代具體實施 例’而不致背離隨附申請專利範圍所定義的本發明的範_。 在申請專利範圍中，任何置於括號之間的參考符號均不應 視為限制該申請專利範圍。「包括」以及類似的詞語並未 任何申請專利範圍或整份說明書中所列以外的元件或步 98158.doc 200534339 ::的兀件亦未排除有複數個此等元件存在，反之亦 二本發明可利用包括數個不同元件的硬體來實施，亦可 使=過適當程式化的電蹈來實施。在一列舉數項構件的 :::專利謝’該些構件中的數者均可 體化。雖然於互不相同的相關申請專利範圍中來 陳述特定的措施，不過，A並 - 一 X不表不結合該歧措施來#用 便無法突顯其優點。 日Ά吏用 【圖式簡單說明】 明上:已經參考隨附的圖式並透過範例來詳細說明本發 ^ > τ · 為根據先前技術用於製造一金屬氧化物半導體積體 70件的主處王里流程步驟的概略剖面圖； -圖2為根據本發明—示範具體實施例用於製造—金屬氧 物半導體積體電路元件的主初始處理流程步驟的概略 剖面圖； ^為根據本發明—第-示範具體實施例心製造-金 屬乳化物半導體積體電路元件的主接續處理流程步驟的 概略剖面圖；以及 =為根據本發明一第二示範具體實施例用於製造一金 屬氧化物半導體積體電路元件的主接續處理流程步驟的 概略剖面圖。 【主要元件符號說明】 10 間極 介電層 98158.doc -14- 11 200534339 12 基板 14 輕度摻雜汲極區 16 分隔體 18 源極/沒極區 20 接點 100 基板 102 介電層 104 多晶矽層 106 閘極 108 分隔體 110 源極/沒極區 112 石夕化物層 114 源極/汲極擴充區 116 源極/汲極袋狀區 118 分隔體 120 非晶區As ions are used as the first type ions and Rhenium ions are used as the second type ions, while ions other than As ions and B ions can be used in different implantation steps. A direct surface annealing (DSA) process can be implemented (for silicidation) Material 112 is not destructive), and is used to substantially simultaneously anneal and electrically activate the pouch regions 116, the source / drain region 110, and the source / drain extension region 4 (Figure 3d). . This annealing process is very fast, so the silicide should not be damaged and should not be affected by phase transitions. Finally, if necessary, a low temperature separator 118 (Fig. 3e) 'can be deposited according to a conventional process so as to form a plurality of unbounded contacts. With this process sequence, the source / drain region can be explicitly annealed and activated independently of the source / drain region (although substantially at the same time) 114 〇 Refer to the diagrams of the diagrams 4. According to the second exemplary embodiment of the present invention, the separators 108 for controlling the source / non-electrode implantation process and avoiding the bridging effect of lithoxide will be completely removed (Fig. 4a). . Then, a pre-amorphization process can be performed to implant PAi. In this step, ions are implanted into the semiconductor substrate 100 to form a plurality of very deep amorphous regions 12 in the substrate 100. For example, Si, Ge, or Ar ions can be implanted to destroy the lattice bond and generate 98158.doc -12- 200534339 in the substrate 100, such as an amorphous or amorphous silicon region 1 20, such as The diagrams are shown in Figure 4b. Then, an implantation process can be performed on the substrate 100 to form a source / drain extension area at the position previously covered by the separator 108 in the substrate 100 as before. 1 1 4. Next, a bevel implantation process can be performed on the substrate i to form a plurality of source / drain pocket regions 116 in the substrate 100 as before, such pockets The shaped region 116 extends below the sides of the gate electrode 106, as shown in FIG. 4c of the drawings. A direct surface annealing (DSA) process (which is not destructive to the silicide) can be implemented to anneal and electrically activate the pouch regions 116 and the source / drain regions substantially simultaneously as before ι10, and the source / drain extension region 114 (FIG. 4d). Due to the DSA process, the defects in the amorphous regions 120 can be repaired, and the amorphous regions 120 will disappear. Alternatively, a conventional spike annealing process may be performed to anneal and electrically activate the pouch regions 116, the source / drain region 110 ', and the source / drain extension region 114 at substantially the same time. For example, 'the duration of the spike annealing step is less than one second, and the application temperature is, for example, equal to or higher than 100 t :. Finally, if necessary, a low temperature separator 118 (Fig. 4e) can be deposited according to conventional processes to form a plurality of borderless contacts. It should be noted that the above-mentioned specific embodiments are intended to illustrate the present invention and not to limit the present invention. Those skilled in the art will be able to design a variety of alternative specific embodiments without departing from the scope of the present invention as defined by the scope of the appended patents. _. Within the scope of a patent application, any reference signs placed between parentheses shall not be construed as limiting the scope of the patent application. "Include" and similar words do not include any elements or steps other than those listed in the scope of the patent application or the entire specification. It can be implemented with hardware that includes several different components, or it can be implemented with a properly programmed circuit. ::: Patent Thanks', which lists several components, can be embodied in several of these components. Although specific measures are stated in the scope of related patent applications that are different from each other, however, A does not mean that it cannot be used in combination with the different measures to highlight its advantages. The Japanese official used [Schematic description] The above description: The present invention has been explained in detail with reference to the accompanying drawings and examples ^ > τ · It is used to manufacture 70 metal oxide semiconductor integrated bodies according to the prior art A schematic cross-sectional view of the main steps of the Wangli process;-FIG. 2 is a schematic cross-sectional view of the main initial process steps of a metal oxide semiconductor integrated circuit element for manufacturing—a metal oxide semiconductor integrated circuit element according to the present invention—an exemplary embodiment; Invention-First-Exemplary Embodiment Heart-manufacturing-A schematic cross-sectional view of the main continuation process steps of a metal emulsion semiconductor integrated circuit element; and = for a second exemplary embodiment of the present invention for producing a metal oxide A schematic cross-sectional view of a main connection process flow step of a semiconductor integrated circuit element. [Description of main component symbols] 10 interlayer dielectric layers 98158.doc -14- 11 200534339 12 Substrate 14 Lightly doped drain region 16 Separator 18 Source / inverted region 20 Contact 100 Substrate 102 Dielectric layer 104 Polycrystalline silicon layer 106 Gate 108 Separator 110 Source / inverted region 112 Lithium oxide layer 114 Source / Drain extension region 116 Source / Drain pocket region 118 Separator 120 Amorphous region

98158.doc -15-98158.doc -15-

Claims (1)

200534339 十、申請專利範圍： 1. 一種用以金屬氧化物半導體積體電路元件的製造方去 該方法包括下面的步驟： (a) 於基板（100)之上提供一閘極（1〇6); (b) 於該閘極（106)的一側護壁之上提供一分隔體（1〇8) · (0 於該基板（100)中形成一源極/汲極區（11〇); (d) 實質完全移除該分隔體（1〇8); (e) 於該基板（1〇〇)中形成一源極/汲極擴充區（114); (f) 於該基板（1〇〇)中，該閘極（106)的下方形成一源極/ 汲極袋狀區（116);以及 (g) 實施一退火製程，用以電活化該源極/汲極區（11〇)、 該源極/汲極擴充區（114)、以及該源極/汲極袋狀區 (116) 〇 2·如清求項1之方法，其中，在移除該分隔體（108)之前，會 先於W亥閘極（1 〇6)以及該等源極/汲極區（1 1 〇)的裸露部份 之上形成一矽化物層（112)。 3 ·如明求項1至2任一項之方法，其中藉由一第一植入步驟 來形成该源極/汲極擴充區（114)。 4·=明求項1至2任一項之方法，其中實施一第二斜角植入 製矛乂开〆成该源極/汲極袋狀區（j ^ 6)。 月长項3之方法，其中於該第一植入步驟之前先實施一 前置非晶化植入步驟。 6 · 如請求j苜·| & +、， 、之方法，其中該退火製程包括〆直接表面退火 仏或是一尖峰退火製程。 98158.doc 200534339 7·如明求項1之方法，其中於該退火步驟之後，可於該閘極 (1〇6)的该等側護壁之上提供複數個低溫分隔體（128)，以 允許形成複數個無邊界接點。 8·種藉由根據請求項1至7任一項製造金屬氧化物半導體 積體電路凡件之方法的裝置，該元件於基板（1G0)之上包 括一閘極（106)，該裝置包括： (勾提供構件，用以於該閘極（1〇6)的一側護壁之上提供 一分隔體（108); (b)形成構件，用以於該基板（100)中形成一源極/汲極區 (110); ()私除構件，用以貫質完全移除該分隔體（1⑽）； (d) 形成構件，用以於該基板（100)中形成一源極/汲極擴 充區（114); (e) 形成構件，用以於該基板（100)中，該閘極（1〇6)的下 方形成一源極/汲極袋狀區（1丨6);以及 ⑴實施構件，用以實施一退火製程，以便電活化該源 極/汲極區（110)、該源極/汲極擴充區（114)、以及該 源極/汲極袋狀區（116)。 9_ 一種藉由根據請求項丨至7中任何一項之方法所製成的金 屬氧化物半導體積體電路元件。 10. 一種藉由根據請求項丨至7中任何一項之方法所製成的金 屬氧化物半導體積體電路元件，其包括： -一基板（100); -一位於該基板（100)之上的介電層（1〇2); 98158.doc 200534339 一位於該介電層（102)之上的閘極（106); 凡素的重 一形成於該基板（100)中之含有第一類型接雜 度摻雜源極/汲極區（110); 一形成於該基板（100)中之含有該第一類刚换μ 、私雜元素的 輕度摻雜源極/汲極擴充區（114); 一形成於該基板（100)中、該閘極（1〇6)下方之含有二類 型換雜元素的重度接雜源極/汲極袋狀區（1 1 6 )。200534339 10. Scope of patent application: 1. A method for manufacturing a metal oxide semiconductor integrated circuit element. The method includes the following steps: (a) providing a gate electrode (106) on a substrate (100); (b) providing a separator (108) on a side wall of the gate electrode (106); (0 forming a source / drain region (11〇) in the substrate (100); d) substantially completely removing the separator (108); (e) forming a source / drain extension region (114) in the substrate (100); (f) in the substrate (100) ), A source / drain pocket region (116) is formed below the gate (106); and (g) an annealing process is performed to electrically activate the source / drain region (11), The source / drain extension region (114) and the source / drain pocket region (116). If the method of item 1 is clear, before removing the separator (108), A silicide layer (112) is formed before the exposed portions of the W Hai gate (106) and the source / drain regions (1 10). 3 · If the term 1 to 2 is required One method, wherein the method is formed by a first implantation step Source / drain expansion region (114). 4 · = A method of any one of items 1 to 2 in which a second bevel implantation spear is opened to form the source / drain pocket region. (J ^ 6). The method of term 3, in which a pre-amorphous implantation step is performed before the first implantation step. 6 · If a request is made for alfalfa ||, & Wherein, the annealing process includes “direct surface annealing” or a spike annealing process. 98158.doc 200534339 7 · The method of item 1 is determined, wherein after the annealing step, the gate electrode (106) can be A plurality of low-temperature separators (128) are provided on the side protective walls to allow the formation of a plurality of unbounded contacts. 8. Types of metal oxide semiconductor integrated circuit components manufactured by any one of claims 1 to 7 The device of the method includes a gate electrode (106) on the substrate (1G0). The device includes: (hook providing means for providing a gate wall on one side of the gate electrode (106)). Separator (108); (b) forming a member for forming a source / drain region (110) in the substrate (100); () removing the member For completely removing the separator (1⑽); (d) forming a member for forming a source / drain expansion region (114) in the substrate (100); (e) forming a member for In the substrate (100), a source / drain pocket region (1 丨 6) is formed below the gate electrode (106); and an implementation member is used to implement an annealing process so as to electrically activate the A source / drain region (110), the source / drain extension region (114), and the source / drain pocket region (116). 9_ A metal oxide semiconductor integrated circuit element manufactured by a method according to any one of claims 1 to 7. 10. A metal oxide semiconductor integrated circuit element made by a method according to any one of claims 1 to 7, comprising:-a substrate (100);-on a substrate (100) Dielectric layer (102); 98158.doc 200534339 a gate (106) located above the dielectric layer (102); the first layer of Fansu formed in the substrate (100) contains the first type Doped source / drain region (110); a lightly doped source / drain extension region (1) formed in the substrate (100) and containing the first type of μ and private impurity elements ( 114); A heavily doped source / drain pocket region (1 1 6) containing two types of doping elements formed in the substrate (100) and under the gate (106). 98158.doc98158.doc
TW093137840A 2003-12-10 2004-12-07 Method and apparatus for fabricating ultra-shallow junction metal-oxide semiconductor integrated circuit devices TW200534339A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP03300257 2003-12-10

Publications (1)

Publication Number Publication Date
TW200534339A true TW200534339A (en) 2005-10-16

Family

ID=34673636

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093137840A TW200534339A (en) 2003-12-10 2004-12-07 Method and apparatus for fabricating ultra-shallow junction metal-oxide semiconductor integrated circuit devices

Country Status (2)

Country Link
TW (1) TW200534339A (en)
WO (1) WO2005057662A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107104051B (en) * 2016-02-22 2021-06-29 联华电子股份有限公司 Semiconductor element and manufacturing method thereof

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6180472B1 (en) * 1998-07-28 2001-01-30 Matsushita Electrons Corporation Method for fabricating semiconductor device
US20020001910A1 (en) * 1999-02-24 2002-01-03 Chin-Lai Chen Method of forming a mos transistor of a semiconductor
US6319798B1 (en) * 1999-09-23 2001-11-20 Advanced Micro Devices, Inc. Method for reducing lateral dopant gradient in source/drain extension of MOSFET
US6211027B1 (en) * 1999-11-19 2001-04-03 United Microelectronics Corp. Method for manufacturing PMOS transistor
JP2001168323A (en) * 1999-12-06 2001-06-22 Mitsubishi Electric Corp Method of manufacturing semiconductor device
JP2001274263A (en) * 2000-03-23 2001-10-05 Sharp Corp Method of manufacturing for semiconductor device and semiconductor device
US6630385B1 (en) * 2001-04-27 2003-10-07 Advanced Micro Devices, Inc. MOSFET with differential halo implant and annealing strategy
US6429084B1 (en) * 2001-06-20 2002-08-06 International Business Machines Corporation MOS transistors with raised sources and drains
JP3980461B2 (en) * 2001-11-26 2007-09-26 富士通株式会社 Manufacturing method of semiconductor device
JP2003258248A (en) * 2002-03-05 2003-09-12 Mitsubishi Electric Corp Method of manufacturing semiconductor device
JP3746246B2 (en) * 2002-04-16 2006-02-15 株式会社東芝 Manufacturing method of semiconductor device
US6642122B1 (en) * 2002-09-26 2003-11-04 Advanced Micro Devices, Inc. Dual laser anneal for graded halo profile
US6660605B1 (en) * 2002-11-12 2003-12-09 Texas Instruments Incorporated Method to fabricate optimal HDD with dual diffusion process to optimize transistor drive current junction capacitance, tunneling current and channel dopant loss

Also Published As

Publication number Publication date
WO2005057662A2 (en) 2005-06-23
WO2005057662A3 (en) 2005-10-13

Similar Documents

Publication Publication Date Title
US6849516B2 (en) Methods of forming drain/source extension structures of a field effect transistor using a doped high-k dielectric layer
TW535260B (en) Method of manufacturing semiconductor device
TWI325604B (en) Methods of heat-treating a semiconductor wafer
WO2001088991A2 (en) Polysilicon sidewall with silicide formation to produce high performance mosfets
US6734109B2 (en) Method of building a CMOS structure on thin SOI with source/drain electrodes formed by in situ doped selective amorphous silicon
JP2009517860A (en) Method for forming self-aligned Schottky junctions for semiconductor devices
US8044470B2 (en) Semiconductor device and method of fabricating the same
JP2010021525A (en) Manufacturing method for semiconductor device
JP2002539638A (en) Method of manufacturing MIS field-effect transistor
US6313505B2 (en) Method for forming shallow source/drain extension for MOS transistor
JP2009076605A (en) Method of manufacturing semiconductor device
KR101022854B1 (en) Drain/source extension structure of a field effect transistor including doped high-k sidewall spacers
US6100142A (en) Method of fabricating sub-quarter-micron salicide polysilicon
TW200303587A (en) Method of forming different silicide portions on different silicon-containing regions in a semiconductor device
TW200534339A (en) Method and apparatus for fabricating ultra-shallow junction metal-oxide semiconductor integrated circuit devices
US9236440B2 (en) Sandwich silicidation for fully silicided gate formation
JP3866874B2 (en) Method for forming a silicidation element
US6586331B2 (en) Low sheet resistance of titanium salicide process
US9012956B2 (en) Channel SiGe removal from PFET source/drain region for improved silicide formation in HKMG technologies without embedded SiGe
US7211489B1 (en) Localized halo implant region formed using tilt pre-amorphization implant and laser thermal anneal
JPH08204193A (en) Manufacture of semiconductor device
JP2001094100A (en) Fabrication method of semiconductor device
US7067410B2 (en) Method of forming a metal silicide
JP3523627B2 (en) Semiconductor device and manufacturing method thereof
KR100620235B1 (en) Method for manufacturing Ti-silicide