WO2005057662A2 - Method and apparatus for fabricating ultra-shallow junction metal-oxide semiconductor integrated circuit devices. - Google Patents

Method and apparatus for fabricating ultra-shallow junction metal-oxide semiconductor integrated circuit devices. Download PDF

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Publication number
WO2005057662A2
WO2005057662A2 PCT/IB2004/003991 IB2004003991W WO2005057662A2 WO 2005057662 A2 WO2005057662 A2 WO 2005057662A2 IB 2004003991 W IB2004003991 W IB 2004003991W WO 2005057662 A2 WO2005057662 A2 WO 2005057662A2
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Prior art keywords
source
drain
substrate
region
gate
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PCT/IB2004/003991
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French (fr)
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WO2005057662A3 (en
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Frédéric Salvetti
Etienne Robilliart
Alexandre Dray
François Wacquant
Damien Lenoble
Ramiro Palla
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Koninklijke Philips Electronics N.V.
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Definitions

  • This invention relates to a method and apparatus for fabricating an ultra-shallow junction metal-oxide semiconductor integrated circuit device and, more particularly, to a method and apparatus for fabricating a metal-oxide semiconductor integrated circuit device having an ultra-shallow, low sheet-resistance source/drain junction and improved short channel performance.
  • VLSI Very Large Scale Integration
  • MOS metal-oxide semiconductor
  • LDD lightly doped drain
  • a source/drain extension region with a higher dopant concentration is formed to replace the lightly doped region.
  • a gate 10 is formed on a substrate 12 provided with a dielectric layer 11.
  • an ion implantation is performed on the substrate 10 to form the lightly doped drain (LDD) regions 14, as illustrated schematically in Figure lb of the drawings.
  • a spacer 16 is then formed on the sidewall of the gate 10, as shown in Figure lc, and a source/drain implantation process is performed to form a source/drain region 18 in the substrate, as shown in Figure Id of the drawings.
  • suicide contacts 20 are formed on the source, drain and gate regions of the device, to create a structure as illustrated schematically in Figure le of the drawings.
  • the prior art process described above includes at least two annealing steps, namely the spacer annealing deposition and the suicide annealing reaction and phase transformation.
  • the further performance of the above-mentioned source/drain annealing for activation leads to over-diffusion of the extensions, more specifically, lateral diffusion of the source/drain extension region occurs accompanied by an increase in junction depth, which results in the devices suffering from short channel effects.
  • a method of fabricating a metal-oxide semiconductor integrated circuit device comprising the steps of: a) providing a gate on a substrate; b) providing a spacer on a sidewall of said gate; c) forming a source/drain region in said substrate; d) substantially completely removing said spacer; e) forming a source/drain extension region in said substrate; f) forming a source drain pocket region in said substrate, beneath said gate; and g) performing an annealing process to electrically activate said source/drain region, said source/drain extension region and said source/drain pocket region.
  • the present invention also extends to apparatus for fabricating a metal-oxide semiconductor integrated circuit device by the method defined above, the device comprising a gate on a substrate, the apparatus comprising: a) means for providing a spacer on a sidewall of said gate; b) means for forming a source/drain region in said substrate; c) means for substantially completely removing said spacer; d) means for forming a source/drain extension region in said substrate; e) means for forming a source drain pocket region in said substrate, beneath said gate; and f) means for performing an annealing process to electrically activate said source/drain region, said source/drain extension region and said source/drain pocket region.
  • the present invention extends still further to a metal-oxide semiconductor integrated circuit device fabricated according to the method defined above.
  • a suicide layer is formed on said gate and exposed portions of said source/drain regions, prior to removal of said spacer.
  • the source/drain pocket region is formed by performing a tilt angle implantation process.
  • the source/drain extension region is formed by a first implantation step and the source/drain pocket region is formed by a second, tilt angle, implantation step.
  • the source/drain extension region and the source/drain pocket region may be formed by a single tilt angle implantation step, in which case, the implantation step is beneficially preceded by a pre-amorphisation implantation step.
  • the annealing process may, for example, comprise an ultra-rapid annealing process, such that the suicide layer is not degraded or caused to exhibit phase modification, or a conventional spike annealing process.
  • low temperature spacers may be provided on the sidewalls of the gate, to allow the formation of borderless contacts.
  • Figure 1 is a schematic cross-sectional illustration of the main process flow steps for fabricating a metal-oxide semiconductor integrated circuit device according to the prior art
  • Figure 2 is a schematic cross-sectional view of the main initial process flow steps for fabricating a metal-oxide semiconductor integrated circuit device according to an exemplary embodiment of the present invention
  • Figure 3 is a schematic cross-sectional illustration of the main subsequent process flow steps for the fabrication of a metal-oxide semiconductor integrated circuit device according to a first exemplary embodiment of the present invention
  • Figure 4 is a schematic cross-sectional illustration of the main subsequent process flow steps for the fabrication of a metal-oxide semiconductor integrated circuit device according to a second exemplary embodiment of the present invention.
  • a substrate 100 is provided in which the N well and P well have been implanted.
  • the substrate 100 is provided with a dielectric layer 102 on which is deposited a full-sheet layer 104 of poly-silicon according to a principle known to a person skilled in the art, as illustrated in Figure 2a.
  • Said dielectric layer includes, for example, an oxide (for example SiO 2 ), an oxy-nitride (for example SiO 2 +Si3N 4 ) or a high dielectric permittivity material (for example HfO 2 ).
  • the poly-silicon layer 104 is etched to form a gate 106, as illustrated in Figure 2b.
  • a spacer 108 is formed on the sidewall of the gate 106, for example, by forming a silicon nitride layer on the substrate and covering the gate 106, and then performing an anisotropic etching process on the silicon nitride layer.
  • a source/drain implantation is then performed on the substrate 100, through the dielectric layer 102 to form a heavily doped source/drain region 110 in the substrate 100 adjacent to the outer edge of the spacer 108 ( Figure 2d).
  • the implantation step is adapted to implant ions of a first type at a first predetermined energy corresponding to this type of ions so as to form a heavily doped region.
  • Arsenic Bo ions are implanted at an energy of around 10 keV. It will be appreciated by a person skilled in the art that, if necessary, a sacrificial layer can be added just before implantation. A sacrificial oxide etching step is performed to remove the dielectric layer 102 not covered by the gate 104 and the spacer 108 ( Figure 2e). Self-aligned suicide layer 112 is then formed on the exposed surfaces of the gate 106 and the source/drain region 110, as illustrated in Figure 2f of the drawings. The self-aligned suicide layer 112 may be formed by, for example, forming a metal layer (e.g.
  • Said implantation step is adapted to implant ions of the first type at a second predetermined energy corresponding to this type of ions so as to form a lightly doped region.
  • ions of the first type at a second predetermined energy corresponding to this type of ions so as to form a lightly doped region.
  • Bore B ions are implanted at an energy of around 1 keV.
  • a tilt angle implantation process is performed on the substrate 100 to form source/drain pockets 116 in the substrate 100 under the side of the gate 106, as illustrated in Figure 3c of the drawings.
  • Said tilt angle implantation step is adapted to implant ions of a second type at a third predetermined energy corresponding to this type of ions so as to form a heavily doped region.
  • Arsenic ions are implanted at an energy of around 50 keV. It will be apparent to a person skilled in the art that As ions can be used as ions of the first type and B ion can be used as ions of the second type, and that ions other than As and B ions can be used in the different implantation steps.
  • a direct surface annealing (DSA) process which is non-destructive in respect of the suicide 112, is performed to anneal and electrically activate substantially simultaneously the pockets 116, the source/drain region 110 and the source/drain extension region 114 ( Figure
  • a low temperature spacer 118 can be deposited ( Figure 3e) to allow for the formation of borderless contacts, in accordance with a conventional process.
  • the source/drain extensions 114 are specifically annealed and activated independently of (and although substantially simultaneously with) the source/drain region 110.
  • a pre-amorphisation process implantation PAI step is performed.
  • ions are implanted into the semiconductor substrate 100 to form relatively deep amorphous regions 120 in the substrate 100.
  • Si, Ge or Ar ions may be implanted to break lattice bonds and create a non-crystalline or amorphous silicon region 120 in the substrate 100, as shown in Figure 4b of the drawings.
  • An implantation process is then performed on the substrate 100 to form, as before, a source/drain extension region 114 in the substrate 100 at the location previously covered by the spacer 108, followed by a tilt angle implantation process performed on the substrate 100 to form, as before, source/drain pockets 116 in the substrate 100, the pockets 116 extending under the side of the gate 104, as illustrated in Figure 4c of the drawings.
  • An direct surface annealing (DSA) process which is non-destructive in respect of the suicide, is performed to anneal and electrically activate substantially simultaneously the pockets 116, the source/drain region 110 and the source/drain extension region 114 ( Figure 4d), as before.
  • a conventional spike annealing process may be performed to anneal and electrically activate substantially simultaneously the pockets 116, the source/drain region 110 and the source/drain extension region 114.
  • Said spike annealing step duration is, for example, lower than one second and is performed, for example, at a temperature equal to or higher than 1000°C.
  • a low temperature spacer 118 can be deposited ( Figure 4e) to allow for the formation of borderless contacts, in accordance with a conventional process.

Abstract

A method and apparatus for fabricating a metal oxide semiconductor integrated circuit device, the method comprising sequentially: (a) providing a gate (106) on a substrate (100); (b) providing a spacer (108) on a sidewall of said gate (106); (c) forming a source/drain region (110) in said substrate (100); (d) substantially completely removing said spacer (108); (e) forming a source/drain extension region (114) in said substrate (100); (f) forming a source drain pocket region (116) in said substrate (100), beneath said gate (106); and (g) performing an annealing process to substantially simultaneously electrically activate said source/drain region (110), said source/drain extension region (114) and said source/drain pocket region (116).

Description

Method and Apparatus for Fabricating Ultra-Shallow Junction Metal-Oxide Semiconductor Integrated Circuit Devices
FIELD OF THE INVENTION This invention relates to a method and apparatus for fabricating an ultra-shallow junction metal-oxide semiconductor integrated circuit device and, more particularly, to a method and apparatus for fabricating a metal-oxide semiconductor integrated circuit device having an ultra-shallow, low sheet-resistance source/drain junction and improved short channel performance.
BACKGROUND OF THE INVENTION The development of Very Large Scale Integration (VLSI) is evolving along the line of a large wafer size and a small line width. This trend of development enhances the function of integrated circuits and reduces the manufacturing cost. As the device dimensions are reduced with respect to the metal-oxide semiconductor transistors of integrated circuits, the channel length diminishes correspondingly to increase the operating speed of the transistor. As the dimensions of metal-oxide semiconductor (MOS) transistors are scaled down to 0.1 μm and below, in order to achieve continued improvements in integrated circuit density and performance, a significant number of new technological issues emerge. Among these is the need for new techniques for forming ultra-shallow junctions which provide adequately low sheet resistance. As device dimensions become miniaturised, an overlapping of the depletion layer of the source/drain region and the channel often occurs due to a reduction of the channel length. The shorter the channel length, the greater becomes the overlapping ratio of the source/drain region. As a consequence, the actual channel length is reduced and this phenomenon is known as the short channel effect. In an attempt to solve the above-mentioned problem, a lightly doped drain (LDD) is formed. However, when the line width is less than 0.25 microns, the depth of the LDD has to be further reduced. As a result, the resistance increases and the speed of the device decreases accordingly, which is obviously undesirable. Therefore, in order to avoid this problem, a source/drain extension region with a higher dopant concentration is formed to replace the lightly doped region. Referring to Figure la of the drawings, in a prior art metal-oxide semiconductor device fabrication process, a gate 10 is formed on a substrate 12 provided with a dielectric layer 11. Next, an ion implantation is performed on the substrate 10 to form the lightly doped drain (LDD) regions 14, as illustrated schematically in Figure lb of the drawings. A spacer 16 is then formed on the sidewall of the gate 10, as shown in Figure lc, and a source/drain implantation process is performed to form a source/drain region 18 in the substrate, as shown in Figure Id of the drawings. Finally, following the subjection of the silicon wafer to a thermal process (such as annealing) to repair the crystal structure and drive-in the dopants, suicide contacts 20 are formed on the source, drain and gate regions of the device, to create a structure as illustrated schematically in Figure le of the drawings. The prior art process described above includes at least two annealing steps, namely the spacer annealing deposition and the suicide annealing reaction and phase transformation. The further performance of the above-mentioned source/drain annealing for activation leads to over-diffusion of the extensions, more specifically, lateral diffusion of the source/drain extension region occurs accompanied by an increase in junction depth, which results in the devices suffering from short channel effects. In order to avoid this, it has been proposed to add an offset spacer before extension implantation. However, this complicates the process flow and decreases throughput. Even if one problem is solved thereby because of the increase in effective channel length, the extension junction is still undesirably deep which leads to huge drain induced barrier lowering effects and poor device manufacturability.
SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a method and apparatus for fabricating a metal-oxide semiconductor integrated circuit device in which a better doping profile and activation control than the one of prior art is attained for ultra-shallow source and drain extensions and for deep source and drain extensions. In accordance with the present invention, there is provided a method of fabricating a metal-oxide semiconductor integrated circuit device, the method comprising the steps of: a) providing a gate on a substrate; b) providing a spacer on a sidewall of said gate; c) forming a source/drain region in said substrate; d) substantially completely removing said spacer; e) forming a source/drain extension region in said substrate; f) forming a source drain pocket region in said substrate, beneath said gate; and g) performing an annealing process to electrically activate said source/drain region, said source/drain extension region and said source/drain pocket region. The present invention also extends to apparatus for fabricating a metal-oxide semiconductor integrated circuit device by the method defined above, the device comprising a gate on a substrate, the apparatus comprising: a) means for providing a spacer on a sidewall of said gate; b) means for forming a source/drain region in said substrate; c) means for substantially completely removing said spacer; d) means for forming a source/drain extension region in said substrate; e) means for forming a source drain pocket region in said substrate, beneath said gate; and f) means for performing an annealing process to electrically activate said source/drain region, said source/drain extension region and said source/drain pocket region. The present invention extends still further to a metal-oxide semiconductor integrated circuit device fabricated according to the method defined above. In a preferred embodiment of the invention, a suicide layer is formed on said gate and exposed portions of said source/drain regions, prior to removal of said spacer. Preferably, the source/drain pocket region is formed by performing a tilt angle implantation process. In one embodiment of the invention, the source/drain extension region is formed by a first implantation step and the source/drain pocket region is formed by a second, tilt angle, implantation step. In an alternative exemplary embodiment of the invention, the source/drain extension region and the source/drain pocket region may be formed by a single tilt angle implantation step, in which case, the implantation step is beneficially preceded by a pre-amorphisation implantation step. The annealing process may, for example, comprise an ultra-rapid annealing process, such that the suicide layer is not degraded or caused to exhibit phase modification, or a conventional spike annealing process. Following the annealing step, low temperature spacers may be provided on the sidewalls of the gate, to allow the formation of borderless contacts. These and other aspects of the invention will be apparent from and will be elucidated with reference to the embodiments described hereinafter.
BRIEF DESCRIPTION OF THE DRAWINGS The present invention will now be described in more detail, by way of example, with reference to the accompanying drawings, wherein: Figure 1 is a schematic cross-sectional illustration of the main process flow steps for fabricating a metal-oxide semiconductor integrated circuit device according to the prior art; - Figure 2 is a schematic cross-sectional view of the main initial process flow steps for fabricating a metal-oxide semiconductor integrated circuit device according to an exemplary embodiment of the present invention; Figure 3 is a schematic cross-sectional illustration of the main subsequent process flow steps for the fabrication of a metal-oxide semiconductor integrated circuit device according to a first exemplary embodiment of the present invention; and Figure 4 is a schematic cross-sectional illustration of the main subsequent process flow steps for the fabrication of a metal-oxide semiconductor integrated circuit device according to a second exemplary embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION It is an object of the present invention to provide a method and apparatus for fabricating a metal-oxide semiconductor integrated circuit device in which the diffusion of the source/drain extension region is limited to substantially that which is necessary for their electrical activation. We have now devised the improved arrangement.
Referring to Figure 2 of the drawings, a substrate 100 is provided in which the N well and P well have been implanted. The substrate 100 is provided with a dielectric layer 102 on which is deposited a full-sheet layer 104 of poly-silicon according to a principle known to a person skilled in the art, as illustrated in Figure 2a. Said dielectric layer includes, for example, an oxide (for example SiO2), an oxy-nitride (for example SiO2+Si3N4) or a high dielectric permittivity material (for example HfO2). Just after the deposition step, the poly-silicon layer 104 is etched to form a gate 106, as illustrated in Figure 2b. As illustrated in Figure 2c of the drawings, in the next step, a spacer 108 is formed on the sidewall of the gate 106, for example, by forming a silicon nitride layer on the substrate and covering the gate 106, and then performing an anisotropic etching process on the silicon nitride layer. A source/drain implantation is then performed on the substrate 100, through the dielectric layer 102 to form a heavily doped source/drain region 110 in the substrate 100 adjacent to the outer edge of the spacer 108 (Figure 2d). The implantation step is adapted to implant ions of a first type at a first predetermined energy corresponding to this type of ions so as to form a heavily doped region. For example, Arsenic Bo ions are implanted at an energy of around 10 keV. It will be appreciated by a person skilled in the art that, if necessary, a sacrificial layer can be added just before implantation. A sacrificial oxide etching step is performed to remove the dielectric layer 102 not covered by the gate 104 and the spacer 108 (Figure 2e). Self-aligned suicide layer 112 is then formed on the exposed surfaces of the gate 106 and the source/drain region 110, as illustrated in Figure 2f of the drawings. The self-aligned suicide layer 112 may be formed by, for example, forming a metal layer (e.g. Titanium) on the substrate 100 covering the gate 106, and then conducting a thermal treatment process to allow the gate 106 and the source/drain region 110 to react with the metal layer to form the self-aligned suicide layer 112. The excess unreacted metal layer is removed. At this stage, the remaining process can be accomplished by several different methods, and, in this regard, two exemplary embodiments of the present invention will now be described in more detail. Referring to Figure 3 of the drawings, in accordance with a first exemplary embodiment of the present invention, the spacers 108 used to control the source/drain implantation process and avoid the suicide bridging are completely removed (Figure 3a). An implantation process is then performed on the substrate 100 to form a source/drain extension region 114, i.e. a lightly doped region, in the substrate 100 at the location previously covered by the spacer 108, as illustrated in Figure 3b of the drawings. Said implantation step is adapted to implant ions of the first type at a second predetermined energy corresponding to this type of ions so as to form a lightly doped region. For example, Bore B ions are implanted at an energy of around 1 keV. Next, a tilt angle implantation process is performed on the substrate 100 to form source/drain pockets 116 in the substrate 100 under the side of the gate 106, as illustrated in Figure 3c of the drawings. Said tilt angle implantation step is adapted to implant ions of a second type at a third predetermined energy corresponding to this type of ions so as to form a heavily doped region. For example, Arsenic ions are implanted at an energy of around 50 keV. It will be apparent to a person skilled in the art that As ions can be used as ions of the first type and B ion can be used as ions of the second type, and that ions other than As and B ions can be used in the different implantation steps. A direct surface annealing (DSA) process, which is non-destructive in respect of the suicide 112, is performed to anneal and electrically activate substantially simultaneously the pockets 116, the source/drain region 110 and the source/drain extension region 114 (Figure
3d). This annealing process is so rapid that the suicide should not be degraded and should not suffer from phase modification. Finally, if necessary, a low temperature spacer 118 can be deposited (Figure 3e) to allow for the formation of borderless contacts, in accordance with a conventional process. With this process sequence, the source/drain extensions 114 are specifically annealed and activated independently of (and although substantially simultaneously with) the source/drain region 110.
Referring to Figure 4 of the drawings, in accordance with a second exemplary embodiment of the present invention, the spacers 108 used to control the source/drain implantation process and avoid the suicide bridging are completely removed (Figure 4a). Next, a pre-amorphisation process implantation PAI step is performed. In this step, ions are implanted into the semiconductor substrate 100 to form relatively deep amorphous regions 120 in the substrate 100. For example, Si, Ge or Ar ions may be implanted to break lattice bonds and create a non-crystalline or amorphous silicon region 120 in the substrate 100, as shown in Figure 4b of the drawings. An implantation process is then performed on the substrate 100 to form, as before, a source/drain extension region 114 in the substrate 100 at the location previously covered by the spacer 108, followed by a tilt angle implantation process performed on the substrate 100 to form, as before, source/drain pockets 116 in the substrate 100, the pockets 116 extending under the side of the gate 104, as illustrated in Figure 4c of the drawings. An direct surface annealing (DSA) process, which is non-destructive in respect of the suicide, is performed to anneal and electrically activate substantially simultaneously the pockets 116, the source/drain region 110 and the source/drain extension region 114 (Figure 4d), as before. Thanks to this DSA process the defects in the amorphous regions 120 are repaired and said amorphous regions 120 disappear. Alternatively, a conventional spike annealing process may be performed to anneal and electrically activate substantially simultaneously the pockets 116, the source/drain region 110 and the source/drain extension region 114. Said spike annealing step duration is, for example, lower than one second and is performed, for example, at a temperature equal to or higher than 1000°C. Finally, if necessary, a low temperature spacer 118 can be deposited (Figure 4e) to allow for the formation of borderless contacts, in accordance with a conventional process.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be capable of designing many alternative embodiments without departing from the scope of the invention as defined by the appended claims. In the claims, any reference signs placed in parentheses shall not be construed as limiting the claims. The word "comprising" and "comprises", and the like, does not exclude the presence of elements or steps other than those listed in any claim or the specification as a whole. The singular reference of an element does not exclude the plural reference of such elements and vice-versa. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A method of fabricating a metal-oxide semiconductor integrated circuit device, the method comprising the steps of: (a) providing a gate (106) on a substrate (100);
(b) providing a spacer (108) on a sidewall of said gate (106);
(c) forming a source/drain region (110) in said substrate (100);
(d) substantially completely removing said spacer (108);
(e) forming a source/drain extension region (114) in said substrate (100) (f) forming a source drain pocket region (116) in said substrate (100), beneath said gate (106); and
(g) performing an annealing process to electrically activate said source/drain region (110), said source/drain extension region (114) and said source/drain pocket region (116).
2. A method according to claim 1, wherein a suicide layer (112) is formed on said gate (106) and exposed portions of said source/drain regions (110), prior to removal of said spacer (108).
3. A method according to any one of claims 1 to 2, wherein the source/drain extension region (1 14) is formed by a first implantation step.
4. A method according to any one of claims 1 to 2, wherein the source/drain pocket region (116) is formed by performing a second tilt angle implantation process.
5. A method according to claim 3, wherein the first implantation step is preceded by a pre-amorphisation implantation step.
6. A method according to any one of claims 1 to 5, wherein the annealing process comprises a direct surface annealing process, or a spike annealing process.
7. A method according to any one of claims 1 to 6, wherein following the annealing step, low temperature spacers (128) are provided on the sidewalls of the gate (106), to allow the formation of borderless contacts.
8. Apparatus for fabricating a metal oxide semiconductor integrated circuit device by the method according to any one of claims 1 to 7, the device comprising a gate (106) on a substrate (100) the apparatus comprising:
(a) means for providing a spacer (108) on a sidewall of said gate (106); (b) means for forming a source/drain region (110) in said substrate (100);
(c) means for substantially completely removing said spacer (108);
(d) means for forming a source/drain extension region (114) in said substrate (100);
(e) means for forming a source drain pocket region (116) in said substrate (100), beneath said gate (106); and (f) means for performing an annealing process to electrically activate said source/drain region (110), said source/drain extension region (114) and said source/drain pocket region (116).
9. A metal oxide semiconductor integrated circuit device fabricated by the method according to any one of claims 1 to 7.
10. A metal oxide semiconductor integrated circuit device fabricated by the method according to any one of claims 1 to 7, comprising: a substrate (100); - a dielectric layer (102) provided on said substrate (100); a gate (106) provided on said dielectric layer (102); a heavily doped source/drain region (110) formed in said substrate (100) including doping elements of a first type; a lightly doped source/drain extension region (114) formed in said substrate (100) including doping elements of the first type; a heavily doped source drain pocket region (116) formed in said substrate (100), beneath said gate (106), including doping elements of a second type.
PCT/IB2004/003991 2003-12-10 2004-12-03 Method and apparatus for fabricating ultra-shallow junction metal-oxide semiconductor integrated circuit devices. WO2005057662A2 (en)

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