WO2005064586A1

WO2005064586A1 - Display device drive device, display device, and drive device or display device check method

Info

Publication number: WO2005064586A1
Application number: PCT/JP2003/016739
Authority: WO
Inventors: Yoshito Tanaka; Mitsunori Katsu
Original assignee: Test Research Laboratories Inc.
Priority date: 2003-12-25
Filing date: 2003-12-25
Publication date: 2005-07-14
Also published as: EP1699039A1; JPWO2005064586A1; CN1781136A; AU2003296116A1; CA2527676A1

Abstract

A display device drive device includes a signal processing section (20) for correcting an input digital image signal and outputting a digital corrected signal, an analog signal output section (30) for outputting an analog image signal to a plurality of image output terminals (1), a signal switching selection (40) for successively selecting an analog image signal from the analog signal output section (30), and a delta/sigma modulator (9) for delta/sigma-modulating the analog image signal selected by the signal switching section (40) and feedback-inputs the created 1-bit digital modulated signal to the signal processing section (20). The signal processing section (20) successively outputs initial output data Vinit0 to Vinitm to the analog signal output section (30), receives a modulated signal for the initial output data Vinit0 to Vinitm from the delta/sigma modulator (9) so as to calculate correction data. Thus, even if irregularities are caused in the non-linear electric characteristic between output terminals in the display drive LSI of ultra-multi-pin output, it is possible to sufficiently correct them with a high accuracy.

Description

Display device drive device, display device, drive device or display device inspection method

Technical field

The present invention relates to a driving device having many analog output terminals such as an LSI for driving a display device, a display device using the driving device, and a driving device.

The present invention relates to a method of inspecting a display or a display device.

1 book

Background art

In a display device such as a liquid crystal display device, an organic EL display device, a plasma display, and a surface electric field display, image data is processed by an electronic circuit such as a drive circuit, and a plurality of output terminals of the drive circuit are connected to display elements. Is output. Since the drive transistors provided corresponding to the respective output terminals of the drive circuit have considerable variations in the electrical characteristics, the signal values output from the respective output terminals vary.

For example, variations in driving transistors appear as mismatches in transistor characteristics and appear as offset errors and gain errors. In addition, system errors in circuit characteristics appear due to fluctuations in the manufacturing process. Various techniques have been proposed to correct such variations (see, for example, Patent Documents 1 to 3).

Patent Document 1: Japanese Unexamined Patent Application Publication No. 2000-30074

Patent Document 2: Japanese Patent Application Laid-Open No. 2002-3666611

Patent Literature 4: Japanese Patent No. 3199878 The technology described in Patent Literature 1 relates to an electronic circuit that converts a digital input signal into an analog output signal and outputs the analog output signal to a display element side. This electronic times The circuit includes a latch circuit for storing an input signal and a memory circuit for storing offset correction data, corresponding to the plurality of output terminals.

It has an adder circuit that adds offset correction 7—evening to the digital signal input signal, and a Ό / A number converter that converts the output signal from the adder circuit into an analog signal.

In Patent Document 1, a correction circuit for measuring the offset amount of each DA converter and converting the offset amount into offset correction data is separately provided. The correction circuit is a comparator that compares the analog output signal of the D / A component corresponding to each output terminal with the D / A converter and the analog output signal of the correction circuit of the correction circuit, and the output of the comparator. It is configured to have a digital circuit that generates a digital offset correction in the evening. Thus, each memory circuit has a corresponding output m

Since the difference between the output signal from the D / A connector and the output signal from the reference D / A amplifier is stored as offset correction data, the correction is made by: r The digital signal has the same level at each output terminal.

Patent Literature 2 describes a circuit that corrects the dispersion by using a comparison table provided for a plurality of analog circuits. The technology described in Patent Document 2 relates to a liquid crystal display device, and a video signal control circuit in the display control device includes an AZD converter that converts an analog input signal to the display control device into a digital signal. And a signal processing circuit for processing the digital signal

A reference table for storing correction data; and a D / A converter for converting the digital signal corrected by the reference table into an analog signal. The reference table and D / A converter are provided for each phase. With such a configuration, the variation can be corrected for each phase using the look-up table. Patent Document 3 discloses that a signal output from an inspection terminal is used to drive a driving circuit. A technique for correcting an input signal has been disclosed. According to this technique, display image signals of various test patterns are input to the drive circuit in advance, and output signals corresponding to the display image signals are sequentially selected. Then, the sequentially selected signals are output from the inspection terminal to the AZD converter, and the correction data obtained based on the digital signals output from the AZD converter are stored in the memory element. The input signal to the drive circuit can be corrected by this correction data.

By the way, in general, variations in the electrical characteristics of transistors

It is strongly influenced by variations in the number of impurities implanted in the process, variations in transistor size due to non-uniform etching, and channel length modulation effects caused by reducing the size of the transistor. Based on 0, the effect of the change in the channel length L on the transient characteristics will be described. In Yo shown in FIG. 1 9 (A), the channel length L of the transistor is sufficiently large, drain - source - drain current I _D irrespective of the size of the scan voltage V _DS is substantially constant (solid line ). However, as the channel length L of the transistor decreases, the effect of the channel length modulation effect appears, and the drain current _ID increases in proportion to the magnitude of the drain-source voltage V _DS (dashed line). ). The effect of this

— — Increases as source-to-source voltage V _GS increases.

FIG. 19 (B) shows this characteristic in the relationship between the gate-source voltage V _GS and the drain current _ID . In other words, when the channel length L is large, if the gate-source voltage V _GS is constant, the drain current _ID is almost constant regardless of the change in the drain-source voltage V _DS . On the other hand, when the channel length L decreases, the drain current _ID greatly changes due to the change in the drain-source voltage V _Ds . For this reason, in an operational amplifier using a transistor having a small channel length L, a non-linear effect occurs. For example, in a voltage follower circuit as shown in Fig. 20 (A) Causes nonlinearity as shown in Fig. 20 (B) with respect to the ideal value. As shown in Fig. 20 (B), when the channel length L is large, the relationship between the input voltage and the output voltage is linear so that it substantially matches the ideal value, but when the channel length L is small, the relationship is nonlinear. And deviate from the ideal value. The channel length modulation effect that causes nonlinearity such as

It can be reduced by increasing L. Also, since the variation in the number of impurities introduced into the transistor is affected by statistical fluctuations, it is possible to reduce the area by increasing the area of the transistor.

. Furthermore, the variation in etching fc can be reduced by increasing the circumference of the transistor, thus reducing the electrical characteristics of the transistor.

,

In order to reduce the variability, it is effective to increase the size of the transcript.

For this reason, semiconductor circuits that typically output image signals via multiple pins (terminals), such as those typically used in display drive LSIs, use large-size transistors to reduce the dispersion of output values. In particular, when the channel length L is reduced, the characteristics of the range characteristic are lost due to the effect of the channel tuning effect and the like, so a large-sized transistor has been used in a high-precision LCD drive circuit. For example, even if the driving circuit is a 0.18 m process, a large driving transistor having a channel length L of 4 m and a channel width W of about 100 m is used. D / A converters to suppress characteristic variations

,

In addition, a large tranche with a channel length L of about 3 m is usually used.

In addition, when a voltage control circuit is formed in a drive circuit by a pump instead of a source control circuit, a large-size transistor control circuit is used to suppress variation in characteristics. And D / A conversion using When a drive circuit is formed using an analog signal switch (multiplexer) and a grayscale voltage source, the channel length L is increased in order to increase the accuracy of the grayscale voltage source. In order to equalize and lower the voltage drop (impedance), the multiplexer must use Ik so that the same number of transistor switches are used from the power supply. However, it is inevitable that the voltage drop is proportional to the distance from the source and that the voltage drop mismatches due to variations in the range. Ultra-high-pin count LSIs With the miniaturization of LSI manufacturing processes progressing L

It is required to reduce the size of the transistor used in SI. Simultaneously, the accuracy of the analog signal is also required. However, when the size of the transistor is reduced, the characteristic of the transistor characteristic is reduced as described in (1) above. Patent Literature 1 discloses that the degree of nonlinearity of a circuit due to deterioration is deteriorated, and the degree of linear correction using an offset constant, a gain constant, and the like cannot be ensured.

As described in 1, only the offset variance * is used, and the estimated linear correction uses a transistor with a small size.¾ It is possible to sufficiently correct the nonlinear characteristic deviation that occurs at the mouth. There is a problem that can not be.

Further, in the correction technique described in Patent Document 2, correction data is set while observing and evaluating the display screen, so that it is necessary to rely on human eyes or a large-scale device such as an imaging device. There was an inconvenience.

Further, in the technique according to Patent Document 3, the analog signal output from the driving LsI is converted into a digital signal by AZD conversion and input to a correction circuit. However, simply converting an analog value to a digital value by A / D conversion like this requires an extremely large number of signal lines, and causes a problem that the circuit size becomes large. Since the D converter and correction circuit are external to the drive LSI,

Noise components easily enter the analog signal before being input to the ZD converter And it is difficult to perform high-precision correction. Disclosure of the invention

The present invention has been made to solve such a problem. Even when a small-sized transistor is used in a multi-pin output display driving LSI, the non-linear electrical characteristics generated between the output terminals are reduced. The purpose is to make it possible to sufficiently correct the variation in.

It is another object of the present invention to accurately correct non-linear variations in non-linear electrical characteristics between output terminals in a display drive LSI with a super multi-pin output.

Another object of the present invention is to minimize the circuit configuration for correcting the non-linear variation in the electrical characteristics generated between the output terminals in the display drive LSI of a super multi-pin output.

In order to solve the above-mentioned problem, a driving device for a display device according to the present invention is configured to input digital signals corresponding to a plurality of output terminals and convert each digital signal into correction data corresponding to the signal size. A signal processing unit that outputs a digital correction signal corrected by the analog signal generator, and an analog signal output unit that generates an analog signal based on the digital correction signal output from the signal processing unit and outputs the analog signal to a plurality of output terminals. And a signal switching unit connected to a plurality of output terminals for sequentially selecting an analog signal from the analog signal output unit; and a delta-sigma modulation of the analog signal selected by the signal switching unit to obtain a delta-sigma signal. It has a delta-sigma modulator that outputs a 1-bit sigma-modulated digital signal to the signal processor.The signal processor outputs an analog signal with multiple levels of reference digital signals. To the demodulation unit, a 1-bit digital modulation signal corresponding to the reference digital signal is input from the Dell Shimadama modulation unit and demodulated, and correction data is generated based on the demodulated signal and the quasi-digital signal. Calculate And a function of performing correction based on the correction data.

As described above, according to the present invention, the correction data is calculated based on the multi-stage reference digital signal and the multi-stage digital signal obtained by digitizing the analog signal generated from the multi-stage reference digital signal. Unlike a simple linear correction using a constant, it is possible to calculate a correction data that incorporates nonlinear output characteristics. Therefore, even if a small-sized transistor is used in a display drive LSI with an ultra-high pin output, the variation in nonlinear electrical characteristics caused by this can be sufficiently corrected according to the magnitude of the input digital signal. it can.

Further, in the present invention, by using a delta-sigma modulation unit, it is possible to measure an output signal with extremely high accuracy while suppressing quantization noise, and it is possible to generate accurate | ¾ correction data. Also, since the output from the delta-sigma transformation unit is a 1-bit digital modulation signal from one output terminal, the number of wirings can be reduced and the size can be reduced.

Also, the signal processing unit has a plurality of levels of size.

An approximation curve may be calculated based on the change of the PM-i signal with respect to the quasi-digital signal, and the correction data may be calculated based on the approximation curve. The resolution for the signal magnitude is high <and accurate correction: Evening can be obtained, so that more accurate correction can be performed.

Further, the signal processing unit may be configured to calculate correction data using an average value of a plurality of demodulated signals generated by outputting a plurality of reference digital signals having a plurality of levels of magnitude. . With this configuration, it is possible to reduce random noise included in an output signal measured when a reference digital signal is input, and it is possible to calculate correction data with a smaller error. . Further, the correction data may be generated for each of the plurality of output terminals. Normally, there is a variation in the electrical characteristics between the circuits corresponding to the respective output terminals. Therefore, it is possible to perform more accurate correction by calculating the correction data corresponding to the respective output terminals.

Further, the delta-sigma modulator may be configured so that the clock speed can be changed. With this configuration, the clock speed can be changed according to the required correction accuracy. For example, the SZN ratio of a signal can be improved by increasing the clock speed, so that the analog output signal from the output terminal is simply fed back to the correction signal processing circuit via the A / D converter. As compared with the case where the correction data is generated, the accuracy of the generated correction data has a higher degree of freedom, and the correction data having appropriate accuracy can be calculated.

Also, a delta-sigma modulation output terminal capable of outputting a 15-bit 1-bit digital modulation signal of delta-sigma modulation sound may be provided. With this configuration, an analog signal to be output from the output terminal can be externally detected through the relay sigma modulation output terminal, and the drive device can be inspected or evaluated. Since the signal output from the delta-sigma modulation output terminal is a 1-bit digital modulation signal, the degree to which the accuracy of the signal is reduced by noise is reduced as compared with the case where the analog signal is output. Also, since the output of one delta-sigma modulation section can be completed by one wiring, even if the number of output terminals is very large, the output signal can be connected by connecting to one Dell sigma-modulation output terminal. It can inspect and evaluate the characteristics of the device, and does not require a complicated and expensive test system corresponding to an extremely large number of pins. In addition, the inspection apparatus that receives the one-bit digital modulation signal can be a simple digital tester that performs digital signal processing, and does not require an analog tester.

Also, the drive device configured as above is formed on the same semiconductor IC. Is also good. According to this structure, the signal processing unit for calculating and storing the correction data is incorporated in the drive device, so that the correction data can be calculated using a high-precision image in which noise hardly enters. The accuracy of correction can be improved. In other words, the output signal from the output terminal is

Since it is configured to pass only inside the on-chip drive device and not to pass through the external wiring, it is difficult for noise to enter the output signal. In addition, the inspection and evaluation of the driving device can be performed by including the signal processing section having the correction function, so that it is not necessary to separately inspect the circuit having the correction function.

Therefore, the manufacturing cost can be reduced as a whole.

In addition, it is preferable that the display device is configured using the above-described driving device. With such a configuration, the display is performed by the output signal corrected by the high-precision correction data as described above. Driving is performed, and the displayed image of the shell can be improved. In addition, high-precision inspection and evaluation can be performed with the drive unit incorporated. Further, since the correction is performed in a state where the driving device is assembled to the display device, it is possible to perform the correction including the manufacturing variation, the environmental variation, and the aging variation of the entire display device.

As described above, according to the present invention, by using a transistor having a small size, display drive of an ultra-high pin output is performed and even if non-linear electric characteristics vary between output terminals in the SI. , Nonlinear errors can be corrected sufficiently and with good accuracy, image outputs with small variations can be obtained, and digital signals from a small number of output terminals can be used for highly accurate inspection of electrical characteristics, etc. In addition, a circuit configuration for the evaluation can be made as small as possible. Brief Description of Drawings

FIG. 1 is a block diagram showing the configuration of the liquid crystal display device according to the present embodiment. The

FIG. 2 is a diagram illustrating a configuration of a terminal included in the drive device of the present embodiment. FIG. 3 is a block diagram illustrating a circuit configuration example of the driving device according to the present embodiment.

FIG. 4 is a diagram illustrating a relationship between an input signal and an output signal to the delta-sigma modulator of the present embodiment.

FIG. 5 is a diagram showing a configuration example of initial output data set by the correction signal processing circuit when generating correction data.

FIG. 6 is a diagram illustrating a configuration example of measurement data measured by the delta-sigma modulator when the correction data is generated.

FIG. 7 is a diagram illustrating a configuration example of the correction data stored in the correction data storage circuit.

FIG. 8 is a diagram illustrating another configuration example of the correction data stored in the correction data storage circuit.

FIG. 9 is a diagram illustrating a configuration example of a correction signal processing circuit and a decimation filter incorporated in a simple tester according to the present embodiment.

FIG. 10 is a diagram illustrating an example of a result obtained by performing a decimation process and an averaging process on a 1-bit digital modulation signal output from a delta-sigma modulator using a correction signal processing circuit.

FIG. 11 is a diagram illustrating a configuration example of the approximate curve coefficient data stored in the correction data storage circuit.

FIG. 12 is a diagram showing a configuration example of a test system in the case of performing inspection / evaluation of a drive having the drive device of the present embodiment.

FIG. 13 is a diagram illustrating a configuration example of a test system in a case where inspection and evaluation of a liquid crystal display device in which the driving device of the present embodiment is mounted is performed.

FIG. 14 is a block diagram showing another example of the circuit configuration of the driving device according to the present embodiment. Fig.

FIG. 15 is a block diagram showing another example of the circuit configuration of the drive device according to the present embodiment.

FIG. 16 is a diagram illustrating a configuration example of a measurement time measured by the Dell Sigma e week 3δ when the correction data is generated in the driving device using the gradation voltage source.

FIG. 17 is a diagram illustrating a configuration example of correction data for global correction stored in a correction data storage circuit in a driving device using a floor voltage source. FIG. 18 is a diagram showing a configuration of a conventional test system.

FIG. 19 is a diagram for explaining the effect of the change in the channel length on the transistor characteristics.

FIG. 20 is a diagram for explaining the effect of the change in the channel length on the transistor characteristics. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of a liquid crystal display device S according to the present embodiment. As shown in FIG. 1, the liquid crystal display device S of the present embodiment includes a liquid crystal panel (liquid crystal display element).

) 50 and a controller that controls the display of images on the liquid crystal panel 50.

0.

The liquid crystal panel 50 is composed of a display section 51 in which pixel sections are provided in a matrix.

The driving device 52, 53, which includes a driving device (source driver LSI) 52 for the running signal line and a driving device (source driver LSI) 53 for the image signal line, Display unit 5 Display unit 5 arranged on the same board as 1

In FIG. 1, a plurality of scanning signal lines 54 and a plurality of image signal lines 55 orthogonal to the scanning signal lines 54 are provided. Is provided. The ends of the scanning signal line 54 and the image signal line 55 are connected to the output terminals of the driving devices 52 and 53, respectively.

The controller 60 receives a display signal (image signal), a clock signal, a timing signal, a horizontal synchronizing signal, a vertical synchronizing signal, and the like from an external device such as a personal computer, and transmits a control signal to the driving device 5. The display signal is output to the driving device 53 in addition to the output to the driving device 53. The driving devices 52 and 53 operate based on these signals, and each pixel portion (panel pixel group) of the liquid crystal panel 50 from the driving device 53 according to the driving period of the scanning electrode by the driving device 52. To supply an analog image signal.

FIG. 2 is an explanatory diagram of terminals provided in the driving device 53. As shown in FIG. 2, the driving device 53 includes a plurality of image output terminals 1 (Ι—, Ι—η) for supplying an analog image signal to an external panel pixel group, and an analog image signal. Drives a 1-bit digital signal generated by Delaware sigma modulation.

丄

And a delta-sigma modulation output m (inspection terminal) 2 for outputting to the outside of the device.

FIG. 3 is a block diagram showing an example of a circuit configuration of the driving device 53. As shown in FIG. 3, the driving device 53 includes an input latch circuit 8, a Dell Sigma modulator 9, a signal processing unit 20, an analog signal output unit 30 and a signal switching unit 4.

0. The driving device 53 having such a configuration is

It is packaged as a one-chip IC.

The input latch circuit 8 inputs a digital image signal and a clock signal displayed on the liquid crystal panel 50. The signal processing unit 20 performs a correction process on the digital image signal input from the input latch circuit 8. The signal processing unit 20 includes a correction data storage circuit 10 that stores correction data, and a correction signal processing circuit 1 that corrects a digital image signal supplied from the input latch circuit 8 with the correction data and outputs a digital correction signal. Consists of 1 and The

The analog signal output unit 30 receives the digital correction signal generated by the signal processing unit 20, converts the digital correction signal into an analog signal, and outputs the analog signal to the image output terminal 1. The analog signal output part 3 0, the correction signal processing circuit 1 1 digital correction signals output from the plurality of image output terminals 1 -, a latch circuit 6 that stores in correspondence with ~ 1 _ _[pi, shift register circuit 7 and a plurality of DZA converters 5 (

5-, ~ 5. „) and a plurality of drive transistors 4 for driving the data electrodes of the liquid crystal panel element by the A-converted analog image signal.

). Note that a voltage follower circuit may be used instead of the driving transistor 4.

The correction data stored in the above-described correction data storage circuit 10 is a driving device.

53 Variation in the electrical characteristics of each transistor (such as drive transistors 4 to 4 and D / A converters 5 to 5_ „transistors) built in, and the display

5 Driving device for correcting variations in the electrical characteristics of 1

The correction data used when performing correction and inspection of 3 itself is data for correcting an error due to variation in electrical characteristics of each transistor in the drive circuit 53. On the other hand, the correction data used when performing correction and inspection while the driving device 53 is mounted on the liquid crystal display device S includes, in addition to the variation in the electrical characteristics of each h range in the driving device 53, the display unit TF in 5 1

This data is used to correct errors due to variations in the electrical characteristics of T-transistors and capacitors. Such correction data is supplied to the correction signal processing circuit 11 comprising a correction amount or the like to be corrected for the digital image signal input to the input latch circuit 8, the digital signal supplied from the input latch circuit 8. The correction amount data corresponding to the magnitude of the evening image signal (corresponding to the digitization of the voltage value of the image signal) is read from the correction data storage circuit 10. Then, a digital correction signal is generated by subtracting the correction amount from the digital image signal.

A signal switching unit 40 is connected between the analog signal output unit 30 and the image output terminal 1. The signal switching section 40 is composed of an analog switch 3 (33- _n ) composed of a plurality of transistors and the like arranged corresponding to each of the image output terminals 1-! 1- „. The analog switches 3 —, 3 „operate sequentially in synchronization with the operation of storing the digital correction signal in the latch circuit 6, and the analog signal output unit 30 outputs the image output terminals 1 —, ιι. The analog image signals (the potentials of the image output terminals 1 to • 1-„) output to are sequentially selected and output to the delta-sigma modulator 9.

The delta-sigma modulator 9 includes an integrator, a comparator, a 1-bit DZA converter 5S, and the like. Then, the analog image signals sequentially supplied from the signal switching unit 40 are delta-sigma modulated at a predetermined clock speed, and the obtained analog image signals are obtained.

A 1-bit digital modulation signal is output from one output terminal to the signal processing unit 20 and the delta-sigma modulation output terminal 2.

The clock interval of the delta-sigma modulator 9 is sufficiently smaller than the Nyquist interval, and the signal bandwidth is much wider than that of a normal A / D converter. In addition, the Dell Sigma modulator 9 of the present embodiment can control the clock speed from a high speed to a low speed (however, it is set to be sufficiently larger than the Nyquist interval) by inputting a control signal from the external control terminal 12. It is configured so that it can be changed. Note that an arbitrary value set in advance according to the accuracy is used as the click speed of the Dell Sigma modulator 9 during the normal operation of the driving device 53.

FIG. 4 is a diagram showing a relationship between an input signal to the Dell Sigma modulator 9 and an output signal. In FIG. 4 (A), the input signal is an analog voltage that changes substantially linearly with time. This input signal is Is large and the variation in the electrical characteristics existing in the driving device 53 and the display unit 51 is small, or the variation in the electrical characteristics existing in the driving device 53 and the display unit 51 is sufficiently corrected. In this case, the signal input to the delta-sigma modulator 9 is shown. On the other hand, the input signal shown in Fig. 4 (B) is smaller than the drive unit 53

Fig. 1 shows a case where the electrical characteristics fluctuate and this has nonlinear characteristics.

The 1-bit digital signal output from the delta-sigma modulator 9 differs depending on whether an ideal signal without distortion is input to the delta-sigma modulator 9 and a signal with nonlinear distortion. The modulated signal will be completely different. That is, the delta-sigma modulator 9 can obtain a 1-bit digital modulation signal corresponding to the nonlinear distortion. Accordingly, the analog image signals output from the plurality of image output terminals 1-, 1- „are delta-sigma-modulated by the delta-sigma modulator 9, and the obtained 1-bit digital modulation signal is processed by the signal processing unit 20. , Which can generate correction data corresponding to the output value of each image output terminal l_, l- _n as described later. The drive device 53 and the display unit 51 can be inspected and evaluated by taking them out from the output terminals 2.

The drive unit 53 controls the data on the dispersion and abnormalities of the electrical characteristics of the drive unit 53g and the drive transistor 4 and the D / A converter 5, etc. (if they exceed the correctable range). In other words, the output of the correction signal processing circuit 11 is input to the latch circuit 6, but the latch circuit 6 is also connected to the y-evening bus of the controller 60. It has been done. The controller 60 is capable of measuring the voltage value of the image output terminal 1 by using the data supplied from the input / output circuit 6 of the image output terminal. If the display unit 51 is connected to the child 1, the controller 60 can also measure variations and abnormalities in the electrical characteristics of the display unit 51.

Next, the overall operation of the driving device 53 according to the present embodiment configured as described above will be described. First, the digital image signal and the clock signal supplied from the controller 60 are input to the input latch circuit 8 and stored. Then, the digital image signal stored in the input latch circuit 8 is transferred to the correction signal processing circuit 11 in synchronization with the clock signal.

In the correction signal processing circuit 11, the correction of the digital image signal is performed in accordance with the correction data stored in the correction data storage circuit 10 (the calculation method thereof will be described later) in correspondence with each image output terminal 11- _n. A digital correction signal is generated. The shift register circuit 7 sequentially outputs pulses to the latch circuit 6 based on a clock signal and a shift start signal (not shown). The digital correction signal is sequentially stored in the latch circuit 6 in accordance with the pulse output, and distributed to each image output terminal l ^ l.

The digital correction signal output from the latch circuit 6, DZA varying exchanger [delta] -, is an analog image signal through a [delta] driving transistor 4 4 _ _eta, an image output terminal 1, the display unit 5 from 1- _eta 1 is output to each pixel section. During normal operation, the delta-sigma modulator 9 is not operating, and the analog switches 33 _{η of} the signal switching unit 40 are all in a non-selected state.

On the other hand, when the correction data is generated and when the driving device 53 and the display unit 51 are inspected and evaluated, the analog image signal output to the image output terminal 11 is supplied to the analog switch of the signal switching unit 40. 3 „順次順次選択選択選択出力出力出力デルデルデルではではではアナログではではではではではアナログアナログではアナログアナログアナログアナログではアナログ. The 1-bit digital modulation signal is output to the signal processing unit 20 and the delta-sigma modulation output terminal 2. Next, a method of generating correction data will be described. When the power is turned on, the correction data is not stored in the correction data storage circuit 10 at all. The correction signal processing circuit 11 sets certain initial output data V _init (V _init0 to V _inilB ) as shown in FIG. 5 in the initialization process at power-on.

Figure 5 shows the initial output data V _init . FIG. 6 is a diagram illustrating a configuration example of ~ V _inilm . As shown in FIG. 5, the initial output data V _init as a reference digital signal. VV _initm is set within the range of the magnitude (voltage value) of the digital image signal input to the driving device ₅₃ . In the initial output data V _{innQ to} V _initn , values of a plurality of stages are set for each appropriate size. Note that the initial output data _{Vinn ()} to V may be stored in the correction data storage circuit 10 in advance. Also, the initial output data V _init . The number and interval of values of V _initffl may be arbitrarily set from an external control terminal (not shown) according to the required accuracy.

Next, the correction signal processing circuit 11 sequentially outputs the initial output data V _inilQ to V _initra set as the reference digital signal to the analog signal output section 30. At this time, the reference digital signal is converted into an analog signal in the analog signal output unit 30 and is output from each of the drive transistors 4_, to 4- _n to each of the image output terminals Ι-, Ι. Each driving transistor 4 -, - 4 - analog signal output from _η are selected sequentially Ri by the signal switching section 4 0, is input to the delta sigma modulator 9 is a delta-sigma modulation. Then, the generated 1-bit digital modulation signal is input to the correction signal processing circuit 11.

The correction signal processing circuit 11 is provided with a decimation filter, and performs a decimation process on the input 1-bit digital modulation signal, thereby forming a digital signal of a predetermined number of bits (output of the image output terminal 1). (Corresponds to the digitized voltage). By performing the decimation, the quantization error can be removed and a very high precision digital power A pressure value can be obtained. This decimation filter is composed of, for example, an FIR filter as shown in FIG. The configuration for performing the decimation is not limited to this, and may be a DSP (Digital Signal Processor) or another configuration.

As described above, the correction signal processing circuit 11 receives the 1- _bit digital modulation signal from the delta-sigma modulator 9 and demodulates the signal, thereby _{obtaining the} initial output _data . ~ V _Inilm the image output terminal corresponding to each value of the 1 -, ~ 1 - output voltage values D of _{_{_{n (D 1 () ~D nm}}} ) is measured.

Figure 6 is a diagram showing a configuration example of the measurement data _{_{D (D 10 ~ D nm)}} . As shown in FIG. „D„ _m is the initial output data V _inil from the correction signal processing circuit _{11. When 〜V inilm} is sequentially output to the analog signal output unit 30, each image output terminal _1-1 to 1- This is the digital voltage value measured corresponding to „. For example, initial output data V _inil . The digital voltage value D ₁ is measured corresponding to each of the image output terminals 1 ~ 1 _ _n Ri by the delta-sigma modulator 9 when output to the analog signal output section 3 0 ₍₎ ~ D _n. The digital voltage value measured by the delta-sigma modulator 9 corresponding to each of the image output terminals 1-, to 1 _n when the initial output data V _{ini D1} is output to the analog signal output unit 30 is D _lm. ~ D „ _m .

Note that the initial output data V _inilQ to V _iniln are output from the correction signal processing circuit 11 to the analog signal output section 30 a plurality of times, and the delta-sigma modulator 9 outputs the data to each of the image output terminals _1-1 to 1- _n . Average values of the correspondingly measured digital voltage values may be used as the measurement data D1 ₍₎ to D „.

, Measurement data D,. Regarding the initial output data V _inil . Since the voltage value of the image output terminal 1 is measured a plurality of times by outputting a plurality of times, the average value is measured data D,. And By performing the averaging process in this way, the measured data D,. ~ Random noise in the drive device 5 3 gets on D „ _ffl Inconvenience can be suppressed.

Next, the correction signal processing circuit 11 outputs the initial output data ν _ίηΠ . ~ _{Ν ίπηί1} and the corresponding measurement data D _,. DD _nm to generate a correction data C (C _{1 ()} to C „ _m ) and store this in the correction data storage circuit 10. Figure 7 shows the correction data C _{1 ( )} is a diagram showing a configuration example of a ~ C _nra. as shown in FIG. 7, the correction data C _1Q ~ C _nm, the initial output data V _{_ini lQ} ~ V _ini _tm corresponding from the measured data D _1Q to D _nm For example, a value obtained by subtracting the initial output data V _in no from the measurement data D, .. is applied to the drive circuit ₅₃ to output a digital voltage having the same voltage as the initial output data V in _lQ. When the signal is input, the correction amount for the image output terminals 1-, is C. Similarly, the initial output data V _{ini tra} is subtracted from the measurement data D _ηπι to _{obtain the} initial output to the drive circuit ₅₃ . When a digital signal of the same voltage as the data _Vinila is input to the image output terminal _{1_} „ The correction amount is C _nm .

Correction data C, initial output data _V _init "~ V initm measured de Isseki D ₁ with respect to the change in ₍₎ to D changes the k-th order curve of _Nffl (k is 1 or more (m + 1) any integer below) in similar, may be obtained from the approximate curve. for example, consider the case of approximating by a quadratic curve ^{(y = ax 2 + bx +} c). in this case, the initial in the image output terminal 1, if example embodiment The change in the measured data D _{1 ()} to D „with respect to the change in the output data V _init ~ V _inilm can be expressed by the following equation.

D ₁₀ = a V _init0 ² + b V _inil0 + c

D ,, = a V _inill ² + b V _inil , + c

D _lm = a V _inilm ² + b V _ini + c

The correction signal processing circuit 11 obtains three coefficients a, b, and c from these multiple equations. _If the changes in the measured data D and „to D _lm with respect to the changes in the initial output data V _{inM ()} to V _inilll cannot be approximated by a quadratic curve, Approximate by the k-th order curve more than that and find the coefficient.

Measurements with respect to the initial output data _V inilQ ~ V _ini changes in other image output terminal 1 _ ₂ ~ 1- _n data D _2. Similarly, for the change in ~ D _求め_る _π , the coefficient is obtained by approximating the k-th order curve, and the order k of the approximate curve can be different for each of the image output terminals 1 to 1_n.

Correction signal processing circuit 1 1, each image output terminal 1 _ After determining the approximate curve for each ~ 1 _ _n, V. voltage value of the plurality of levels the expression of the approximate curve To V _M, and the voltage value V from the approximate value obtained by the operation. Isseki especially good go-between correction de subtracting the ~V _M to generate _{_{C (C 1Q ~ C nM)}} .

FIG. 8 shows the corrected data C, obtained from the approximated curve. FIG. 3 is a diagram illustrating a configuration example of C _nM . As shown in FIG. ~ C _nM , measurement data D _,. Input voltage value V. the ~ D _nm from the approximate value obtained Ri by the approximate curve based on Corresponds to the digital voltage value obtained by subtracting the ~ V _M. For example, m pieces of the measurement data D _1G to D _lm than obtained the M input voltage value V ₀ ~V _M corresponding from the approximate value minus respectively, the voltage value V. to the drive circuit 5 3 A correction amount C, for the image output terminal 1 when a digital signal having the same voltage as V _M is input. ~ C _1M . Similarly, the corresponding input voltage value V. From the _M approximate values obtained from m pieces of measurement data D „to D _{nm, the} corresponding input voltage value V. The correction amounts C _n _端子 to C _nM for the image output terminals 1- „when a digital signal of the same voltage as V _M to V _M are input.

In this case, the input voltage value VQVM is also set within the range of the magnitude (voltage value) of the digital image signal input to the driving device 53, and the number, interval, and the like depend on the required accuracy. Can be set arbitrarily from an external control terminal (not shown). By setting m <M, the resolution of the correction data can be further increased, and more accurate correction can be performed. Also, the initial output data V _inil from the beginning. ~ _{Measured when} the number of V _initD1 is increased Although it takes a lot of time, the measurement time can be shortened by _reducing the number of initial output data V _{ini IQ} V _initn and calculating more approximate M values by calculation.

Figure 10 shows the results of performing the tessellation processing and the averaging processing by the correction signal processing circuit 11 on the 1-hit digital modulation signal output from the delta-sigma modulation 9 powers. O In Fig. 10, the sample points of the 1-bit digital modulation signal of decimation II are the points in time indicated by the dotted line in the time axis direction, and the sample after decimation 3 The dots are the points indicated by the arrows.

The point indicated by “X” in the figure is the voltage value as a result of the τ-sigma 3 processing and averaging processing of the delta-sigma variable P frequency signal with respect to the ideal linear input signal as shown in Fig. 4 (A). It is. This is equivalent to the value of the initial output data v _init v _inilm . The point indicated by “〇” in the figure is the voltage value obtained as a result of the decimation processing and the averaging processing of the delta-sigma modulated signal with respect to the non-linear input signal as shown in FIG. 4 (B). This corresponds to, for example, the value of the measurement data D _{i ()} D regarding the image output terminal 1. In FIG. 10, lines a and b are approximate curves approximating the changes in the voltage values indicated by “X” and “〇”, respectively. The length of the line c corresponds to the correction amount at one sample point after the simulation. When using an approximation curve, the sample points for which the correction amount is taken need not necessarily coincide with the “X” point, but can be taken at any position (as mentioned above, there are more than m M points). It is possible to obtain the correction data C ₁₀ C and _M for the sample points of. Since the line a corresponds to the change in the output voltage value when there is no variation in the electrical characteristics, the correction amount is “0” for all the input voltage values. On the other hand, the line b includes a non-linear variation. “&. Therefore, by correcting with the correction amount represented by the line c, the error of the output voltage value due to the variation is reduced. Can be done.

As described above, the image output terminal 1 _ Reducing the size of the transistors, but the non-linear variation in the output voltage value of 1 _ _n occurs, initial output data V _{inn Q} v of a plurality of stages as in the present embodiment enter the _{Inil ni} correction data c (C, C _nm or C, C _{1 M)} by determining, it is possible to correct accurately than linear correction by offset and Gay N'nomi.

The generation of the correction data as described above can be performed even when the driving device 53 is mounted on the liquid crystal display device S. In this case, errors due to variations in the electrical characteristics of the TFT transistor and capacitance of the display unit 51 connected to the image output terminal 1 of the driving device 53 are also included in the analog signal to the image output terminal 1. Since the data is reflected, the correction data is generated in a form including the error due to the variation of the display unit 51.

Although the example in which the correction data C is stored in the correction data storage circuit 10 has been described here, the coefficient data A of the k-th approximate curve is stored as shown in FIG. 11 to correct the digital image signal. In some cases, the correction data C may be calculated each time from the k-th approximation curve using the coefficient data A.As described above, the order k of the approximation curve differs for each image output terminal 1_ι ~ 1. It is possible to make it. In addition, the order k of the approximate curve is represented by “〇

It is also possible to make it different for each sample point indicated by J (using a different approximation curve between the sample points). Further, an exponential function or a logarithmic function may be used as the approximate curve.

Further, the correction may be repeatedly performed using the correction data C stored in the correction data storage circuit 10, and the degree of correction may be verified.If the error does not converge within a predetermined range, It is also possible to reduce the accuracy to a range where convergence is possible or to output an abnormal signal.

In the verification process in this case, the correction is performed when the initial output data _Vinil is input. Based on the measured data D obtained using the data c, the correction amount for the initial output data _Vinil is further calculated, and the newly calculated correction amount is added to the already generated correction data C. Corrections can be made. If the degree of correction by the new correction data C obtained in this manner does not converge within a predetermined convergence range, the correction data C may be further corrected.

As described above, normally, the generation of the correction data is automatically completed when the power is turned on. During normal operation after the correction data is generated, the delay sigma modulator 9 is controlled so as not to operate. Also, signal switching unit 4 0 § Na port grayed sweep rate pitch 3 -, all ~ 3 _ _n is also placed in the non-selected state. At this time, the digital image signal input to the input latch circuit 8 is corrected by the correction signal processing circuit 11 based on the correction data stored in the correction data storage circuit 10, and the τ digital correction signal is Is output to Then, the digital correction signal output from the latch circuit 6 becomes the input data to the D / A converters 5_, to 5- _n, and the voltage of the analog image signal to each image output terminal 1-, to 1- „. The value is controlled to the optimal value.

Next, a method of inspecting and evaluating the drive 53 and the display unit 51 will be described. The inspection and evaluation of the drive clothing 53 itself is performed with the drive device 53 not mounted on the liquid crystal display device S (with the image output terminal 1 open). For example, in a state where the LSI of the driving device 53 is configured on an antenna, the inspection and evaluation of the device 18 are performed.

Figure 12 is a diagram showing an example of the configuration of a test system in the case of performing inspection and evaluation of Vehachi. The test system shown in FIG. 12 includes a personal computer 90 that performs data processing, a simple digital tester 91, a probe card 92, and a probe 93. It is composed of The simple test 91 is, for example, a measurement period that is longer than the clock cycle of the delta-sigma modulator 9. It consists of a small digital oscilloscope or a mouth analyzer.

This simple test 91 has a decimation filter, and performs a decimation process on a 1-hittental modulation signal input from the delta-sigma modulator 9 via the delta-sigma output terminal 2. This eliminates quantization errors by performing demodulation to a digital signal of a predetermined number of bits (corresponding to the digitized output voltage of the image output terminal 1). However, a highly accurate digital voltage value can be obtained. This decimation filter is formed by, for example, an FIR filter as shown in FIG. The configuration for performing Decimen 3 is not limited to this, and it is also possible to use DSP or another configuration.

When inspecting / evaluating the driving device 53 using the test stem configured as described above, the needle 92 a of the push-in force 92 includes the Delauna sigma modulation output terminal 2. Several terminals were connected, and correction data for correcting errors due to the dispersion of the target characteristics of each transistor in the drive circuit 53 was generated in advance and written to the correction circuit 0. It is in a state.

First, a predetermined test unit is input via the input latch circuit of the driving device 53. The signal image of the test pattern input to the input latch circuit 8 is corrected by the IE 7 in the signal processing unit 10 and then converted into an analog image signal by the DZA converter 5. The analog image signal is transmitted through the driving transistor 4 and the signal switching unit 40.

Input to sigma modulator 9. Then, the raw ^1, ...,..., 変調変調 ■ ― ― ― ― ― ― ― ― ― ― ― デルデルデルデルデルデルデルデルデルデルデル. Note that the signal output from Delta-sidder modulation output pin 2 The signal is serial or zoned depending on the specifications of the drive 53. It can be configured to input a simple test with raller.

The simple tester 91 can receive the 1-bit digital modulation signal output from the delta-sigma modulation output terminal 2 via the probe card 92. In this simple tester 91, the delta-sigma modulation output

The pulse waveform of the 1-bit digitally modulated signal input via the card 92 is displayed so that it can be observed on the display. In addition, digital signal processing such as demodulation processing is performed on the pulse waveform, and the demodulated digital voltage value is measured.

At this time, if the measured voltage value deviates from the voltage value that should be output (the voltage value of the tester) by a predetermined value or more (when the correction data does not allow for sufficient correction), The driving device 53 is determined as a defective product. In addition, even if the measured voltage value is shifted, if it is within the range that can be corrected, it is determined that it can be used. In some cases, the operation of the delta-sigma modulator 9 itself is defective, but in this case, the delta-sigma modulated signal is not output or the waveform pulse is abnormally disturbed. It is possible.

Here, a conventional test system will be described for comparison with the test system according to the present embodiment as described above. FIG. 18 is a schematic diagram schematically showing a conventional test system. FIG. 18 shows an example of the configuration of a test system for inspecting and evaluating the drive LSI configured on the top X. This test system is composed of the following components: size <divided test section 100, tester body 101, test head 102, probe force head 103, and prober 104. o Open mouth 1 0

3 has a plurality of hands 103a.

Outputs image signals, such as display LSIs, on multiple pins The number of output values that can be measured simultaneously is limited by the number of probes 103a of the probe force 103, and the test price is proportional to the test time per LSI. If the number of pins increases beyond the number of the needles 103a, the test price also increases. Therefore, in order to suppress the test price, a test system that can measure the output values of multiple pins at the same time is required.

In the test system shown in Fig. 18, the output terminal (pin

) By arranging the number of needles 103 a corresponding to the number on the probe card 103, a measurement circuit and a signal output circuit can be used for each pin of the driving LSI. However, recently, the needle 103 of the professional card 103 is 10

In some cases, it may exceed pin 0. If the pin is 100000, the signal for the 100000 pin is the tester body 101, the test head 102, the probe card 10

Exchanged between three. Therefore, such a multi-pin test system has a very large configuration.

In addition, when the number of pins and the miniaturization of the drive LSI advance, if the pitch between the output terminals further narrows, it is necessary to create a probe card 103 having a needle 103 a corresponding to the pitch. In addition to the difficulty, the inspection itself becomes difficult, which leads to a decrease in the reliability of the inspection. Also, if a probe card 103 corresponding to the very fine pin pitch of the drive LSI cannot be made, it is necessary to perform multiple tests on one drive LSI, which increases the test price. What is Shima?

In the technique described in Patent Document 3 described above, signals output from a plurality of output terminals of a driving LSI are separately output to the outside from test terminals provided at a ratio of one to a predetermined number of output terminals. It is also described. According to Patent Document 3, switches are provided between one inspection terminal and a predetermined number of output terminals, respectively, and an image signal appearing at the output terminal is output by the switch circuit. Are sequentially selected and output to the inspection terminal. With this configuration, it is possible to perform inspection using the image signal output from the inspection element without applying probe pins to all of the many output terminals. It can respond to pinning.

However, according to the technology described in Patent Document 3, since the output signal from the inspection terminal is an analog signal, an analog test device must be used as an inspection device. Therefore, there is a problem that the test system becomes large-scale. Another problem is that noise components are easily included in the output signal, making it difficult to perform inspection and evaluation with the same accuracy.

On the other hand, in the example of the present embodiment shown in FIG. 12, a single drive LSI can be used without using a probe card having a large number of needles as used in the conventional test system. Inspection / evaluation can be performed using a probe card 92 having a very small number of needles (10 in this example). Inspection of electrical wiring short Z open, resistance value, capacitance value, transistor characteristics, etc., using the output from one delta sigma modulation output terminal 2 instead of the output from many image output terminals 1 That is because they can do it.

As described above, according to the present embodiment, it is possible to inspect and evaluate a super-high pin analog image signal using a 1-bit digital signal line. Also, since the signal to be handled is a digital signal, an analog type tester is not required.

Inspection and evaluation can be performed by the very simplified simple tester 91 and the personal computer 90. The inspection signal input to the simple test 91 is a digital signal. Therefore, high-precision inspection and evaluation can be performed without being affected by noise.

The inspection and evaluation of the driving device 53 can be performed even when the driving device 53 is mounted on the liquid crystal display device S. Drive device 5 3 to liquid crystal display device S When mounted, errors due to variations in the electrical characteristics of the TFT transistors and capacitors included in the table T unit 51 connected to the image output terminal 1 of the driving device 53 are also reflected in the analog image signal. Therefore, the analog image signal is converted to a delta-sigma signal by the delta-sidma modulator 9 and the 1-bit digital modulation signal is extracted as a detection signal. Can also be performed at the same time.

Fig. 13 is a diagram showing an example of the configuration of a test system for testing and evaluating the liquid crystal device S with the driving device 53 mounted. When performing the correction, the correction circuit memory circuit 10 of the driving circuit 53 stores the variation in the electrical characteristics of each transistor in the driving device 53]] and the TFT circuit in the display unit 51. Correction data for correcting errors due to fluctuations in the characteristics of capacitance and capacitance characteristics are generated and stored in advance.o

As shown in Fig. 13, the inspection and evaluation of the liquid crystal display device S is also a simple tester.

1 and personal computer 90 can be used. To the simple test 91, the 1-bit modulation ^ 5 generated by the DEL SIGMA modulator 9 when a test pattern is input to the input latch circuit 8 is transmitted to the DEL SIG. All you have to do is input the signal from the modulation output terminal 2.

If the voltage value measured based on the 1-bit digital modulation signal deviates from the original output threshold voltage value by a predetermined value or more in 1, the liquid crystal display device S is determined to be defective. Even if the measured voltage value is shifted, if it is within the correctable range, it is determined that it can be used.

In the state where the driving device 53 is mounted on the liquid crystal display device S as shown in FIG. The pixel capacity of the display unit 51 can be measured by outputting the image to the image output terminal 1 via the external device. Picture By applying a pulse signal to the image output terminal 1 and measuring its transient characteristics with the delta-sigma modulator 9, the capacitance and resistance in the display unit 51 connected to each image output terminal 1—, 1_ „ In this case, if the time interval to be measured is short, the clock speed of the delta-sigma modulator 9 is changed.

As described above in detail, in the driving device 53 of the present embodiment, the analog image signals output from the many image output terminals 1 _ and 1 „are converted into 1-bit digital modulation signals by the delta-sidma modulator 9. This can be output to the correction signal processing circuit 11 and the delta-sigma modulation output terminal 2 by one wire, so that the number of wires is small and the manufacturing cost can be reduced, and the driving device 53 The size can be reduced.

Further, according to the present embodiment, it is possible to improve the correction accuracy of the digital image signal. That is, since the delta-sigma modulator 9 is mounted on the same semiconductor chip as the driving device 53, the accuracy of the signal due to noise is lower than when the analog signal is output to the outside of the semiconductor chip and subjected to AZD conversion. Can be reduced.

In addition, as a configuration of the driving device 53, an AZD converter is simply provided instead of the delta-sigma modulator 9, and the digital output is used as a correction signal processing circuit 1.

If the configuration is such that the digital image signal is supplied to the correction signal processing circuit 11, the precision of the digital image signal fed back to the correction signal processing circuit 11 is fixed by the precision of the AZD converter. On the other hand, since the driving device 53 of the present embodiment uses the Dell Sigma modulator 9, the degree of freedom of calculating the correction data is not limited to the number of bits of the AZD converter. The clock speed of the delta-sigma modulator 9 is configured to be changeable, so that by setting the clock speed of the delta-sigma modulator 9 to a high speed, the time resolution can be increased to 1 bit. S-ratio of digitally modulated signal It is possible to improve. As a result, highly accurate correction data can be obtained.

Further, according to the present embodiment, the inspection accuracy can be improved. That is, the number of probe card needles corresponding to several output pins including the delta-sigma modulation output terminal 2 is sufficient. As a result, it is possible to increase the pitch of the □ -pin, and it is possible to securely connect to the delta-sigma P-peripheral output terminal 2. In addition, since the signal output from the delta-sigma variation P output terminal 2 is a digital signal, the accuracy of the signal is reduced due to noise compared to the case where an analog signal is output. It is possible to perform high-precision inspections and evaluations with reduction.

Further, a delta-sigma modulator 9 is used as a configuration of the driving device 53, and

Since the configuration is such that the setting of the clock speed can be changed, unlike the case where the A / D converter is simply used, the number of bits is not limited and a high-precision inspection signal can be obtained. That is, by changing the clock speed of the delta-sigma modulator 9, it is possible to detect a 1-bit digital modulation signal corresponding to the inspection accuracy by an external inspection device. By setting the D-cock speed of the delta-sigma modulator 9 to a high speed, the time resolution is increased and the detection signal

It is possible to improve the S / N ratio.

Further, according to the present embodiment, the configuration of the inspection device can be simplified. That is, as described above, the probe card needles need only correspond to a few output pins including the Delaware sigma modulation output terminal 2. Also, since the signal output from the delta-sigma modulation output terminal 2 is a digital signal, measures against signal deterioration and noise can be simplified, and there is no need to configure a large-scale inspection device with an expensive analog type tester.

In the above embodiment, the signal switching unit 40 is implemented by a transistor or the like. Although the example using the analog switch 3 has been described, the present invention is not limited to this example. For example, as shown in Fig. 14, an analog memory 41 (41-, ~ 41- „) may be used for the signal switching section 40. Even in this case, each image output terminal 1-, ... The analog image signal output from 1 can be selectively input to the delta-sigma converter 9. In this case, too, instead of the drive signal 4 (4— It is possible to use a keyer circuit.

In the above embodiment, the output from the latch circuit 6 is output to the image output terminal 1 via the D / A converter 5 and the driving transistor 4.

However, the present invention is not limited to this example. For example, as shown in FIG.

Multiple analog signal switches (multiplexers) connected to 1 3 2 (3

An analog image signal may be output to the image output terminal 1 through 2-'to 3 2. „).

When the driving device 53 is configured in this way, the grayscale voltage source 31 and the analog

The DZA conversion using the Og signal switch 32 is performed as follows. That is, the digital image signal input to the input latch circuit 8 is transferred to the correction signal processing circuit 22 and corrected here. After the correction based on the correction data C stored in the data storage circuit 21, the digital correction signal is output to the latch circuit 6. From the latch circuit 6, each image output terminal

Digital correction signal in response to the 1 ~ 1 _-n is outputted to the analog signal switching device _{3 2 ~ 3 2 · _ η} . Then, a gray scale voltage having a value corresponding to the digital correction signal is supplied from the gray scale voltage source 31 to the analog signal switches 32 to 32_ „and output to the image output terminals 1 to 1 1. You.

In the case of the example shown in FIG. 15, the correction signal processing circuit 22 includes a correction circuit for correcting an error due to a variation in each of the gradation voltages V 1 to V i of the gradation voltage source 31, and each analog signal. Compensate for errors due to variations in signal switchers 32 to 32_ Correction data for correction is generated and stored in the correction data storage circuit 21. The correction signal processing circuit 22 corrects (global correction) the variation of the gradation voltages V 1 to V i, and outputs the image output terminals 1 to 4 to the digital image signal supplied from the input latch circuit 8. Correction of variation between 1 and _n (Misma

V-correction). By performing the correction of the gray scale voltage source 31, it is possible to correct the variations of the gray scale voltages V 1 to Vi which are common to the plurality of image output terminals 1 to 1 „.

FIG. 16 is a diagram showing a configuration example of measurement data obtained when generating the correction data when the driving device 53 is configured as shown in FIG. Fig. 16

(A) shows measurement data D _1Q to D _nm measured by the delta-sigma modulator 9 when generating correction data for performing mismatch correction. This measurement data is the measurement data D, shown in FIG. To _ηπ . On the other hand, FIG. 16 (Β) shows the measured data D _,, 'to _Dη ' measured by the delta-sigma modulator 9 when generating the correction data for performing the global correction. As shown in FIG. 16 (Β), the measurement data D _n ′ to D ′ for global correction are output from the correction signal processing circuit 22 as a reference digital signal as initial output data V _grad , When ~ V _gradi (the ideal value of the gradation voltage) is sequentially output to the analog signal output unit 30, for example, the analog signal output to the image output terminal 1 is delta-sigma modulated by the Dell Sigma modulator 9. Is the digital voltage value measured by Here, the image output terminal 1 is used, but other image output terminals _1-2 to 1_ „may be used.The measurement was performed using a plurality of image output terminals 1 to 1. The respective voltage values may be averaged.

The correction signal processing circuit _{22 calculates} the approximate curve based on the measurement data D _1Q to D „for mismatch correction shown in FIG. The correction data C as shown in Fig. 8 is calculated. By taking the difference between the measured data D _,, 'D _η , and the initial output data V _{sr ad l} to V _gradi shown in FIG. Calculate the correction data C '. Similar to the correction data C for mismatch correction, the correction data C ′ for global correction obtains an approximate curve from the measurement data D,, D, i, and the correction data is obtained based on the approximate curve. C ′ may be calculated,

These correction data CC 'are used to determine the correction for global correction: the first correction C, and then use the corrected grayscale voltages V, ~ Vi to correct the correction C for mismatch later. Is preferably obtained from Further, the calculation of the correction data C 'for global correction and the calculation of the correction data C for S-smatch may be repeated. The correction data processing circuit 22 stores the correction data c C obtained in this manner in the correction data storage circuit 21. Then, the global correction is performed based on the stored correction data C, and the mismatch correction is performed based on the correction data C.

In the above embodiment, the signal output through the delta-sigma modulator 9 is an analog image signal to be output from the image output terminal 1, but is not limited thereto. That is, an analog signal supplied from another analog circuit connected to the drive clothing 53 or a large analog signal output to another analog circuit is converted into a digital signal through the delta-sigma frequency converter 9. May be output.

In the above embodiment, an example in which the present invention is applied to a voltage-driven liquid crystal display device S has been described. However, the present invention can be applied to a current-driven organic EL display device. In addition, the present invention can be applied to other displays such as a plasma display and a surface electric field display.

In addition, each of the above embodiments is a specific example for implementing the present invention. It is merely an example of the conversion, and the technical scope of the present invention should not be interpreted in a limited manner. That is, the present invention can be implemented in various forms without departing from the spirit or main features thereof. Industrial applicability

The present invention relates to a drive device having many analog output terminals such as an LSI for driving a display device such as a liquid crystal display device, an organic EL display device, a plasma display, and a surface electric field display, and a display device using the drive device. , And a method for inspecting a driving device or a display device.

Claims

The scope of the claims

1. A display device driver having a plurality of output terminals and outputting an analog signal from the plurality of output terminals,

A signal processing unit that inputs a digital signal corresponding to the plurality of output terminals and outputs a digital correction signal obtained by correcting each digital signal with correction data corresponding to a signal size;

An analog signal output unit that generates an analog signal based on the digital correction signal output from the signal processing unit and outputs the analog signal to the plurality of output terminals,

A signal switching unit that is connected to the plurality of output terminals and sequentially selects an analog signal from the analog signal output unit;

A delta-sigma modulation unit that performs a Dell Sigma modulation on the analog signal selected by the signal switching unit and outputs a 1-bit delta-sigma-modulated digital modulation signal to the signal processing unit;

The digital signal processing unit sequentially outputs the base digital signal of a plurality of levels to the analog signal output unit, and the 1-bit digital modulation corresponding to the reference digital signal from the delta-sigma modulation unit. It has a function of calculating the upper ci correction data based on the demodulated signal and the reference digital signal, and a function of performing correction based on the correction data. Characteristic display device driving device.

2. The upper ρϋ analog signal output unit is configured to include a plurality of DA converters for converting digital signals corresponding to the plurality of output terminals into analog signals, respectively. Display in section;) ±

Stationary driving device.

3. The analog signal output section is a digital signal processor corresponding to the plurality of output terminals. A plurality of analog signal switches each outputting a gradation voltage based on the

2. The driving device for a display device according to claim 1, further comprising a grayscale voltage source that supplies a grayscale voltage to the plurality of analog signal switches.

4. The signal processing unit is configured to calculate correction data for gradation voltage correction based on the demodulated signal with respect to the reference digital signal having the plurality of levels of magnitude,

4. The gray-scale voltage source according to claim 3, wherein the gray-scale voltage is adjusted based on the gray-scale voltage correction data calculated by the signal processing unit. 4. A driving device for a display device according to claim 1.

5. The signal processing unit calculates an approximate curve based on a change in the demodulated signal with respect to the reference digital signal having the plurality of levels, and calculates the correction data based on the approximate curve. The driving device for a display device according to claim 1, wherein

6. The signal processing unit calculates an approximate curve based on the change of the demodulated signal with respect to the reference digital signal having the plurality of levels of magnitude, and based on the approximate curve, the correction data for the gradation voltage correction. The driving device for a display device according to claim 4, wherein:

7. The signal processing unit calculates the correction data by using an average value of the demodulated signals for a plurality of times generated by outputting the reference digital signal of the plurality of stages in a plurality of times. The driving device for a display device according to claim 1, wherein

8. The display device driving device according to claim 1, wherein the correction data is calculated for each of the plurality of output terminals.

9. The signal switching section is a switch composed of transistors or analog 0 1

The driving device according to claim 1, wherein the driving device is constituted by:

10. The display device driving apparatus according to claim 1, wherein the desoring sigma modulation section is configured to be capable of setting a black and white M degree.

11 1 A delta-sigma modulation output terminal capable of outputting a 1-bit digital modulation f¾ signal from the delta-sigma modulation section is provided. Any one of claims 1 to 10 Or the driving device for a display device according to item 1.

12. The signal processing unit, the analog signal output unit, the signal switching unit, and the delta-sigma modulation unit are configured on the same semiconductor IC. 2. The driving device for a display device according to claim 1.

13. A display device provided with the drive device according to any one of claims 1 to 12.

14. A method for testing a driving device that outputs an analog signal from a plurality of output terminals or a display device including the driving device,

An analog signal generated based on the test pattern by sequentially switching a test pattern input step of inputting a test pattern to the drive device and a signal switch connected to a plurality of output terminals of the drive device; Analog signal acquisition step of sequentially acquiring

A delta-sigma modulation step of delta-sigma modulating the analog signal obtained in the analog signal obtaining step,

A delta-sigma modulation signal output step of outputting the 1-bit digital modulation signal generated in the delta-sigma modulation step from an inspection terminal to the outside,

The 1-bit digital modulation signal output from the test terminal is acquired and And an inspection method for inspecting or evaluating a driving device or a display device.

15. After the test pattern input step, a step of correcting the test pattern with the correction data is included.

14. The method according to claim 14, wherein in the analog signal acquiring step, an analog signal generated based on the test pattern corrected by the correction data is obtained. How to detect the drive or display device described in

16. 入力 Before the input process, input the reference digital signal of multiple steps to the above-mentioned driving device sequentially, and the analog signal generated based on the input reference digital signal. Signals are sequentially acquired by the above signal switch.

The 1-bit digital modulation signal is obtained by performing delta-sigma modulation on the upper pH signal and obtaining a 1-bit digital modulation signal. The method for inspecting a driving device or a display device according to Item 15, wherein the step of calculating the correction table is performed based on the following.