JP6239878B2 - LCD display driver - Google Patents

Description

  The present invention relates to a liquid crystal display driver, and in particular, can be suitably used for a liquid crystal display driver connected to a liquid crystal display panel compatible with dot inversion driving.

  Various methods have been proposed as methods for realizing dot inversion driving of liquid crystal display panels. In the dot inversion drive, pixel capacitors arranged in n rows and m columns are driven by signals on the positive side and the negative side alternately with reference to a common potential for each row, and alternately on the positive side for each column. And driven by a signal on the negative electrode side. Here, m and n are natural numbers, respectively. The liquid crystal display panel regulates the luminance to be displayed by changing the polarization of the liquid crystal depending on the magnitude of the applied electric field and controlling the transmittance. The pixel capacitor is formed by electrodes sandwiching the liquid crystal in order to give an electric field to be applied to the liquid crystal. The amount of polarization of the liquid crystal is defined by the absolute value of the applied electric field and is originally symmetric with respect to the direction of the electric field, but in reality, there is a bias due to various factors. For this reason, the direction of the electric field to be applied is dispersed spatially and temporally to suppress display image quality deterioration due to the bias. In the dot inversion driving method, the direction of the electric field is inverted for each pixel.

  Patent Documents 1 to 3 disclose liquid crystal display panels in which even-numbered column pixels and odd-numbered column pixels are alternately connected to data lines in a staggered manner. Pixel capacitances arranged in n rows and m columns are connected to n gate lines for each row, and each row from the first column to the m-th column data line and from the second column to the m + 1-th column data line. Are connected alternately. In order to drive m pixel capacitors per row, m + 1 data lines are provided. If the data lines are alternately driven by positive and negative signals one by one, dot inversion driving of the liquid crystal display panel can be realized.

  In Patent Documents 4 to 6, in order to alternately output positive side and negative side data drive signals based on a common potential, a positive side amplifier and a negative side amplifier are provided as m / 2 sets. A liquid crystal display driver is disclosed. The output is provided with a switch for switching the positive electrode and the negative electrode. The m data lines are alternately driven by positive and negative amplifiers one column at a time. The relationship between the positive electrode and the negative electrode is switched for each row. Thereby, dot inversion driving of the liquid crystal display panel can be realized.

Japanese Patent Laid-Open No. 04-223428 Japanese Patent Laid-Open No. 09-016132 JP-A-11-102174 Japanese Patent Application Laid-Open No. 09-026765 Japanese Patent Laid-Open No. 10-062744 Japanese Patent Laid-Open No. 11-095729

  As a result of examination of Patent Documents 1 to 6 by the inventors of the present application, it has been found that there are the following new problems.

  The data lines of the liquid crystal display panel driven by the liquid crystal display driver described in Patent Documents 4 to 6 are alternately driven by positive and negative data drive signals for each line period. If one line period is, for example, 30 frames / second and 1080 lines per frame, it is about 30.9 μs. One line period tends to be shortened with the increase in definition of the display panel. Therefore, high-speed performance tends to be required for amplifiers that are alternately driven by the positive and negative data drive signals. On the other hand, as the size of the display panel increases, the load capacity of the data line tends to increase, which hinders improvement in the switching speed between positive and negative, and is increasing the power consumption of the liquid crystal display driver.

  In the liquid crystal display panels described in Patent Documents 1 to 3, since the pixel capacitors driven by one data line are alternately arranged in a staggered manner for each row, data drive signals on the positive electrode side and the negative electrode side are output. It is not necessary to alternate each line period. However, since it is known that a burn-in problem occurs when the pixel capacitance is always driven by a data drive signal on the positive electrode side or the negative electrode side, in general, the positive electrode side and the negative electrode side are changed every frame period. Configured to replace.

  Patent Documents 1 and 2 do not disclose a specific operation of the entire display device including the data line driving circuit, but Patent Document 3 includes a circuit and an operation for switching the positive electrode side and the negative electrode side. It is described in FIG. 2 and paragraphs 0420 to 0580 in the literature. FIG. 2 illustrates a liquid crystal display panel with 3 rows and 3 columns, and three pixel capacities per line are arranged in a staggered manner for each line on four data lines X1 to X4. Three channel drive units CR1 to CR3 (corresponding to data line drive circuits) are connected to four data lines X1 to X4 via six switches. During the period when the gate line of the first row is activated, the odd-numbered channel drivers CR1 and CR3 output positive grayscale voltages to drive the odd-numbered data lines X1 and X3, and the even-numbered data lines X1 and X3. The channel driver CR2 outputs a negative gradation voltage to drive the even-numbered data line X2. In the period when the next second-row gate line is activated, the odd-numbered channel drivers CR1 and CR3 output negative gradation voltages to drive the even-numbered data lines X2 and X4. The second channel driver CR2 outputs a negative gradation voltage to drive the odd-numbered data line X3. During one frame scanning period, each data line is always driven with a voltage having either a positive polarity or a negative polarity (paragraph 0540). At this time, the channel driver alternately outputs a positive voltage and a negative voltage for each line (paragraph 0580). As described in FIG. 3 and the paragraphs 0030 to 0410 of the same document, the channel driver is configured to be switched between the positive voltage and the negative voltage depending on the inversion control signal RV. Has been.

  The inventors of the present application described in Patent Documents 4 to 6 instead of switching the output polarity of the data line driving circuit (channel driving unit in Patent Document 3) between positive polarity and negative polarity for each line. A liquid crystal display device in which a liquid crystal display panel described in Patent Documents 1 to 3 is driven by a simple liquid crystal display driver was examined. In the liquid crystal display drivers described in Patent Documents 4 to 6, a positive side amplifier and a negative side amplifier are used as a set in order to alternately output positive side and negative side data drive signals based on a common potential. Prepare. If the amplifier and the data line are connected via a switch and appropriately controlled, high-speed control for switching the polarity of the amplifier for each line period can be eliminated.

  However, it has been clarified that the following problems occur in the test of the data line driving circuit. First, the size of the liquid crystal display panel is set to n rows and m columns in terms of the number of pixels. The pixel capacitance is arranged in n rows and m columns. At this time, in the liquid crystal display panels described in Patent Documents 1 to 3, since the pixel capacitors driven by one data line are alternately arranged in a staggered manner for each row, the number of data lines is m + 1. Become a book. Here, in order to combine the liquid crystal display drivers described in Patent Documents 4 to 6, it may be configured to include (m + 1) / 2 sets of amplifiers. However, the actual size of the liquid crystal display panel is 1920 × 1080 for full high vision, 640 × 480 for VGA, etc., and m is an even number. Since the liquid crystal display driver must always include a positive amplifier and a negative amplifier as a set, the liquid crystal display driver includes (m + 2) / 2 sets of amplifiers. At this time, since the number of data lines to be driven is m + 1, the number of output pads is m + 1. In other words, the liquid crystal display driver includes a total of m + 2 amplifiers including positive amplifiers (m + 2) / 2 and negative amplifiers (m + 2) / 2, and m + 1 output pads.

  On the other hand, it has been found that in the test of the data line driving circuit, the gradation test of the amplifier is indispensable, and the test time required for the gradation test imposes a test cost. The amplifier converts digitally inputted data into an analog voltage level and outputs it. The gradation test is a test for confirming that an appropriate analog voltage level is output corresponding to an input digital code. Therefore, it takes a long test time to input all digital codes and measure the output voltage, and the ratio to the total test time is large, which has a great influence on the test cost.

  As described above, since the liquid crystal display driver under examination by the inventor has m + 1 output pads for a total of m + 2 amplifiers, even if all m + 1 output pads are used, all m + 2 amplifiers are used. It was found that the gradation test cannot be performed simultaneously. For this reason, the gradation test of m + 2 amplifiers is performed in two steps, and the test time required for the gradation test is doubled, and the influence on the test cost is extremely serious.

  Means for solving such problems will be described below, but other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  In the liquid crystal display driver according to the present invention, pixel capacitors arranged in n rows and m columns (n is a natural number and m is a positive even number) are connected to n gate lines for each row, and the first to mth columns. And a liquid crystal display driver connected to the data line of the second column to the data line of the (m + 1) th column to the (m + 1) th column alternately for each row. (M + 2) / 2 positive-side amplifiers to output, (m + 2) / 2 negative-side amplifiers to output a negative-side voltage with reference to the common potential, and (m + 2) / 2 at the time of gradation test Positive amplifiers and m + 2 pads to which output voltages of the (m + 2) / 2 negative amplifiers are output.

  The effect obtained by the one embodiment will be briefly described as follows.

  That is, the gray scale test of m + 2 amplifiers can be performed in parallel at the same time, the test time required for the gray scale test can be minimized, and the increase in test cost can be suppressed.

FIG. 1 is a block diagram showing a configuration of a liquid crystal display driver according to the present invention. FIG. 2 is a circuit diagram showing a configuration of a main part of a liquid crystal display panel compatible with dot inversion driving, which is connected to the liquid crystal display driver according to the present invention. FIG. 3 is a block diagram for explaining dot inversion driving of a liquid crystal display panel using the liquid crystal display driver according to the present invention. FIG. 4 is a block diagram for explaining the gradation test for the liquid crystal display driver according to the present invention. FIG. 5 is a characteristic diagram showing the relationship between the code corresponding to the image data and the drive voltage of the positive and negative data lines in the dot inversion drive method. FIG. 6 is an explanatory diagram showing an application sequence of driving voltages on the positive electrode side and the negative electrode side to the pixels of the liquid crystal display panel in the dot inversion driving method. FIG. 7 is a flowchart for explaining the gradation test for the liquid crystal display driver according to the present invention.

1. First, an outline of a typical embodiment disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] <Add test pads to the same number as the amplifier>
In a liquid crystal display driver (100) according to a representative embodiment disclosed in the present application, a pixel capacitor (1) arranged in n rows and m columns is connected to n gate lines (G1 to Gn) for each row. The liquid crystal display panel (200) is alternately connected to the data lines (D1 to Dm) from the first column to the mth column and the data lines (D2 to Dm + 1) from the second column to the (m + 1) th column for each row. It can be connected to and is configured as follows. Here, n is a natural number, m is a positive even number, and the same applies hereinafter.

  The liquid crystal display driver outputs a positive-side voltage (m + 2) / 2 positive-side amplifiers (101) with reference to the common potential, and outputs a negative-side voltage with respect to the common potential (m + 2) / Two negative side amplifiers (102), and m + 2 pads (to which output voltages of the (m + 2) / 2 positive side amplifiers and the (m + 2) / 2 negative side amplifiers are output at the time of the gradation test) 161).

  As a result, the gradation test of m + 2 amplifiers (101, 102) can be performed simultaneously in parallel, the test time required for the gradation test can be minimized, and the increase in test cost can be suppressed. .

[2] <Crossbar switch>
In (1), the (m + 2) / 2 positive side amplifiers are first to (m + 2) / 2 positive side amplifiers, and the (m + 2) / 2 negative side amplifiers are from the first. The (m + 2) / 2 negative amplifiers, and the m + 2 pads are the first to m + 2 pads.

  The liquid crystal display driver further includes first to (m + 2) / 2 crossbar switches (150, 151).

  The i-th crossbar switch is selectively controlled between straight connection and cross connection. In the straight connection, the output of the i-th positive side amplifier is connected to the second i-1 pad, the output of the i-th negative side amplifier is connected to the second i pad, and in the cross connection, the output of the i-th positive side amplifier is connected. The second i-pad is connected, and the output of the i-th negative side amplifier is connected to the second i-1 pad. Here, i is an integer greater than or equal to 1 and less than or equal to (m + 2) / 2, and the same applies hereinafter.

  Thereby, the polarity of the drive voltage can be inverted by a simple circuit, and the control for the dot inversion drive of the liquid crystal display panel (200) can be simplified.

[3] <Data latch>
In item 2, the liquid crystal display driver includes a positive-side gradation voltage generation circuit (141), a negative-side gradation voltage generation circuit (142), and first to m + 2 data latches (130, 131, 132). And first to m + 2 grayscale selection circuits (110, 111, 112).

  The positive-side gradation voltage generation circuit (141) outputs a plurality of positive-side analog voltages with the common potential as a reference, and supplies the analog voltage to the 2i-1 gradation selection circuit (111). The regulated voltage generation circuit (142) outputs a plurality of negative-side analog voltages with the common potential as a reference, and supplies the analog voltages to the second i gradation selection circuit (112).

  The second i-1 gradation selection circuit (111) selects one analog voltage from the plurality of positive-side analog voltages based on the value held in the second i-1 data latch (131). , And supplied to the i-th positive side amplifier (101).

  The second i gradation selection circuit (112) selects one analog voltage from the plurality of analog voltages on the negative electrode side based on the value held in the second i data latch (132), and the i th Supply to the negative side amplifier (102).

  Thereby, the absolute value of the voltage level for driving the data line of the liquid crystal display panel (200) is set in the data latch (130), so that the polarity of the electric field applied to the liquid crystal pixel is automatically controlled by dot inversion. As described above, the signal level for the data line is controlled and output from the pad (161). Further, since the data latch (130) is provided with m + 2 which is two more than the number m of pixels per line of the liquid crystal display panel to be connected, input data for gradation test with respect to m + 2 amplifiers is provided in parallel. Can be set.

[4] <Dot inversion operation>
In item 3, the first to (m + 1) th pads are connected to the first to m + 1th data lines of the liquid crystal display panel, respectively.

  The outputs from the first to (m + 2) / 2 so that the output of the positive side amplifier and the output of the negative side amplifier are alternately supplied to the data lines of the even and odd columns for each field period. The crossbar switch is controlled. That is, in the first field period, which is one of the odd field period and the even field period, the output of the positive side amplifier is supplied to the odd-numbered data line, and the output of the negative side amplifier is supplied to the even-numbered data line. Is supplied. In the other second field period, the output of the negative side amplifier is supplied to the odd-numbered data lines, and the output of the positive side amplifier is supplied to the even-numbered data lines.

  In the first field period, image data to be displayed in odd rows of the liquid crystal display panel is input to the first to m + 1th data latches, and even numbers of the liquid crystal display panel are input to the second to m + 2 data latches. Image data to be displayed in a row is input.

  In the second field period, image data to be displayed in odd rows of the liquid crystal display panel is input to the second to m + 2 data latches, and even numbers of the liquid crystal display panel are input to the first to m + 1 data latches. Image data to be displayed in a row is input.

  Accordingly, it is possible to provide a liquid crystal display driver capable of controlling the polarity of the data line to be inverted every field scan. Since the frequency of polarity inversion of the data line is suppressed for each field, not for each line, even if the load capacity of the data line is large, the power consumption can be kept low, and there is a demand for each of the positive side amplifier and the negative side amplifier. The slew rate can be kept low.

[5] <Gradation test>
In Item 3, the liquid crystal display driver is configured to be connectable to a test apparatus (400) including first to m + 2 voltage measurement units (421) and a pattern input unit (430).

  The first to m + 2 pads are connected to the first to m + 2 voltage measuring units of the test apparatus, respectively, and the first to m + 2 data latches are connected to the input code from the pattern input unit. Is configured to be settable.

  As a result, the gray scale test of m + 2 amplifiers can be performed in parallel at the same time, the test time required for the gray scale test can be minimized, and the increase in test cost can be suppressed.

[6] <Liquid crystal display driver IC>
In the liquid crystal display driver (100) according to Item 3, the (m + 2) / 2 positive side amplifiers, the (m + 2) / 2 negative side amplifiers, and the first to (m + 2) / 2ths. To the crossbar switch, the positive gradation voltage generation circuit, the negative gradation voltage generation circuit, the first to m + 2 data latches, and the first to m + 2 gradation selection. A circuit and the m + 2 pads are formed on a single semiconductor substrate.

  Thereby, a liquid crystal display driver integrated on one chip can be provided.

2. Details of Embodiments Embodiments will be further described in detail.

[Embodiment 1] <Configuration of liquid crystal display driver>
The liquid crystal display driver 100 according to the first embodiment can be connected to a liquid crystal display panel 200 that supports dot inversion driving. FIG. 1 is a block diagram showing a configuration of a liquid crystal display driver 100 according to the present invention, and FIG. 2 is a main part of a liquid crystal display panel 200 that is connected to the liquid crystal display driver 100 according to the present invention and is compatible with dot inversion driving. FIG.

  In the liquid crystal display panel 200, a pixel capacitor 1 arranged in n rows and m columns is connected to n gate lines G1 to Gn for each row via a pass transistor 2, and data from the first column to the mth column is connected. The lines D1 to Dm and the data lines D2 to Dm + 1 from the second column to the (m + 1) th column are alternately connected for each row. The pixel capacitors 1_1_1, 1_1_2, -1_1_m-1, 1_1_m in the first row are connected to the data lines D1 to Dm via pass transistors 2_1_1, 2_1_2, ˜2_1_m-1, 2_1_m controlled by the gate line G1. Yes. The pixel capacitors 1_2_1, 1_2_2, -1_2_m-1, 1_2_m in the second row are connected to the data lines D2 to Dm + 1 via pass transistors 2_2_1, 2_2_2, ˜2_2_m-1, 2_2_m controlled by the gate line G2. Yes. The pixel capacitors 1_3_1, 1_3_2, ˜1_3_m−1, 1_3_m in the third row are connected to the data lines D1 to Dm via the pass transistors 2_3_1, 2_3_2, and ˜2_3_m-1, 2_3_m controlled by the gate line G3. Yes. Although not shown in the drawings, the odd-numbered pixel capacitors 1 are connected to the data lines D1 to Dm, and the even-numbered pixel capacitors 1 are connected to the data lines D2 to Dm + 1 via the pass transistors 2, respectively. The pixel capacitors located in the same column are alternately connected to the data lines on both sides sandwiching the row for each row. The first column pixel capacitors 1_1_1, 1_2_1, 1_3_1,... Are alternately connected to the data lines D1 and D2, and the second column pixel capacitors 1_1_2, 1_2_2, 1_3_2,. Connected alternately to lines D2 and D3. By driving the odd-numbered data lines D1, D3,... Dm + 1 and the even-numbered data lines D2, D4,. In this case, pixel capacitors adjacent in the vertical and horizontal directions are driven by signals having opposite polarities, and dot inversion driving is performed.

  The liquid crystal display driver 100 outputs a positive voltage on the basis of the common potential (m + 2) / 2 positive amplifiers 101_1 to 101_m + 1 and outputs a negative voltage on the basis of the common potential (m + 2) / Two negative-side amplifiers 102_2 to 102_m + 2, and m + 2 pads 161_1 to 161_m + 2 to which output voltages of the positive-side amplifiers 101_1 to 101_m + 1 and the negative-side amplifiers 102_2 to 102_m + 2 are output during the gray scale test.

  As a result, the gray scale tests of the m + 2 amplifiers 101_1 to 101_m + 1 and 102_2 to 102_m + 2 can be performed simultaneously in parallel, minimizing the test time required for the gray scale test, and suppressing an increase in test cost. Can do.

  The liquid crystal display driver 100 includes a crossbar switch 150 that selectively controls straight connection and cross connection. The i-th crossbar switch 151_i switches the connection between two pads 161_2i-1 and 161_2i corresponding to the output of the positive amplifier 101_2i-1 and the negative amplifier 102_2i as a set. i is an integer of 1 or more and (m + 2) / 2 or less. In the straight connection, the output of the positive side amplifier 101_2i-1 is connected to the pad 161_2i-1, and the output of the negative side amplifier 102_2i is connected to the pad 161_2i. In the cross connection, the output of the positive amplifier 101_2i-1 is connected to the pad 161_2i, and the output of the negative amplifier 102_2i is connected to the pad 161_2i-1.

  Thereby, the polarity of the driving voltage for driving the data lines D1 to Dm + 1 can be inverted by a simple circuit, and the control for the dot inversion driving of the liquid crystal display panel 200 can be simplified.

  The liquid crystal display driver 100 includes a positive side grayscale voltage generation circuit 141, a negative side grayscale voltage generation circuit 142, first to m + 2 data latches 130, a level shift circuit 120, and first to m + 2th. The gradation selection circuit 110 is further provided. One data latch 130, one level shift circuit 121, and one gradation selection circuit 110 are provided corresponding to each of the positive side amplifiers 101_1 to 101_m + 1 and the negative side amplifiers 102_2 to 102_m + 2. Data latches 131_1 to 131_m + 1, level shift circuits 121_1 to 121_m + 1, and gradation selection circuits 111_1 to 111_m + 1 are provided corresponding to the positive side amplifiers 101_1 to 101_m + 1, and data latches corresponding to the negative side amplifiers 102_2 to 102_m + 2. 132_2 to 132_m + 2, level shift circuits 122_2 to 122_m + 2, and gradation selection circuits 112_2 to 112_m + 2 are provided.

  The positive-side gradation voltage generation circuit 141 outputs a plurality of positive-side analog voltages with reference to the common potential, and supplies the analog voltages to the gradation selection circuits 111_1 to 111_m + 1. The negative-side gradation voltage generation circuit 142 outputs a plurality of negative-side analog voltages based on the common potential and supplies the analog voltages to the gradation selection circuits 112_2 to 112_m + 2. Although not particularly limited, the common potential is, for example, a ground level of 0 V. If the gradation is, for example, 256 according to the gradation of the image data to be displayed, the positive-side gradation voltage generation circuit 141 has 256 positive-sides. The voltage level is output, and the negative side gradation voltage generation circuit 142 outputs 256 negative side voltage levels. The gradation voltage generation circuit is configured by, for example, connecting a power supply having a voltage in a range including the maximum value and the minimum value of the voltage to be output by connecting a number of resistors corresponding to the number of gradations in series. A plurality of analog voltages are generated by the divided voltage generated by.

  FIG. 5 is a characteristic diagram showing an example of the relationship between the code corresponding to the image data and the driving voltage of the positive and negative data lines in the dot inversion driving method. The horizontal axis represents codes corresponding to image data in hexadecimal notation, and the vertical axis represents drive voltages for the data lines D1 to Dm + 1. The characteristics on the positive electrode side and the negative electrode side are shown across the common potential 0V. When the code is 0x00 (00 in hexadecimal), the data line is driven at about 0.2V, for example, to display black (lowest luminance), and when the code is 0xFF (FF in hexadecimal), the data line is driven at about 4V, for example. Appears white (maximum brightness). The characteristics are symmetrical between the positive electrode side and the negative electrode side across the common potential 0V. That is, a voltage having the same absolute value on the positive electrode side and the negative electrode side is the drive voltage for the same cord. For 256 gray scale display, the code is 8 bits, and the positive gray scale voltage generation circuit 141 outputs 256 analog voltages obtained by dividing 256 between 0.2V and 4V to generate negative gray scale voltage The circuit 142 outputs 256 analog voltages obtained by dividing 256 between −0.2V and −4V. As shown in the figure, the relationship between the code and the drive voltage is not necessarily a proportional relationship indicated by a straight line, but is expressed by a non-linear curve. It is defined in consideration of the physical characteristics of liquid crystal and γ correction coefficient. The maximum value ± 4V and minimum value 0.2V of the voltage to be output, the number of gradations 256, and the code allocation method for them are all examples, and are not particularly limited thereto.

  The gradation selection circuits 111_1 to 111_m + 1 are based on the values (codes) held in the data latches 131_1 to 131_m + 1, and a plurality of positive-side analog voltages generated by the positive-side gradation voltage generation circuit 141 (0.2 in the above example). One analog voltage is selected from 256 analog voltages obtained by dividing 256 between V and 4V and supplied to the positive side amplifiers 101_1 to 101_m + 1. The grayscale selection circuits 112_2 to 112_m + 2 are configured to have a plurality of negative-side analog voltages (in the above example, −−) generated by the negative-side grayscale voltage generation circuit 142 based on values (codes) held in the data latches 132_2 to 132_m + 2. One analog voltage is selected from 256 analog voltages obtained by dividing 256 between 0.2V and -4V, and supplied to the negative-side amplifiers 102_2 to 102_m + 2. The level shift circuits 121_1 to 121_m + 1 and 122_2 to 122_m + 2 convert the output voltage levels of the data latches 131_1 to 131_m + 1 and 132_2 to 132_m + 2 into voltage levels suitable for controlling the gradation selection circuits 111_1 to 111_m + 1 and 112_2 to 112_m + 2.

  As a result, the absolute value of the voltage level for driving the data lines D1 to Dm + 1 of the liquid crystal display panel 200 is set in the data latch 130 as a digital value, so that the polarity of the electric field applied to the liquid crystal pixels is automatically changed to dots. The signal level for the data line is controlled so as to be inverted and output from the pad 161. Since the data latch 130 is provided with m + 2, which is two more than the number m of pixels per line of the liquid crystal display panel to be connected, the total m + 2 of the positive side amplifiers 101_1 to 101_m + 1 and the negative side amplifiers 102_2 to 102_m + 2. The input data for gradation test for the amplifiers 101 and 102 can be set in parallel.

  As described above, the liquid crystal display driver 100 according to the present embodiment includes the pads 161_m + 2 in addition to the pads 161_1 to 161_m + 1 for driving the data lines D1 to Dm + 1 of the liquid crystal display panel 200. In addition, a total of m + 2 data latches equal to the number of amplifiers to be tested are provided. Therefore, the gradation test of a total of m + 2 amplifiers including the positive side amplifiers 101_1 to 101_m + 1 and the negative side amplifiers 102_2 to 102_m + 2 can be simultaneously performed in parallel.

  The liquid crystal display driver 100 is not particularly limited. For example, the liquid crystal display driver 100 is formed on a single semiconductor substrate such as silicon by using a known complementary metal-oxide-semiconductor field effect transistor (CMOS) LSI (Large Scale Integrated circuit) manufacturing technique. It is formed. Thereby, a liquid crystal display driver integrated on one chip can be provided.

[Embodiment 2] <Dot inversion driving operation>
FIG. 3 is a block diagram for explaining dot inversion driving of the liquid crystal display panel 200 using the liquid crystal display driver 100 according to the present invention.

  The liquid crystal display driver 100 further includes a host interface 170 in addition to the liquid crystal display driver 100 illustrated in FIG. 1, and performs communication with the connected host processor 300. Image data of an image to be displayed on the liquid crystal display panel 200 is transmitted from the host processor 300, received by the host interface 170 by the liquid crystal display driver 100, and set in the data latch 130. The liquid crystal display panel 200 includes pads 261_1 to 261_m + 1 corresponding to the data lines D1 to Dm + 1. The pads 161_1 to 161_m + 1 of the liquid crystal display driver 100 are not particularly limited and are electrically connected to the pads 261_1 to 261_m + 1 of the liquid crystal display panel 200, for example, via a bump electrode and an anisotropic conductive film. . The liquid crystal display panel 200 may be further provided with one pad 261_m + 2 corresponding to the pad 161_m + 2 of the liquid crystal display driver 100 and connected to the pad 161_m + 2 of the liquid crystal display driver 100. As a result, structural symmetry is maintained and the occurrence of mechanical problems such as stress concentration can be mitigated.

  FIG. 6 is an explanatory diagram showing an example of the application sequence of the drive voltage on the positive electrode side and the negative electrode side to the pixels of the liquid crystal display panel in the dot inversion drive method. The polarity of the electric field applied to the pixel capacitors 1 arranged in the n rows and m columns via the data lines D1 to Dm + 1 is represented by the positive side “+” symbol and the negative side “−” symbol. (A) and (B) show application states in odd and even fields, respectively. In the dot inversion driving method, control is performed so that the polarity is inverted between adjacent pixels vertically and horizontally. Furthermore, control is performed so that the odd field and the even field are also inverted. The odd-numbered field and the even-numbered field are merely examples, and it is only necessary that the odd-numbered field and the even-numbered field are temporally dispersed so that the same liquid crystal is not continuously applied with the same direction polarity. This is to prevent the occurrence of a problem called burn-in.

  In order to perform dot inversion driving in the sequence shown in FIG. 6, the odd-numbered data lines D1, D3,... Dm-1, Dm + 1 are connected to the positive side amplifiers 101_1 to 101_m + 1 in the odd field by connecting the crossbar switch 150 straight. And the even-numbered data lines D2, D4,... Dm are controlled to be driven by the negative side amplifiers 102_2 to 102_m. In the even field, the crossbar switch 150 is cross-connected, and the odd-numbered data lines D1, D3,... Dm-1, Dm + 1 are driven by the negative side amplifiers 102_2-102_m + 2, and the even-numbered data lines D2, D4,. Control is performed so that Dm is driven by the positive side amplifiers 101_1 to 101_m + 1.

  By controlling in this way, in each data line, the polarity of the drive voltage is not inverted within one field period. The odd-numbered data lines D1, D3,... Dm-1, Dm + 1 are always driven with the drive voltage on the positive side during one field period of the odd field, and always with the drive voltage on the negative side in the next one field (even field). Driven. Similarly, the polarity of the drive voltage is inverted for each field in the even-numbered data lines, but there is no inversion within one field period. For this reason, the power consumption required for charging / discharging the data line is greatly reduced as compared with the control methods disclosed in, for example, Patent Documents 4 to 6, in which the polarity of the drive voltage of the data line is inverted every line period. can do. In addition, the required specifications for the slew rates of the amplifiers 101_1 to 101_m + 1 and 102_2 to 102_m + 2 are relaxed.

[Embodiment 3] <Gradation test of amplifier>
FIG. 4 is a block diagram for explaining a gradation test for the liquid crystal display driver 100 according to the present invention. The liquid crystal display driver 100 is connected to the test apparatus 400 for a shipping test including a gradation test. The test apparatus 400 includes a pattern input unit 430, the same number of voltage measuring units 421_1 to 421_m + 2 as the amplifiers 101_1 to 101_m + 1 and 102_2 to 102_m + 2 mounted on the liquid crystal display driver 100 to be tested, a memory 440, and a determination unit 450. Is provided. An output from the pattern input unit 430 of the test apparatus 400 is connected to, for example, the host interface 170 of the liquid crystal display driver 100 to be tested. If a predetermined code can be set in the data latches 131_1 to 131_m + 1 and 132_2 to 132_m + 2, it is not always necessary to set data via the host interface 170. For example, it may be automatically generated inside the liquid crystal display driver 100.

  The pads 161_1 to 161_m + 2 of the liquid crystal display driver 100 are electrically connected to the voltage measurement units 421_1 to 421_m + 2 in the gray scale test. For example, the probes 411_1 to 411_m + 2 are provided in the test apparatus 400, and are brought into contact with and electrically connected to the pads 161_1 to 161_m + 2.

  The liquid crystal display driver 100 is controlled to output corresponding analog voltages from the amplifiers 101_1 to 101_m + 1 and 102_2 to 102_m + 2 according to the codes set in the data latches 131_1 to 131_m + 1 and 132_2 to 132_m + 2, and the output voltage is output to the voltage measuring unit 421_1. Measure at ~ 421_m + 2. The measured output voltage value is once stored in the memory 440 and then sent to the determination unit 450. The determination unit 450 determines that the output analog voltage is defective if it falls outside the allowable range from the expected value corresponding to the set code.

  With this measurement method, the gradation test of m + 2 amplifiers can be performed in parallel at the same time, the test time required for the gradation test can be kept to a minimum, and the increase in test cost can be suppressed.

  FIG. 7 is a flowchart for explaining an example of the gradation test S1 for the liquid crystal display driver 100 according to the present invention. Although not particularly limited, for example, the gradation test S <b> 1 is one test item of a non-defective / defective product selection test that is performed on the liquid crystal display driver 100 before shipment. When the gradation test S1 is reached through other test items from the start of the test, and the determination result of “defective” is output (S9), the test is terminated. If not, proceed to other test items. In the gradation test S1, first, the input code is initialized (S11) and set in the data latches 131_1 to 131_m + 1 and 132_2 to 132_m + 2 (S12). Next, the output voltages from the amplifiers 101_1 to 101_m + 1, 102_2 to 102_m + 2 are measured by the voltage measuring units 421_1 to 421_m + 2 (S13), and the value of the measured output voltage is not particularly limited. Stored in the memory 440. The code is changed to an unmeasured code (S14, S11, S12), voltage measurement (S13) is repeated, measurement is completed for all codes, and the measured values are stored in the memory 440, and then stored in the memory 440. It is determined whether or not the measured value is within an allowable range from the expected value corresponding to each code (S15). If there is even one output voltage that is not within the allowable range, a determination result of “defective” is output (S9).

  In the gray scale test, in principle, all the amplifiers 101_1 to 101_m + 1 and 102_2 to 102_m + 2 are input with all codes, that is, 256 codes for 8 bits, and voltage measurement is performed. Since it is necessary to repeat data setting and voltage measurement for the number of gradations, a long time is required. In particular, when the number of gradations increases, not only the number of gradations increases, but the number of repetitions also increases, and the resolution of the voltage value per gradation becomes finer, so the stabilization waiting time (setling time) for voltage measurement becomes longer. Therefore, the test time required for the gradation test is further increased.

  When the ratio of the test time required for the gradation test to the test time of the whole non-defective / defective product test performed before the shipment to the liquid crystal display driver 100 is sufficiently short, all the amplifiers 101_1 to 101_1. It is not necessary to test for 101_m + 1, 102_2 to 102_m + 2 in parallel, and the test may be performed in multiple times within the allowable range from the number of pads required for actual operation. When the test time required for the gray scale test becomes longer and the proportion of the total becomes larger, the gray scale test shown in this embodiment minimizes the test time required for the gray scale test and increases the test cost. It is effective to suppress

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, although the liquid crystal display driver 100 is provided with the host interface 170 and the image data and the test code are input to the data latch 130, they may be transmitted by other methods. Communication with the host processor may be performed using compressed data, and image data decompressed / restored inside the liquid crystal display driver 100 may be input to the data latch. At the time of testing, for example, input may be performed via a scan chain, while a test code generation circuit may be provided inside the liquid crystal display driver 100.

  In the gradation test, voltage measurement is generally performed for all codes, that is, 256 codes for 8 bits. However, the test time may be shortened by thinning out according to an empirical rule.

1 pixel capacitance 2 pass transistor 100 liquid crystal display driver 101, 102 amplifier 110, 111, 112 gradation selection circuit 120, 121, 122 level shift circuit 130, 131, 132 data latch 140, 141, 142 gradation voltage generation circuit 150, 151 Crossbar Switch 161 Data Line Output Pad 170 Host Interface 200 Liquid Crystal Display Panel 261 Data Line Input Pad 300 Host Processor 400 Tester 411 Probe (Probe)
421 Voltage measurement unit 430 Pattern input unit 440 Memory 450 Judgment unit D1 to Dm + 1 Data line G1 to Gn Gate line S1 Gradation test S11 Step to initialize or change input code S12 Step to set input code to data latch S13 Output voltage Step S14 to store the measured value in the memory S14 Step to determine whether measurement for all the input codes is completed S15 Step to determine output voltage for all the input codes S9 Step to output

Claims (7)

Pixel capacitances arranged in n rows and m columns (n is a natural number, m is a positive even number) are connected to n gate lines for each row, and from the first column to the m-th column data line, and from the second column A liquid crystal display driver connected to a liquid crystal display panel that is alternately connected to the data line of the (m + 1) th column for each row,
Outputs the positive side voltage with reference to the common potential, does not output the negative side voltage (m + 2) / 2 positive side amplifiers, outputs the negative side voltage with reference to the common potential, and outputs the positive side voltage not output (m + 2) / 2 pieces of the negative electrode side amplifier, the at gradation test (m + 2) / 2 pieces of the positive electrode side amplifier (m + 2) / 2 pieces of m + 2 when the output voltage of the negative side amplifier is output A liquid crystal display driver comprising a plurality of pads. 2. The (m + 2) / 2 positive-polarity amplifiers according to claim 1 are first to (m + 2) / 2 positive-polarity amplifiers, and the (m + 2) / 2 negative-polarity amplifiers are first To (m + 2) / 2, and the m + 2 pads are the first to m + 2 pads,
The liquid crystal display driver further includes first to (m + 2) / 2 crossbar switches,
The i-th (i is an integer of 1 or more and (m + 2) / 2 or less) crossbar switch is selectively controlled between straight connection and cross connection,
In the straight connection, the output of the i-th positive side amplifier is connected to the second i-1 pad, the output of the i-th negative side amplifier is connected to the second i pad,
In the cross connection, the output of the i-th positive side amplifier is connected to the second i pad, and the output of the i-th negative side amplifier is connected to the 2i-1 pad.
LCD display driver. 3. The liquid crystal display driver according to claim 2, wherein the liquid crystal display driver includes a positive gradation voltage generation circuit, a negative gradation voltage generation circuit, first to m + 2 data latches, and first to m + 2 gradation selection. A circuit, and
The positive-side grayscale voltage generation circuit outputs a plurality of positive-side analog voltages with the common potential as a reference, and supplies the analog voltages to the 2i-1 grayscale selection circuit. A plurality of analog voltages on the negative electrode side are output with reference to the common potential, and supplied to the second i gradation selection circuit,
The second i-1 gradation selecting circuit selects one analog voltage from the plurality of positive-side analog voltages based on the value held in the second i-1 data latch, and the i-th positive side To the amplifier,
The second i gradation selection circuit selects one analog voltage from the plurality of analog voltages on the negative electrode side based on a value held in the second i data latch, and supplies the selected analog voltage to the i th negative amplifier. ,
LCD display driver. In Claim 3, the first to m + 1th pads are connected to the data lines of the liquid crystal display panel from the first column to the m + 1th column, respectively.
In the first field period, which is one of the odd field period and the even field period, the output of the positive amplifier is supplied to the odd-numbered data line, and the output of the negative amplifier is supplied to the even-numbered data line. In the other second field period, the output of the negative side amplifier is supplied to the odd-numbered data lines, and the output of the positive side amplifier is supplied to the even-numbered data lines. To (m + 2) / 2 crossbar switches are controlled,
In the first field period, image data to be displayed in odd rows of the liquid crystal display panel is input to the first to m + 1th data latches, and even numbers of the liquid crystal display panel are input to the second to m + 2 data latches. The image data to be displayed in a row is entered,
In the second field period, image data to be displayed in odd rows of the liquid crystal display panel is input to the second to m + 2 data latches, and even numbers of the liquid crystal display panel are input to the first to m + 1 data latches. The image data to be displayed in a row is input,
LCD display driver. The liquid crystal display driver according to claim 3, wherein the liquid crystal display driver is configured to be connectable to a test apparatus including first to m + 2 voltage measuring units and a pattern input unit,
The first to m + 2 pads are connected to the first to m + 2 voltage measuring units of the test apparatus, respectively, and the first to m + 2 data latches are connected to the input code from the pattern input unit. Configured to be able to set
LCD display driver.   4. The (m + 2) / 2 positive-side amplifiers, the (m + 2) / 2 negative-side amplifiers, the first to (m + 2) / 2 crossbar switches, and the positive electrodes A side gradation voltage generation circuit, the negative side gradation voltage generation circuit, the first to m + 2 data latches, the first to m + 2 gradation selection circuits, and the m + 2 pads. Is a liquid crystal display driver formed on a single semiconductor substrate. Pixel capacitances arranged in n rows and m columns (n is a natural number, m is a positive even number) are connected to n gate lines for each row, and from the first column to the m-th column data line, and from the second column A liquid crystal display panel that is alternately connected to the data line of the (m + 1) th column for each row;
A liquid crystal display driver for supplying a driving voltage for driving the pixel capacitance of the liquid crystal display panel to the liquid crystal display panel.
And
Among the driving voltages for driving the pixel capacitor, a positive driving voltage is output with reference to a common potential, and a negative driving voltage is not output (m + 2) / 2 positive amplifiers;
Out of the drive voltages for driving the pixel capacitors, a negative side drive voltage is output with reference to the common potential, and a positive side drive voltage is not output (m + 2) / 2 negative side amplifiers;
(M + 2) / 2 positive side amplifiers and (m + 2) / 2 negative side amplifiers output voltages of the (m + 2) / 2 negative side amplifiers at the time of a gradation test.
Liquid crystal display device.

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